Statistics
| Branch: | Revision:

root / hw / exynos4210.c @ 9bfa659e

History | View | Annotate | Download (11.5 kB)

1
/*
2
 *  Samsung exynos4210 SoC emulation
3
 *
4
 *  Copyright (c) 2011 Samsung Electronics Co., Ltd. All rights reserved.
5
 *    Maksim Kozlov <m.kozlov@samsung.com>
6
 *    Evgeny Voevodin <e.voevodin@samsung.com>
7
 *    Igor Mitsyanko  <i.mitsyanko@samsung.com>
8
 *
9
 *  This program is free software; you can redistribute it and/or modify it
10
 *  under the terms of the GNU General Public License as published by the
11
 *  Free Software Foundation; either version 2 of the License, or
12
 *  (at your option) any later version.
13
 *
14
 *  This program is distributed in the hope that it will be useful, but WITHOUT
15
 *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16
 *  FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17
 *  for more details.
18
 *
19
 *  You should have received a copy of the GNU General Public License along
20
 *  with this program; if not, see <http://www.gnu.org/licenses/>.
21
 *
22
 */
23

    
24
#include "boards.h"
25
#include "sysemu.h"
26
#include "sysbus.h"
27
#include "arm-misc.h"
28
#include "loader.h"
29
#include "exynos4210.h"
30

    
31
#define EXYNOS4210_CHIPID_ADDR         0x10000000
32

    
33
/* PWM */
34
#define EXYNOS4210_PWM_BASE_ADDR       0x139D0000
35

    
36
/* RTC */
37
#define EXYNOS4210_RTC_BASE_ADDR       0x10070000
38

    
39
/* MCT */
40
#define EXYNOS4210_MCT_BASE_ADDR       0x10050000
41

    
42
/* UART's definitions */
43
#define EXYNOS4210_UART0_BASE_ADDR     0x13800000
44
#define EXYNOS4210_UART1_BASE_ADDR     0x13810000
45
#define EXYNOS4210_UART2_BASE_ADDR     0x13820000
46
#define EXYNOS4210_UART3_BASE_ADDR     0x13830000
47
#define EXYNOS4210_UART0_FIFO_SIZE     256
48
#define EXYNOS4210_UART1_FIFO_SIZE     64
49
#define EXYNOS4210_UART2_FIFO_SIZE     16
50
#define EXYNOS4210_UART3_FIFO_SIZE     16
51
/* Interrupt Group of External Interrupt Combiner for UART */
52
#define EXYNOS4210_UART_INT_GRP        26
53

    
54
/* External GIC */
55
#define EXYNOS4210_EXT_GIC_CPU_BASE_ADDR    0x10480000
56
#define EXYNOS4210_EXT_GIC_DIST_BASE_ADDR   0x10490000
57

    
58
/* Combiner */
59
#define EXYNOS4210_EXT_COMBINER_BASE_ADDR   0x10440000
60
#define EXYNOS4210_INT_COMBINER_BASE_ADDR   0x10448000
61

    
62
/* PMU SFR base address */
63
#define EXYNOS4210_PMU_BASE_ADDR            0x10020000
64

    
65
/* Display controllers (FIMD) */
66
#define EXYNOS4210_FIMD0_BASE_ADDR          0x11C00000
67

    
68
static uint8_t chipid_and_omr[] = { 0x11, 0x02, 0x21, 0x43,
69
                                    0x09, 0x00, 0x00, 0x00 };
70

    
71
void exynos4210_write_secondary(ARMCPU *cpu,
72
        const struct arm_boot_info *info)
73
{
74
    int n;
75
    uint32_t smpboot[] = {
76
        0xe59f3024, /* ldr r3, External gic_cpu_if */
77
        0xe59f2024, /* ldr r2, Internal gic_cpu_if */
78
        0xe59f0024, /* ldr r0, startaddr */
79
        0xe3a01001, /* mov r1, #1 */
80
        0xe5821000, /* str r1, [r2] */
81
        0xe5831000, /* str r1, [r3] */
82
        0xe320f003, /* wfi */
83
        0xe5901000, /* ldr     r1, [r0] */
84
        0xe1110001, /* tst     r1, r1 */
85
        0x0afffffb, /* beq     <wfi> */
86
        0xe12fff11, /* bx      r1 */
87
        EXYNOS4210_EXT_GIC_CPU_BASE_ADDR,
88
        0,          /* gic_cpu_if: base address of Internal GIC CPU interface */
89
        0           /* bootreg: Boot register address is held here */
90
    };
91
    smpboot[ARRAY_SIZE(smpboot) - 1] = info->smp_bootreg_addr;
92
    smpboot[ARRAY_SIZE(smpboot) - 2] = info->gic_cpu_if_addr;
93
    for (n = 0; n < ARRAY_SIZE(smpboot); n++) {
94
        smpboot[n] = tswap32(smpboot[n]);
95
    }
96
    rom_add_blob_fixed("smpboot", smpboot, sizeof(smpboot),
97
                       info->smp_loader_start);
98
}
99

    
100
Exynos4210State *exynos4210_init(MemoryRegion *system_mem,
101
        unsigned long ram_size)
102
{
103
    qemu_irq cpu_irq[EXYNOS4210_NCPUS];
104
    int i, n;
105
    Exynos4210State *s = g_new(Exynos4210State, 1);
106
    qemu_irq *irqp;
107
    qemu_irq gate_irq[EXYNOS4210_NCPUS][EXYNOS4210_IRQ_GATE_NINPUTS];
108
    unsigned long mem_size;
109
    DeviceState *dev;
110
    SysBusDevice *busdev;
111

    
112
    for (n = 0; n < EXYNOS4210_NCPUS; n++) {
113
        s->cpu[n] = cpu_arm_init("cortex-a9");
114
        if (!s->cpu[n]) {
115
            fprintf(stderr, "Unable to find CPU %d definition\n", n);
116
            exit(1);
117
        }
118

    
119
        /* Create PIC controller for each processor instance */
120
        irqp = arm_pic_init_cpu(s->cpu[n]);
121

    
122
        /*
123
         * Get GICs gpio_in cpu_irq to connect a combiner to them later.
124
         * Use only IRQ for a while.
125
         */
126
        cpu_irq[n] = irqp[ARM_PIC_CPU_IRQ];
127
    }
128

    
129
    /*** IRQs ***/
130

    
131
    s->irq_table = exynos4210_init_irq(&s->irqs);
132

    
133
    /* IRQ Gate */
134
    for (i = 0; i < EXYNOS4210_NCPUS; i++) {
135
        dev = qdev_create(NULL, "exynos4210.irq_gate");
136
        qdev_prop_set_uint32(dev, "n_in", EXYNOS4210_IRQ_GATE_NINPUTS);
137
        qdev_init_nofail(dev);
138
        /* Get IRQ Gate input in gate_irq */
139
        for (n = 0; n < EXYNOS4210_IRQ_GATE_NINPUTS; n++) {
140
            gate_irq[i][n] = qdev_get_gpio_in(dev, n);
141
        }
142
        busdev = sysbus_from_qdev(dev);
143

    
144
        /* Connect IRQ Gate output to cpu_irq */
145
        sysbus_connect_irq(busdev, 0, cpu_irq[i]);
146
    }
147

    
148
    /* Private memory region and Internal GIC */
149
    dev = qdev_create(NULL, "a9mpcore_priv");
150
    qdev_prop_set_uint32(dev, "num-cpu", EXYNOS4210_NCPUS);
151
    qdev_init_nofail(dev);
152
    busdev = sysbus_from_qdev(dev);
153
    sysbus_mmio_map(busdev, 0, EXYNOS4210_SMP_PRIVATE_BASE_ADDR);
154
    for (n = 0; n < EXYNOS4210_NCPUS; n++) {
155
        sysbus_connect_irq(busdev, n, gate_irq[n][0]);
156
    }
157
    for (n = 0; n < EXYNOS4210_INT_GIC_NIRQ; n++) {
158
        s->irqs.int_gic_irq[n] = qdev_get_gpio_in(dev, n);
159
    }
160

    
161
    /* Cache controller */
162
    sysbus_create_simple("l2x0", EXYNOS4210_L2X0_BASE_ADDR, NULL);
163

    
164
    /* External GIC */
165
    dev = qdev_create(NULL, "exynos4210.gic");
166
    qdev_prop_set_uint32(dev, "num-cpu", EXYNOS4210_NCPUS);
167
    qdev_init_nofail(dev);
168
    busdev = sysbus_from_qdev(dev);
169
    /* Map CPU interface */
170
    sysbus_mmio_map(busdev, 0, EXYNOS4210_EXT_GIC_CPU_BASE_ADDR);
171
    /* Map Distributer interface */
172
    sysbus_mmio_map(busdev, 1, EXYNOS4210_EXT_GIC_DIST_BASE_ADDR);
173
    for (n = 0; n < EXYNOS4210_NCPUS; n++) {
174
        sysbus_connect_irq(busdev, n, gate_irq[n][1]);
175
    }
176
    for (n = 0; n < EXYNOS4210_EXT_GIC_NIRQ; n++) {
177
        s->irqs.ext_gic_irq[n] = qdev_get_gpio_in(dev, n);
178
    }
179

    
180
    /* Internal Interrupt Combiner */
181
    dev = qdev_create(NULL, "exynos4210.combiner");
182
    qdev_init_nofail(dev);
183
    busdev = sysbus_from_qdev(dev);
184
    for (n = 0; n < EXYNOS4210_MAX_INT_COMBINER_OUT_IRQ; n++) {
185
        sysbus_connect_irq(busdev, n, s->irqs.int_gic_irq[n]);
186
    }
187
    exynos4210_combiner_get_gpioin(&s->irqs, dev, 0);
188
    sysbus_mmio_map(busdev, 0, EXYNOS4210_INT_COMBINER_BASE_ADDR);
189

    
190
    /* External Interrupt Combiner */
191
    dev = qdev_create(NULL, "exynos4210.combiner");
192
    qdev_prop_set_uint32(dev, "external", 1);
193
    qdev_init_nofail(dev);
194
    busdev = sysbus_from_qdev(dev);
195
    for (n = 0; n < EXYNOS4210_MAX_INT_COMBINER_OUT_IRQ; n++) {
196
        sysbus_connect_irq(busdev, n, s->irqs.ext_gic_irq[n]);
197
    }
198
    exynos4210_combiner_get_gpioin(&s->irqs, dev, 1);
199
    sysbus_mmio_map(busdev, 0, EXYNOS4210_EXT_COMBINER_BASE_ADDR);
200

    
201
    /* Initialize board IRQs. */
202
    exynos4210_init_board_irqs(&s->irqs);
203

    
204
    /*** Memory ***/
205

    
206
    /* Chip-ID and OMR */
207
    memory_region_init_ram_ptr(&s->chipid_mem, "exynos4210.chipid",
208
            sizeof(chipid_and_omr), chipid_and_omr);
209
    memory_region_set_readonly(&s->chipid_mem, true);
210
    memory_region_add_subregion(system_mem, EXYNOS4210_CHIPID_ADDR,
211
                                &s->chipid_mem);
212

    
213
    /* Internal ROM */
214
    memory_region_init_ram(&s->irom_mem, "exynos4210.irom",
215
                           EXYNOS4210_IROM_SIZE);
216
    memory_region_set_readonly(&s->irom_mem, true);
217
    memory_region_add_subregion(system_mem, EXYNOS4210_IROM_BASE_ADDR,
218
                                &s->irom_mem);
219
    /* mirror of iROM */
220
    memory_region_init_alias(&s->irom_alias_mem, "exynos4210.irom_alias",
221
                             &s->irom_mem,
222
                             0,
223
                             EXYNOS4210_IROM_SIZE);
224
    memory_region_set_readonly(&s->irom_alias_mem, true);
225
    memory_region_add_subregion(system_mem, EXYNOS4210_IROM_MIRROR_BASE_ADDR,
226
                                &s->irom_alias_mem);
227

    
228
    /* Internal RAM */
229
    memory_region_init_ram(&s->iram_mem, "exynos4210.iram",
230
                           EXYNOS4210_IRAM_SIZE);
231
    vmstate_register_ram_global(&s->iram_mem);
232
    memory_region_add_subregion(system_mem, EXYNOS4210_IRAM_BASE_ADDR,
233
                                &s->iram_mem);
234

    
235
    /* DRAM */
236
    mem_size = ram_size;
237
    if (mem_size > EXYNOS4210_DRAM_MAX_SIZE) {
238
        memory_region_init_ram(&s->dram1_mem, "exynos4210.dram1",
239
                mem_size - EXYNOS4210_DRAM_MAX_SIZE);
240
        vmstate_register_ram_global(&s->dram1_mem);
241
        memory_region_add_subregion(system_mem, EXYNOS4210_DRAM1_BASE_ADDR,
242
                &s->dram1_mem);
243
        mem_size = EXYNOS4210_DRAM_MAX_SIZE;
244
    }
245
    memory_region_init_ram(&s->dram0_mem, "exynos4210.dram0", mem_size);
246
    vmstate_register_ram_global(&s->dram0_mem);
247
    memory_region_add_subregion(system_mem, EXYNOS4210_DRAM0_BASE_ADDR,
248
            &s->dram0_mem);
249

    
250
   /* PMU.
251
    * The only reason of existence at the moment is that secondary CPU boot
252
    * loader uses PMU INFORM5 register as a holding pen.
253
    */
254
    sysbus_create_simple("exynos4210.pmu", EXYNOS4210_PMU_BASE_ADDR, NULL);
255

    
256
    /* PWM */
257
    sysbus_create_varargs("exynos4210.pwm", EXYNOS4210_PWM_BASE_ADDR,
258
                          s->irq_table[exynos4210_get_irq(22, 0)],
259
                          s->irq_table[exynos4210_get_irq(22, 1)],
260
                          s->irq_table[exynos4210_get_irq(22, 2)],
261
                          s->irq_table[exynos4210_get_irq(22, 3)],
262
                          s->irq_table[exynos4210_get_irq(22, 4)],
263
                          NULL);
264
    /* RTC */
265
    sysbus_create_varargs("exynos4210.rtc", EXYNOS4210_RTC_BASE_ADDR,
266
                          s->irq_table[exynos4210_get_irq(23, 0)],
267
                          s->irq_table[exynos4210_get_irq(23, 1)],
268
                          NULL);
269

    
270
    /* Multi Core Timer */
271
    dev = qdev_create(NULL, "exynos4210.mct");
272
    qdev_init_nofail(dev);
273
    busdev = sysbus_from_qdev(dev);
274
    for (n = 0; n < 4; n++) {
275
        /* Connect global timer interrupts to Combiner gpio_in */
276
        sysbus_connect_irq(busdev, n,
277
                s->irq_table[exynos4210_get_irq(1, 4 + n)]);
278
    }
279
    /* Connect local timer interrupts to Combiner gpio_in */
280
    sysbus_connect_irq(busdev, 4,
281
            s->irq_table[exynos4210_get_irq(51, 0)]);
282
    sysbus_connect_irq(busdev, 5,
283
            s->irq_table[exynos4210_get_irq(35, 3)]);
284
    sysbus_mmio_map(busdev, 0, EXYNOS4210_MCT_BASE_ADDR);
285

    
286
    /*** UARTs ***/
287
    exynos4210_uart_create(EXYNOS4210_UART0_BASE_ADDR,
288
                           EXYNOS4210_UART0_FIFO_SIZE, 0, NULL,
289
                  s->irq_table[exynos4210_get_irq(EXYNOS4210_UART_INT_GRP, 0)]);
290

    
291
    exynos4210_uart_create(EXYNOS4210_UART1_BASE_ADDR,
292
                           EXYNOS4210_UART1_FIFO_SIZE, 1, NULL,
293
                  s->irq_table[exynos4210_get_irq(EXYNOS4210_UART_INT_GRP, 1)]);
294

    
295
    exynos4210_uart_create(EXYNOS4210_UART2_BASE_ADDR,
296
                           EXYNOS4210_UART2_FIFO_SIZE, 2, NULL,
297
                  s->irq_table[exynos4210_get_irq(EXYNOS4210_UART_INT_GRP, 2)]);
298

    
299
    exynos4210_uart_create(EXYNOS4210_UART3_BASE_ADDR,
300
                           EXYNOS4210_UART3_FIFO_SIZE, 3, NULL,
301
                  s->irq_table[exynos4210_get_irq(EXYNOS4210_UART_INT_GRP, 3)]);
302

    
303
    /*** Display controller (FIMD) ***/
304
    sysbus_create_varargs("exynos4210.fimd", EXYNOS4210_FIMD0_BASE_ADDR,
305
            s->irq_table[exynos4210_get_irq(11, 0)],
306
            s->irq_table[exynos4210_get_irq(11, 1)],
307
            s->irq_table[exynos4210_get_irq(11, 2)],
308
            NULL);
309

    
310
    return s;
311
}