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1 | 3475187d | bellard | /*
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2 | 3475187d | bellard | * QEMU Sun4u System Emulator
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3 | 3475187d | bellard | *
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4 | 3475187d | bellard | * Copyright (c) 2005 Fabrice Bellard
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5 | 3475187d | bellard | *
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6 | 3475187d | bellard | * Permission is hereby granted, free of charge, to any person obtaining a copy
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7 | 3475187d | bellard | * of this software and associated documentation files (the "Software"), to deal
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8 | 3475187d | bellard | * in the Software without restriction, including without limitation the rights
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9 | 3475187d | bellard | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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10 | 3475187d | bellard | * copies of the Software, and to permit persons to whom the Software is
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11 | 3475187d | bellard | * furnished to do so, subject to the following conditions:
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12 | 3475187d | bellard | *
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13 | 3475187d | bellard | * The above copyright notice and this permission notice shall be included in
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14 | 3475187d | bellard | * all copies or substantial portions of the Software.
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15 | 3475187d | bellard | *
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16 | 3475187d | bellard | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 | 3475187d | bellard | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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18 | 3475187d | bellard | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 | 3475187d | bellard | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 | 3475187d | bellard | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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21 | 3475187d | bellard | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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22 | 3475187d | bellard | * THE SOFTWARE.
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23 | 3475187d | bellard | */
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24 | 3475187d | bellard | #include "vl.h" |
25 | 83469015 | bellard | #include "m48t59.h" |
26 | 3475187d | bellard | |
27 | 83469015 | bellard | #define KERNEL_LOAD_ADDR 0x00404000 |
28 | 83469015 | bellard | #define CMDLINE_ADDR 0x003ff000 |
29 | 83469015 | bellard | #define INITRD_LOAD_ADDR 0x00300000 |
30 | 75956cf0 | pbrook | #define PROM_SIZE_MAX (512 * 1024) |
31 | 83469015 | bellard | #define PROM_ADDR 0x1fff0000000ULL |
32 | 83469015 | bellard | #define APB_SPECIAL_BASE 0x1fe00000000ULL |
33 | 83469015 | bellard | #define APB_MEM_BASE 0x1ff00000000ULL |
34 | 83469015 | bellard | #define VGA_BASE (APB_MEM_BASE + 0x400000ULL) |
35 | 0986ac3b | bellard | #define PROM_FILENAME "openbios-sparc64" |
36 | 83469015 | bellard | #define NVRAM_SIZE 0x2000 |
37 | 3475187d | bellard | |
38 | 3475187d | bellard | /* TSC handling */
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39 | 3475187d | bellard | |
40 | 3475187d | bellard | uint64_t cpu_get_tsc() |
41 | 3475187d | bellard | { |
42 | 3475187d | bellard | return qemu_get_clock(vm_clock);
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43 | 3475187d | bellard | } |
44 | 3475187d | bellard | |
45 | 3475187d | bellard | int DMA_get_channel_mode (int nchan) |
46 | 3475187d | bellard | { |
47 | 3475187d | bellard | return 0; |
48 | 3475187d | bellard | } |
49 | 3475187d | bellard | int DMA_read_memory (int nchan, void *buf, int pos, int size) |
50 | 3475187d | bellard | { |
51 | 3475187d | bellard | return 0; |
52 | 3475187d | bellard | } |
53 | 3475187d | bellard | int DMA_write_memory (int nchan, void *buf, int pos, int size) |
54 | 3475187d | bellard | { |
55 | 3475187d | bellard | return 0; |
56 | 3475187d | bellard | } |
57 | 3475187d | bellard | void DMA_hold_DREQ (int nchan) {} |
58 | 3475187d | bellard | void DMA_release_DREQ (int nchan) {} |
59 | 3475187d | bellard | void DMA_schedule(int nchan) {} |
60 | 3475187d | bellard | void DMA_run (void) {} |
61 | 3475187d | bellard | void DMA_init (int high_page_enable) {} |
62 | 3475187d | bellard | void DMA_register_channel (int nchan, |
63 | 3475187d | bellard | DMA_transfer_handler transfer_handler, |
64 | 3475187d | bellard | void *opaque)
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65 | 3475187d | bellard | { |
66 | 3475187d | bellard | } |
67 | 3475187d | bellard | |
68 | 83469015 | bellard | /* NVRAM helpers */
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69 | 83469015 | bellard | void NVRAM_set_byte (m48t59_t *nvram, uint32_t addr, uint8_t value)
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70 | 3475187d | bellard | { |
71 | 819385c5 | bellard | m48t59_write(nvram, addr, value); |
72 | 3475187d | bellard | } |
73 | 3475187d | bellard | |
74 | 83469015 | bellard | uint8_t NVRAM_get_byte (m48t59_t *nvram, uint32_t addr) |
75 | 3475187d | bellard | { |
76 | 819385c5 | bellard | return m48t59_read(nvram, addr);
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77 | 3475187d | bellard | } |
78 | 3475187d | bellard | |
79 | 83469015 | bellard | void NVRAM_set_word (m48t59_t *nvram, uint32_t addr, uint16_t value)
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80 | 83469015 | bellard | { |
81 | 819385c5 | bellard | m48t59_write(nvram, addr, value >> 8);
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82 | 819385c5 | bellard | m48t59_write(nvram, addr + 1, value & 0xFF); |
83 | 83469015 | bellard | } |
84 | 83469015 | bellard | |
85 | 83469015 | bellard | uint16_t NVRAM_get_word (m48t59_t *nvram, uint32_t addr) |
86 | 83469015 | bellard | { |
87 | 83469015 | bellard | uint16_t tmp; |
88 | 83469015 | bellard | |
89 | 819385c5 | bellard | tmp = m48t59_read(nvram, addr) << 8;
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90 | 819385c5 | bellard | tmp |= m48t59_read(nvram, addr + 1);
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91 | 83469015 | bellard | |
92 | 83469015 | bellard | return tmp;
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93 | 83469015 | bellard | } |
94 | 83469015 | bellard | |
95 | 83469015 | bellard | void NVRAM_set_lword (m48t59_t *nvram, uint32_t addr, uint32_t value)
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96 | 83469015 | bellard | { |
97 | 819385c5 | bellard | m48t59_write(nvram, addr, value >> 24);
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98 | 819385c5 | bellard | m48t59_write(nvram, addr + 1, (value >> 16) & 0xFF); |
99 | 819385c5 | bellard | m48t59_write(nvram, addr + 2, (value >> 8) & 0xFF); |
100 | 819385c5 | bellard | m48t59_write(nvram, addr + 3, value & 0xFF); |
101 | 83469015 | bellard | } |
102 | 83469015 | bellard | |
103 | 83469015 | bellard | uint32_t NVRAM_get_lword (m48t59_t *nvram, uint32_t addr) |
104 | 83469015 | bellard | { |
105 | 83469015 | bellard | uint32_t tmp; |
106 | 83469015 | bellard | |
107 | 819385c5 | bellard | tmp = m48t59_read(nvram, addr) << 24;
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108 | 819385c5 | bellard | tmp |= m48t59_read(nvram, addr + 1) << 16; |
109 | 819385c5 | bellard | tmp |= m48t59_read(nvram, addr + 2) << 8; |
110 | 819385c5 | bellard | tmp |= m48t59_read(nvram, addr + 3);
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111 | 83469015 | bellard | |
112 | 83469015 | bellard | return tmp;
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113 | 83469015 | bellard | } |
114 | 83469015 | bellard | |
115 | 83469015 | bellard | void NVRAM_set_string (m48t59_t *nvram, uint32_t addr,
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116 | 3475187d | bellard | const unsigned char *str, uint32_t max) |
117 | 3475187d | bellard | { |
118 | 83469015 | bellard | int i;
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119 | 3475187d | bellard | |
120 | 3475187d | bellard | for (i = 0; i < max && str[i] != '\0'; i++) { |
121 | 819385c5 | bellard | m48t59_write(nvram, addr + i, str[i]); |
122 | 3475187d | bellard | } |
123 | 819385c5 | bellard | m48t59_write(nvram, addr + max - 1, '\0'); |
124 | 3475187d | bellard | } |
125 | 3475187d | bellard | |
126 | 83469015 | bellard | int NVRAM_get_string (m48t59_t *nvram, uint8_t *dst, uint16_t addr, int max) |
127 | 83469015 | bellard | { |
128 | 83469015 | bellard | int i;
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129 | 83469015 | bellard | |
130 | 83469015 | bellard | memset(dst, 0, max);
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131 | 83469015 | bellard | for (i = 0; i < max; i++) { |
132 | 83469015 | bellard | dst[i] = NVRAM_get_byte(nvram, addr + i); |
133 | 83469015 | bellard | if (dst[i] == '\0') |
134 | 83469015 | bellard | break;
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135 | 83469015 | bellard | } |
136 | 83469015 | bellard | |
137 | 83469015 | bellard | return i;
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138 | 83469015 | bellard | } |
139 | 83469015 | bellard | |
140 | 83469015 | bellard | static uint16_t NVRAM_crc_update (uint16_t prev, uint16_t value)
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141 | 83469015 | bellard | { |
142 | 83469015 | bellard | uint16_t tmp; |
143 | 83469015 | bellard | uint16_t pd, pd1, pd2; |
144 | 83469015 | bellard | |
145 | 83469015 | bellard | tmp = prev >> 8;
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146 | 83469015 | bellard | pd = prev ^ value; |
147 | 83469015 | bellard | pd1 = pd & 0x000F;
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148 | 83469015 | bellard | pd2 = ((pd >> 4) & 0x000F) ^ pd1; |
149 | 83469015 | bellard | tmp ^= (pd1 << 3) | (pd1 << 8); |
150 | 83469015 | bellard | tmp ^= pd2 | (pd2 << 7) | (pd2 << 12); |
151 | 83469015 | bellard | |
152 | 83469015 | bellard | return tmp;
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153 | 83469015 | bellard | } |
154 | 83469015 | bellard | |
155 | 83469015 | bellard | uint16_t NVRAM_compute_crc (m48t59_t *nvram, uint32_t start, uint32_t count) |
156 | 83469015 | bellard | { |
157 | 83469015 | bellard | uint32_t i; |
158 | 83469015 | bellard | uint16_t crc = 0xFFFF;
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159 | 83469015 | bellard | int odd;
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160 | 83469015 | bellard | |
161 | 83469015 | bellard | odd = count & 1;
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162 | 83469015 | bellard | count &= ~1;
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163 | 83469015 | bellard | for (i = 0; i != count; i++) { |
164 | 83469015 | bellard | crc = NVRAM_crc_update(crc, NVRAM_get_word(nvram, start + i)); |
165 | 83469015 | bellard | } |
166 | 83469015 | bellard | if (odd) {
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167 | 83469015 | bellard | crc = NVRAM_crc_update(crc, NVRAM_get_byte(nvram, start + i) << 8);
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168 | 83469015 | bellard | } |
169 | 83469015 | bellard | |
170 | 83469015 | bellard | return crc;
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171 | 83469015 | bellard | } |
172 | 3475187d | bellard | |
173 | 3475187d | bellard | extern int nographic; |
174 | 3475187d | bellard | |
175 | 83469015 | bellard | int sun4u_NVRAM_set_params (m48t59_t *nvram, uint16_t NVRAM_size,
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176 | 83469015 | bellard | const unsigned char *arch, |
177 | 83469015 | bellard | uint32_t RAM_size, int boot_device,
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178 | 83469015 | bellard | uint32_t kernel_image, uint32_t kernel_size, |
179 | 83469015 | bellard | const char *cmdline, |
180 | 83469015 | bellard | uint32_t initrd_image, uint32_t initrd_size, |
181 | 83469015 | bellard | uint32_t NVRAM_image, |
182 | 83469015 | bellard | int width, int height, int depth) |
183 | 83469015 | bellard | { |
184 | 83469015 | bellard | uint16_t crc; |
185 | 83469015 | bellard | |
186 | 83469015 | bellard | /* Set parameters for Open Hack'Ware BIOS */
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187 | 83469015 | bellard | NVRAM_set_string(nvram, 0x00, "QEMU_BIOS", 16); |
188 | 83469015 | bellard | NVRAM_set_lword(nvram, 0x10, 0x00000002); /* structure v2 */ |
189 | 83469015 | bellard | NVRAM_set_word(nvram, 0x14, NVRAM_size);
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190 | 83469015 | bellard | NVRAM_set_string(nvram, 0x20, arch, 16); |
191 | 83469015 | bellard | NVRAM_set_byte(nvram, 0x2f, nographic & 0xff); |
192 | 83469015 | bellard | NVRAM_set_lword(nvram, 0x30, RAM_size);
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193 | 83469015 | bellard | NVRAM_set_byte(nvram, 0x34, boot_device);
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194 | 83469015 | bellard | NVRAM_set_lword(nvram, 0x38, kernel_image);
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195 | 83469015 | bellard | NVRAM_set_lword(nvram, 0x3C, kernel_size);
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196 | 3475187d | bellard | if (cmdline) {
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197 | 83469015 | bellard | /* XXX: put the cmdline in NVRAM too ? */
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198 | 83469015 | bellard | strcpy(phys_ram_base + CMDLINE_ADDR, cmdline); |
199 | 83469015 | bellard | NVRAM_set_lword(nvram, 0x40, CMDLINE_ADDR);
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200 | 83469015 | bellard | NVRAM_set_lword(nvram, 0x44, strlen(cmdline));
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201 | 83469015 | bellard | } else {
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202 | 83469015 | bellard | NVRAM_set_lword(nvram, 0x40, 0); |
203 | 83469015 | bellard | NVRAM_set_lword(nvram, 0x44, 0); |
204 | 3475187d | bellard | } |
205 | 83469015 | bellard | NVRAM_set_lword(nvram, 0x48, initrd_image);
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206 | 83469015 | bellard | NVRAM_set_lword(nvram, 0x4C, initrd_size);
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207 | 83469015 | bellard | NVRAM_set_lword(nvram, 0x50, NVRAM_image);
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208 | 83469015 | bellard | |
209 | 83469015 | bellard | NVRAM_set_word(nvram, 0x54, width);
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210 | 83469015 | bellard | NVRAM_set_word(nvram, 0x56, height);
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211 | 83469015 | bellard | NVRAM_set_word(nvram, 0x58, depth);
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212 | 83469015 | bellard | crc = NVRAM_compute_crc(nvram, 0x00, 0xF8); |
213 | 83469015 | bellard | NVRAM_set_word(nvram, 0xFC, crc);
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214 | 83469015 | bellard | |
215 | 83469015 | bellard | return 0; |
216 | 3475187d | bellard | } |
217 | 3475187d | bellard | |
218 | 3475187d | bellard | void pic_info()
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219 | 3475187d | bellard | { |
220 | 3475187d | bellard | } |
221 | 3475187d | bellard | |
222 | 3475187d | bellard | void irq_info()
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223 | 3475187d | bellard | { |
224 | 3475187d | bellard | } |
225 | 3475187d | bellard | |
226 | 83469015 | bellard | void qemu_system_powerdown(void) |
227 | 3475187d | bellard | { |
228 | 3475187d | bellard | } |
229 | 3475187d | bellard | |
230 | c68ea704 | bellard | static void main_cpu_reset(void *opaque) |
231 | c68ea704 | bellard | { |
232 | c68ea704 | bellard | CPUState *env = opaque; |
233 | c68ea704 | bellard | cpu_reset(env); |
234 | c68ea704 | bellard | } |
235 | c68ea704 | bellard | |
236 | 83469015 | bellard | static const int ide_iobase[2] = { 0x1f0, 0x170 }; |
237 | 83469015 | bellard | static const int ide_iobase2[2] = { 0x3f6, 0x376 }; |
238 | 83469015 | bellard | static const int ide_irq[2] = { 14, 15 }; |
239 | 3475187d | bellard | |
240 | 83469015 | bellard | static const int serial_io[MAX_SERIAL_PORTS] = { 0x3f8, 0x2f8, 0x3e8, 0x2e8 }; |
241 | 83469015 | bellard | static const int serial_irq[MAX_SERIAL_PORTS] = { 4, 3, 4, 3 }; |
242 | 83469015 | bellard | |
243 | 83469015 | bellard | static const int parallel_io[MAX_PARALLEL_PORTS] = { 0x378, 0x278, 0x3bc }; |
244 | 83469015 | bellard | static const int parallel_irq[MAX_PARALLEL_PORTS] = { 7, 7, 7 }; |
245 | 83469015 | bellard | |
246 | 83469015 | bellard | static fdctrl_t *floppy_controller;
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247 | 3475187d | bellard | |
248 | 3475187d | bellard | /* Sun4u hardware initialisation */
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249 | 3475187d | bellard | static void sun4u_init(int ram_size, int vga_ram_size, int boot_device, |
250 | 3475187d | bellard | DisplayState *ds, const char **fd_filename, int snapshot, |
251 | 3475187d | bellard | const char *kernel_filename, const char *kernel_cmdline, |
252 | 94fc95cd | j_mayer | const char *initrd_filename, const char *cpu_model) |
253 | 3475187d | bellard | { |
254 | c68ea704 | bellard | CPUState *env; |
255 | 3475187d | bellard | char buf[1024]; |
256 | 83469015 | bellard | m48t59_t *nvram; |
257 | 3475187d | bellard | int ret, linux_boot;
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258 | 3475187d | bellard | unsigned int i; |
259 | 83469015 | bellard | long prom_offset, initrd_size, kernel_size;
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260 | 83469015 | bellard | PCIBus *pci_bus; |
261 | 62724a37 | blueswir1 | const sparc_def_t *def;
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262 | 3475187d | bellard | |
263 | 3475187d | bellard | linux_boot = (kernel_filename != NULL);
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264 | 3475187d | bellard | |
265 | 62724a37 | blueswir1 | /* init CPUs */
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266 | 62724a37 | blueswir1 | if (cpu_model == NULL) |
267 | 62724a37 | blueswir1 | cpu_model = "TI UltraSparc II";
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268 | 62724a37 | blueswir1 | sparc_find_by_name(cpu_model, &def); |
269 | 62724a37 | blueswir1 | if (def == NULL) { |
270 | 62724a37 | blueswir1 | fprintf(stderr, "Unable to find Sparc CPU definition\n");
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271 | 62724a37 | blueswir1 | exit(1);
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272 | 62724a37 | blueswir1 | } |
273 | c68ea704 | bellard | env = cpu_init(); |
274 | 62724a37 | blueswir1 | cpu_sparc_register(env, def); |
275 | c68ea704 | bellard | register_savevm("cpu", 0, 3, cpu_save, cpu_load, env); |
276 | c68ea704 | bellard | qemu_register_reset(main_cpu_reset, env); |
277 | c68ea704 | bellard | |
278 | 3475187d | bellard | /* allocate RAM */
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279 | 3475187d | bellard | cpu_register_physical_memory(0, ram_size, 0); |
280 | 3475187d | bellard | |
281 | 83469015 | bellard | prom_offset = ram_size + vga_ram_size; |
282 | b3783731 | bellard | cpu_register_physical_memory(PROM_ADDR, |
283 | b3783731 | bellard | (PROM_SIZE_MAX + TARGET_PAGE_SIZE) & TARGET_PAGE_MASK, |
284 | b3783731 | bellard | prom_offset | IO_MEM_ROM); |
285 | 3475187d | bellard | |
286 | 0986ac3b | bellard | snprintf(buf, sizeof(buf), "%s/%s", bios_dir, PROM_FILENAME); |
287 | 74287114 | ths | ret = load_elf(buf, 0, NULL, NULL, NULL); |
288 | 3475187d | bellard | if (ret < 0) { |
289 | 3475187d | bellard | fprintf(stderr, "qemu: could not load prom '%s'\n",
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290 | 3475187d | bellard | buf); |
291 | 3475187d | bellard | exit(1);
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292 | 3475187d | bellard | } |
293 | 3475187d | bellard | |
294 | 3475187d | bellard | kernel_size = 0;
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295 | 83469015 | bellard | initrd_size = 0;
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296 | 3475187d | bellard | if (linux_boot) {
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297 | b3783731 | bellard | /* XXX: put correct offset */
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298 | 74287114 | ths | kernel_size = load_elf(kernel_filename, 0, NULL, NULL, NULL); |
299 | 3475187d | bellard | if (kernel_size < 0) |
300 | 3475187d | bellard | kernel_size = load_aout(kernel_filename, phys_ram_base + KERNEL_LOAD_ADDR); |
301 | 3475187d | bellard | if (kernel_size < 0) |
302 | 3475187d | bellard | kernel_size = load_image(kernel_filename, phys_ram_base + KERNEL_LOAD_ADDR); |
303 | 3475187d | bellard | if (kernel_size < 0) { |
304 | 3475187d | bellard | fprintf(stderr, "qemu: could not load kernel '%s'\n",
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305 | 3475187d | bellard | kernel_filename); |
306 | 3475187d | bellard | exit(1);
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307 | 3475187d | bellard | } |
308 | 3475187d | bellard | |
309 | 3475187d | bellard | /* load initrd */
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310 | 3475187d | bellard | if (initrd_filename) {
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311 | 3475187d | bellard | initrd_size = load_image(initrd_filename, phys_ram_base + INITRD_LOAD_ADDR); |
312 | 3475187d | bellard | if (initrd_size < 0) { |
313 | 3475187d | bellard | fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
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314 | 3475187d | bellard | initrd_filename); |
315 | 3475187d | bellard | exit(1);
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316 | 3475187d | bellard | } |
317 | 3475187d | bellard | } |
318 | 3475187d | bellard | if (initrd_size > 0) { |
319 | 3475187d | bellard | for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) { |
320 | 3475187d | bellard | if (ldl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i)
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321 | 3475187d | bellard | == 0x48647253) { // HdrS |
322 | 3475187d | bellard | stl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i + 16, INITRD_LOAD_ADDR);
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323 | 3475187d | bellard | stl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i + 20, initrd_size);
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324 | 3475187d | bellard | break;
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325 | 3475187d | bellard | } |
326 | 3475187d | bellard | } |
327 | 3475187d | bellard | } |
328 | 3475187d | bellard | } |
329 | 502a5395 | pbrook | pci_bus = pci_apb_init(APB_SPECIAL_BASE, APB_MEM_BASE, NULL);
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330 | 83469015 | bellard | isa_mem_base = VGA_BASE; |
331 | 75956cf0 | pbrook | pci_cirrus_vga_init(pci_bus, ds, phys_ram_base + ram_size, ram_size, vga_ram_size); |
332 | 83469015 | bellard | |
333 | 83469015 | bellard | for(i = 0; i < MAX_SERIAL_PORTS; i++) { |
334 | 83469015 | bellard | if (serial_hds[i]) {
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335 | d537cf6c | pbrook | serial_init(serial_io[i], NULL/*serial_irq[i]*/, serial_hds[i]); |
336 | 83469015 | bellard | } |
337 | 83469015 | bellard | } |
338 | 83469015 | bellard | |
339 | 83469015 | bellard | for(i = 0; i < MAX_PARALLEL_PORTS; i++) { |
340 | 83469015 | bellard | if (parallel_hds[i]) {
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341 | d537cf6c | pbrook | parallel_init(parallel_io[i], NULL/*parallel_irq[i]*/, parallel_hds[i]); |
342 | 83469015 | bellard | } |
343 | 83469015 | bellard | } |
344 | 83469015 | bellard | |
345 | 83469015 | bellard | for(i = 0; i < nb_nics; i++) { |
346 | a41b2ff2 | pbrook | if (!nd_table[i].model)
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347 | a41b2ff2 | pbrook | nd_table[i].model = "ne2k_pci";
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348 | abcebc7e | ths | pci_nic_init(pci_bus, &nd_table[i], -1);
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349 | 83469015 | bellard | } |
350 | 83469015 | bellard | |
351 | 83469015 | bellard | pci_cmd646_ide_init(pci_bus, bs_table, 1);
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352 | d537cf6c | pbrook | /* FIXME: wire up interrupts. */
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353 | d537cf6c | pbrook | i8042_init(NULL/*1*/, NULL/*12*/, 0x60); |
354 | d537cf6c | pbrook | floppy_controller = fdctrl_init(NULL/*6*/, 2, 0, 0x3f0, fd_table); |
355 | d537cf6c | pbrook | nvram = m48t59_init(NULL/*8*/, 0, 0x0074, NVRAM_SIZE, 59); |
356 | 83469015 | bellard | sun4u_NVRAM_set_params(nvram, NVRAM_SIZE, "Sun4u", ram_size, boot_device,
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357 | 83469015 | bellard | KERNEL_LOAD_ADDR, kernel_size, |
358 | 83469015 | bellard | kernel_cmdline, |
359 | 83469015 | bellard | INITRD_LOAD_ADDR, initrd_size, |
360 | 83469015 | bellard | /* XXX: need an option to load a NVRAM image */
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361 | 83469015 | bellard | 0,
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362 | 83469015 | bellard | graphic_width, graphic_height, graphic_depth); |
363 | 83469015 | bellard | |
364 | 3475187d | bellard | } |
365 | 3475187d | bellard | |
366 | 3475187d | bellard | QEMUMachine sun4u_machine = { |
367 | 3475187d | bellard | "sun4u",
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368 | 3475187d | bellard | "Sun4u platform",
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369 | 3475187d | bellard | sun4u_init, |
370 | 3475187d | bellard | }; |