root / hw / spapr_hcall.c @ 9c17d615
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#include "sysemu/sysemu.h" |
|---|---|
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#include "cpu.h" |
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#include "sysemu/sysemu.h" |
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#include "helper_regs.h" |
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#include "hw/spapr.h" |
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|
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#define HPTES_PER_GROUP 8 |
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|
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#define HPTE_V_SSIZE_SHIFT 62 |
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#define HPTE_V_AVPN_SHIFT 7 |
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#define HPTE_V_AVPN 0x3fffffffffffff80ULL |
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#define HPTE_V_AVPN_VAL(x) (((x) & HPTE_V_AVPN) >> HPTE_V_AVPN_SHIFT)
|
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#define HPTE_V_COMPARE(x, y) (!(((x) ^ (y)) & 0xffffffffffffff80UL)) |
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#define HPTE_V_BOLTED 0x0000000000000010ULL |
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#define HPTE_V_LOCK 0x0000000000000008ULL |
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#define HPTE_V_LARGE 0x0000000000000004ULL |
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#define HPTE_V_SECONDARY 0x0000000000000002ULL |
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#define HPTE_V_VALID 0x0000000000000001ULL |
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|
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#define HPTE_R_PP0 0x8000000000000000ULL |
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#define HPTE_R_TS 0x4000000000000000ULL |
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#define HPTE_R_KEY_HI 0x3000000000000000ULL |
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#define HPTE_R_RPN_SHIFT 12 |
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#define HPTE_R_RPN 0x3ffffffffffff000ULL |
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#define HPTE_R_FLAGS 0x00000000000003ffULL |
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#define HPTE_R_PP 0x0000000000000003ULL |
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#define HPTE_R_N 0x0000000000000004ULL |
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#define HPTE_R_G 0x0000000000000008ULL |
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#define HPTE_R_M 0x0000000000000010ULL |
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#define HPTE_R_I 0x0000000000000020ULL |
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#define HPTE_R_W 0x0000000000000040ULL |
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#define HPTE_R_WIMG 0x0000000000000078ULL |
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#define HPTE_R_C 0x0000000000000080ULL |
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#define HPTE_R_R 0x0000000000000100ULL |
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#define HPTE_R_KEY_LO 0x0000000000000e00ULL |
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|
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#define HPTE_V_1TB_SEG 0x4000000000000000ULL |
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#define HPTE_V_VRMA_MASK 0x4001ffffff000000ULL |
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|
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static target_ulong compute_tlbie_rb(target_ulong v, target_ulong r,
|
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target_ulong pte_index) |
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{
|
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target_ulong rb, va_low; |
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|
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rb = (v & ~0x7fULL) << 16; /* AVA field */ |
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va_low = pte_index >> 3;
|
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if (v & HPTE_V_SECONDARY) {
|
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va_low = ~va_low; |
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} |
| 50 |
/* xor vsid from AVA */
|
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if (!(v & HPTE_V_1TB_SEG)) {
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va_low ^= v >> 12;
|
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} else {
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va_low ^= v >> 24;
|
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} |
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va_low &= 0x7ff;
|
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if (v & HPTE_V_LARGE) {
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rb |= 1; /* L field */ |
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#if 0 /* Disable that P7 specific bit for now */
|
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if (r & 0xff000) {
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/* non-16MB large page, must be 64k */
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/* (masks depend on page size) */
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rb |= 0x1000; /* page encoding in LP field */
|
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rb |= (va_low & 0x7f) << 16; /* 7b of VA in AVA/LP field */
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rb |= (va_low & 0xfe); /* AVAL field */
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}
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#endif
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} else {
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/* 4kB page */
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rb |= (va_low & 0x7ff) << 12; /* remaining 11b of AVA */ |
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} |
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rb |= (v >> 54) & 0x300; /* B field */ |
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return rb;
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} |
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|
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static target_ulong h_enter(PowerPCCPU *cpu, sPAPREnvironment *spapr,
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target_ulong opcode, target_ulong *args) |
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{
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CPUPPCState *env = &cpu->env; |
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target_ulong flags = args[0];
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target_ulong pte_index = args[1];
|
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target_ulong pteh = args[2];
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target_ulong ptel = args[3];
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target_ulong page_shift = 12;
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target_ulong raddr; |
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target_ulong i; |
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uint8_t *hpte; |
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/* only handle 4k and 16M pages for now */
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if (pteh & HPTE_V_LARGE) {
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#if 0 /* We don't support 64k pages yet */
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if ((ptel & 0xf000) == 0x1000) {
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/* 64k page */
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} else
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#endif
|
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if ((ptel & 0xff000) == 0) { |
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/* 16M page */
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page_shift = 24;
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/* lowest AVA bit must be 0 for 16M pages */
|
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if (pteh & 0x80) { |
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return H_PARAMETER;
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} |
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} else {
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return H_PARAMETER;
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} |
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} |
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|
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raddr = (ptel & HPTE_R_RPN) & ~((1ULL << page_shift) - 1); |
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|
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if (raddr < spapr->ram_limit) {
|
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/* Regular RAM - should have WIMG=0010 */
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if ((ptel & HPTE_R_WIMG) != HPTE_R_M) {
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return H_PARAMETER;
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} |
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} else {
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/* Looks like an IO address */
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/* FIXME: What WIMG combinations could be sensible for IO?
|
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* For now we allow WIMG=010x, but are there others? */
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/* FIXME: Should we check against registered IO addresses? */
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if ((ptel & (HPTE_R_W | HPTE_R_I | HPTE_R_M)) != HPTE_R_I) {
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return H_PARAMETER;
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} |
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} |
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|
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pteh &= ~0x60ULL;
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|
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if ((pte_index * HASH_PTE_SIZE_64) & ~env->htab_mask) {
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return H_PARAMETER;
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} |
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if (likely((flags & H_EXACT) == 0)) { |
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pte_index &= ~7ULL;
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hpte = env->external_htab + (pte_index * HASH_PTE_SIZE_64); |
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for (i = 0; ; ++i) { |
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if (i == 8) { |
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return H_PTEG_FULL;
|
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} |
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if ((ldq_p(hpte) & HPTE_V_VALID) == 0) { |
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break;
|
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} |
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hpte += HASH_PTE_SIZE_64; |
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} |
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} else {
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i = 0;
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hpte = env->external_htab + (pte_index * HASH_PTE_SIZE_64); |
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if (ldq_p(hpte) & HPTE_V_VALID) {
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return H_PTEG_FULL;
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} |
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} |
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stq_p(hpte + (HASH_PTE_SIZE_64/2), ptel);
|
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/* eieio(); FIXME: need some sort of barrier for smp? */
|
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stq_p(hpte, pteh); |
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|
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args[0] = pte_index + i;
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return H_SUCCESS;
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} |
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|
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enum {
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REMOVE_SUCCESS = 0,
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REMOVE_NOT_FOUND = 1,
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REMOVE_PARM = 2,
|
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REMOVE_HW = 3,
|
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}; |
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|
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static target_ulong remove_hpte(CPUPPCState *env, target_ulong ptex,
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target_ulong avpn, |
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target_ulong flags, |
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target_ulong *vp, target_ulong *rp) |
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{
|
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uint8_t *hpte; |
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target_ulong v, r, rb; |
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|
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if ((ptex * HASH_PTE_SIZE_64) & ~env->htab_mask) {
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return REMOVE_PARM;
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} |
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|
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hpte = env->external_htab + (ptex * HASH_PTE_SIZE_64); |
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|
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v = ldq_p(hpte); |
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r = ldq_p(hpte + (HASH_PTE_SIZE_64/2));
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|
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if ((v & HPTE_V_VALID) == 0 || |
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((flags & H_AVPN) && (v & ~0x7fULL) != avpn) ||
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((flags & H_ANDCOND) && (v & avpn) != 0)) {
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return REMOVE_NOT_FOUND;
|
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} |
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*vp = v; |
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*rp = r; |
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stq_p(hpte, 0);
|
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rb = compute_tlbie_rb(v, r, ptex); |
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ppc_tlb_invalidate_one(env, rb); |
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return REMOVE_SUCCESS;
|
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} |
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|
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static target_ulong h_remove(PowerPCCPU *cpu, sPAPREnvironment *spapr,
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target_ulong opcode, target_ulong *args) |
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{
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CPUPPCState *env = &cpu->env; |
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target_ulong flags = args[0];
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target_ulong pte_index = args[1];
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target_ulong avpn = args[2];
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int ret;
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|
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ret = remove_hpte(env, pte_index, avpn, flags, |
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&args[0], &args[1]); |
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|
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switch (ret) {
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case REMOVE_SUCCESS:
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return H_SUCCESS;
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|
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case REMOVE_NOT_FOUND:
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return H_NOT_FOUND;
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|
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case REMOVE_PARM:
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return H_PARAMETER;
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|
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case REMOVE_HW:
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return H_HARDWARE;
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} |
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|
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assert(0);
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} |
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|
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#define H_BULK_REMOVE_TYPE 0xc000000000000000ULL |
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#define H_BULK_REMOVE_REQUEST 0x4000000000000000ULL |
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#define H_BULK_REMOVE_RESPONSE 0x8000000000000000ULL |
| 226 |
#define H_BULK_REMOVE_END 0xc000000000000000ULL |
| 227 |
#define H_BULK_REMOVE_CODE 0x3000000000000000ULL |
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#define H_BULK_REMOVE_SUCCESS 0x0000000000000000ULL |
| 229 |
#define H_BULK_REMOVE_NOT_FOUND 0x1000000000000000ULL |
| 230 |
#define H_BULK_REMOVE_PARM 0x2000000000000000ULL |
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#define H_BULK_REMOVE_HW 0x3000000000000000ULL |
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#define H_BULK_REMOVE_RC 0x0c00000000000000ULL |
| 233 |
#define H_BULK_REMOVE_FLAGS 0x0300000000000000ULL |
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#define H_BULK_REMOVE_ABSOLUTE 0x0000000000000000ULL |
| 235 |
#define H_BULK_REMOVE_ANDCOND 0x0100000000000000ULL |
| 236 |
#define H_BULK_REMOVE_AVPN 0x0200000000000000ULL |
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#define H_BULK_REMOVE_PTEX 0x00ffffffffffffffULL |
| 238 |
|
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#define H_BULK_REMOVE_MAX_BATCH 4 |
| 240 |
|
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static target_ulong h_bulk_remove(PowerPCCPU *cpu, sPAPREnvironment *spapr,
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target_ulong opcode, target_ulong *args) |
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{
|
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CPUPPCState *env = &cpu->env; |
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int i;
|
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|
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for (i = 0; i < H_BULK_REMOVE_MAX_BATCH; i++) { |
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target_ulong *tsh = &args[i*2];
|
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target_ulong tsl = args[i*2 + 1]; |
| 250 |
target_ulong v, r, ret; |
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|
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if ((*tsh & H_BULK_REMOVE_TYPE) == H_BULK_REMOVE_END) {
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break;
|
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} else if ((*tsh & H_BULK_REMOVE_TYPE) != H_BULK_REMOVE_REQUEST) { |
| 255 |
return H_PARAMETER;
|
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} |
| 257 |
|
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*tsh &= H_BULK_REMOVE_PTEX | H_BULK_REMOVE_FLAGS; |
| 259 |
*tsh |= H_BULK_REMOVE_RESPONSE; |
| 260 |
|
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if ((*tsh & H_BULK_REMOVE_ANDCOND) && (*tsh & H_BULK_REMOVE_AVPN)) {
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*tsh |= H_BULK_REMOVE_PARM; |
| 263 |
return H_PARAMETER;
|
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} |
| 265 |
|
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ret = remove_hpte(env, *tsh & H_BULK_REMOVE_PTEX, tsl, |
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(*tsh & H_BULK_REMOVE_FLAGS) >> 26,
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&v, &r); |
| 269 |
|
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*tsh |= ret << 60;
|
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|
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switch (ret) {
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case REMOVE_SUCCESS:
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*tsh |= (r & (HPTE_R_C | HPTE_R_R)) << 43;
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break;
|
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|
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case REMOVE_PARM:
|
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return H_PARAMETER;
|
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|
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case REMOVE_HW:
|
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return H_HARDWARE;
|
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} |
| 283 |
} |
| 284 |
|
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return H_SUCCESS;
|
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} |
| 287 |
|
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static target_ulong h_protect(PowerPCCPU *cpu, sPAPREnvironment *spapr,
|
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target_ulong opcode, target_ulong *args) |
| 290 |
{
|
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CPUPPCState *env = &cpu->env; |
| 292 |
target_ulong flags = args[0];
|
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target_ulong pte_index = args[1];
|
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target_ulong avpn = args[2];
|
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uint8_t *hpte; |
| 296 |
target_ulong v, r, rb; |
| 297 |
|
| 298 |
if ((pte_index * HASH_PTE_SIZE_64) & ~env->htab_mask) {
|
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return H_PARAMETER;
|
| 300 |
} |
| 301 |
|
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hpte = env->external_htab + (pte_index * HASH_PTE_SIZE_64); |
| 303 |
|
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v = ldq_p(hpte); |
| 305 |
r = ldq_p(hpte + (HASH_PTE_SIZE_64/2));
|
| 306 |
|
| 307 |
if ((v & HPTE_V_VALID) == 0 || |
| 308 |
((flags & H_AVPN) && (v & ~0x7fULL) != avpn)) {
|
| 309 |
return H_NOT_FOUND;
|
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} |
| 311 |
|
| 312 |
r &= ~(HPTE_R_PP0 | HPTE_R_PP | HPTE_R_N | |
| 313 |
HPTE_R_KEY_HI | HPTE_R_KEY_LO); |
| 314 |
r |= (flags << 55) & HPTE_R_PP0;
|
| 315 |
r |= (flags << 48) & HPTE_R_KEY_HI;
|
| 316 |
r |= flags & (HPTE_R_PP | HPTE_R_N | HPTE_R_KEY_LO); |
| 317 |
rb = compute_tlbie_rb(v, r, pte_index); |
| 318 |
stq_p(hpte, v & ~HPTE_V_VALID); |
| 319 |
ppc_tlb_invalidate_one(env, rb); |
| 320 |
stq_p(hpte + (HASH_PTE_SIZE_64/2), r);
|
| 321 |
/* Don't need a memory barrier, due to qemu's global lock */
|
| 322 |
stq_p(hpte, v); |
| 323 |
return H_SUCCESS;
|
| 324 |
} |
| 325 |
|
| 326 |
static target_ulong h_set_dabr(PowerPCCPU *cpu, sPAPREnvironment *spapr,
|
| 327 |
target_ulong opcode, target_ulong *args) |
| 328 |
{
|
| 329 |
/* FIXME: actually implement this */
|
| 330 |
return H_HARDWARE;
|
| 331 |
} |
| 332 |
|
| 333 |
#define FLAGS_REGISTER_VPA 0x0000200000000000ULL |
| 334 |
#define FLAGS_REGISTER_DTL 0x0000400000000000ULL |
| 335 |
#define FLAGS_REGISTER_SLBSHADOW 0x0000600000000000ULL |
| 336 |
#define FLAGS_DEREGISTER_VPA 0x0000a00000000000ULL |
| 337 |
#define FLAGS_DEREGISTER_DTL 0x0000c00000000000ULL |
| 338 |
#define FLAGS_DEREGISTER_SLBSHADOW 0x0000e00000000000ULL |
| 339 |
|
| 340 |
#define VPA_MIN_SIZE 640 |
| 341 |
#define VPA_SIZE_OFFSET 0x4 |
| 342 |
#define VPA_SHARED_PROC_OFFSET 0x9 |
| 343 |
#define VPA_SHARED_PROC_VAL 0x2 |
| 344 |
|
| 345 |
static target_ulong register_vpa(CPUPPCState *env, target_ulong vpa)
|
| 346 |
{
|
| 347 |
uint16_t size; |
| 348 |
uint8_t tmp; |
| 349 |
|
| 350 |
if (vpa == 0) { |
| 351 |
hcall_dprintf("Can't cope with registering a VPA at logical 0\n");
|
| 352 |
return H_HARDWARE;
|
| 353 |
} |
| 354 |
|
| 355 |
if (vpa % env->dcache_line_size) {
|
| 356 |
return H_PARAMETER;
|
| 357 |
} |
| 358 |
/* FIXME: bounds check the address */
|
| 359 |
|
| 360 |
size = lduw_be_phys(vpa + 0x4);
|
| 361 |
|
| 362 |
if (size < VPA_MIN_SIZE) {
|
| 363 |
return H_PARAMETER;
|
| 364 |
} |
| 365 |
|
| 366 |
/* VPA is not allowed to cross a page boundary */
|
| 367 |
if ((vpa / 4096) != ((vpa + size - 1) / 4096)) { |
| 368 |
return H_PARAMETER;
|
| 369 |
} |
| 370 |
|
| 371 |
env->vpa_addr = vpa; |
| 372 |
|
| 373 |
tmp = ldub_phys(env->vpa_addr + VPA_SHARED_PROC_OFFSET); |
| 374 |
tmp |= VPA_SHARED_PROC_VAL; |
| 375 |
stb_phys(env->vpa_addr + VPA_SHARED_PROC_OFFSET, tmp); |
| 376 |
|
| 377 |
return H_SUCCESS;
|
| 378 |
} |
| 379 |
|
| 380 |
static target_ulong deregister_vpa(CPUPPCState *env, target_ulong vpa)
|
| 381 |
{
|
| 382 |
if (env->slb_shadow_addr) {
|
| 383 |
return H_RESOURCE;
|
| 384 |
} |
| 385 |
|
| 386 |
if (env->dtl_addr) {
|
| 387 |
return H_RESOURCE;
|
| 388 |
} |
| 389 |
|
| 390 |
env->vpa_addr = 0;
|
| 391 |
return H_SUCCESS;
|
| 392 |
} |
| 393 |
|
| 394 |
static target_ulong register_slb_shadow(CPUPPCState *env, target_ulong addr)
|
| 395 |
{
|
| 396 |
uint32_t size; |
| 397 |
|
| 398 |
if (addr == 0) { |
| 399 |
hcall_dprintf("Can't cope with SLB shadow at logical 0\n");
|
| 400 |
return H_HARDWARE;
|
| 401 |
} |
| 402 |
|
| 403 |
size = ldl_be_phys(addr + 0x4);
|
| 404 |
if (size < 0x8) { |
| 405 |
return H_PARAMETER;
|
| 406 |
} |
| 407 |
|
| 408 |
if ((addr / 4096) != ((addr + size - 1) / 4096)) { |
| 409 |
return H_PARAMETER;
|
| 410 |
} |
| 411 |
|
| 412 |
if (!env->vpa_addr) {
|
| 413 |
return H_RESOURCE;
|
| 414 |
} |
| 415 |
|
| 416 |
env->slb_shadow_addr = addr; |
| 417 |
env->slb_shadow_size = size; |
| 418 |
|
| 419 |
return H_SUCCESS;
|
| 420 |
} |
| 421 |
|
| 422 |
static target_ulong deregister_slb_shadow(CPUPPCState *env, target_ulong addr)
|
| 423 |
{
|
| 424 |
env->slb_shadow_addr = 0;
|
| 425 |
env->slb_shadow_size = 0;
|
| 426 |
return H_SUCCESS;
|
| 427 |
} |
| 428 |
|
| 429 |
static target_ulong register_dtl(CPUPPCState *env, target_ulong addr)
|
| 430 |
{
|
| 431 |
uint32_t size; |
| 432 |
|
| 433 |
if (addr == 0) { |
| 434 |
hcall_dprintf("Can't cope with DTL at logical 0\n");
|
| 435 |
return H_HARDWARE;
|
| 436 |
} |
| 437 |
|
| 438 |
size = ldl_be_phys(addr + 0x4);
|
| 439 |
|
| 440 |
if (size < 48) { |
| 441 |
return H_PARAMETER;
|
| 442 |
} |
| 443 |
|
| 444 |
if (!env->vpa_addr) {
|
| 445 |
return H_RESOURCE;
|
| 446 |
} |
| 447 |
|
| 448 |
env->dtl_addr = addr; |
| 449 |
env->dtl_size = size; |
| 450 |
|
| 451 |
return H_SUCCESS;
|
| 452 |
} |
| 453 |
|
| 454 |
static target_ulong deregister_dtl(CPUPPCState *env, target_ulong addr)
|
| 455 |
{
|
| 456 |
env->dtl_addr = 0;
|
| 457 |
env->dtl_size = 0;
|
| 458 |
|
| 459 |
return H_SUCCESS;
|
| 460 |
} |
| 461 |
|
| 462 |
static target_ulong h_register_vpa(PowerPCCPU *cpu, sPAPREnvironment *spapr,
|
| 463 |
target_ulong opcode, target_ulong *args) |
| 464 |
{
|
| 465 |
target_ulong flags = args[0];
|
| 466 |
target_ulong procno = args[1];
|
| 467 |
target_ulong vpa = args[2];
|
| 468 |
target_ulong ret = H_PARAMETER; |
| 469 |
CPUPPCState *tenv; |
| 470 |
|
| 471 |
for (tenv = first_cpu; tenv; tenv = tenv->next_cpu) {
|
| 472 |
if (tenv->cpu_index == procno) {
|
| 473 |
break;
|
| 474 |
} |
| 475 |
} |
| 476 |
|
| 477 |
if (!tenv) {
|
| 478 |
return H_PARAMETER;
|
| 479 |
} |
| 480 |
|
| 481 |
switch (flags) {
|
| 482 |
case FLAGS_REGISTER_VPA:
|
| 483 |
ret = register_vpa(tenv, vpa); |
| 484 |
break;
|
| 485 |
|
| 486 |
case FLAGS_DEREGISTER_VPA:
|
| 487 |
ret = deregister_vpa(tenv, vpa); |
| 488 |
break;
|
| 489 |
|
| 490 |
case FLAGS_REGISTER_SLBSHADOW:
|
| 491 |
ret = register_slb_shadow(tenv, vpa); |
| 492 |
break;
|
| 493 |
|
| 494 |
case FLAGS_DEREGISTER_SLBSHADOW:
|
| 495 |
ret = deregister_slb_shadow(tenv, vpa); |
| 496 |
break;
|
| 497 |
|
| 498 |
case FLAGS_REGISTER_DTL:
|
| 499 |
ret = register_dtl(tenv, vpa); |
| 500 |
break;
|
| 501 |
|
| 502 |
case FLAGS_DEREGISTER_DTL:
|
| 503 |
ret = deregister_dtl(tenv, vpa); |
| 504 |
break;
|
| 505 |
} |
| 506 |
|
| 507 |
return ret;
|
| 508 |
} |
| 509 |
|
| 510 |
static target_ulong h_cede(PowerPCCPU *cpu, sPAPREnvironment *spapr,
|
| 511 |
target_ulong opcode, target_ulong *args) |
| 512 |
{
|
| 513 |
CPUPPCState *env = &cpu->env; |
| 514 |
|
| 515 |
env->msr |= (1ULL << MSR_EE);
|
| 516 |
hreg_compute_hflags(env); |
| 517 |
if (!cpu_has_work(CPU(cpu))) {
|
| 518 |
env->halted = 1;
|
| 519 |
env->exception_index = EXCP_HLT; |
| 520 |
env->exit_request = 1;
|
| 521 |
} |
| 522 |
return H_SUCCESS;
|
| 523 |
} |
| 524 |
|
| 525 |
static target_ulong h_rtas(PowerPCCPU *cpu, sPAPREnvironment *spapr,
|
| 526 |
target_ulong opcode, target_ulong *args) |
| 527 |
{
|
| 528 |
target_ulong rtas_r3 = args[0];
|
| 529 |
uint32_t token = ldl_be_phys(rtas_r3); |
| 530 |
uint32_t nargs = ldl_be_phys(rtas_r3 + 4);
|
| 531 |
uint32_t nret = ldl_be_phys(rtas_r3 + 8);
|
| 532 |
|
| 533 |
return spapr_rtas_call(spapr, token, nargs, rtas_r3 + 12, |
| 534 |
nret, rtas_r3 + 12 + 4*nargs); |
| 535 |
} |
| 536 |
|
| 537 |
static target_ulong h_logical_load(PowerPCCPU *cpu, sPAPREnvironment *spapr,
|
| 538 |
target_ulong opcode, target_ulong *args) |
| 539 |
{
|
| 540 |
target_ulong size = args[0];
|
| 541 |
target_ulong addr = args[1];
|
| 542 |
|
| 543 |
switch (size) {
|
| 544 |
case 1: |
| 545 |
args[0] = ldub_phys(addr);
|
| 546 |
return H_SUCCESS;
|
| 547 |
case 2: |
| 548 |
args[0] = lduw_phys(addr);
|
| 549 |
return H_SUCCESS;
|
| 550 |
case 4: |
| 551 |
args[0] = ldl_phys(addr);
|
| 552 |
return H_SUCCESS;
|
| 553 |
case 8: |
| 554 |
args[0] = ldq_phys(addr);
|
| 555 |
return H_SUCCESS;
|
| 556 |
} |
| 557 |
return H_PARAMETER;
|
| 558 |
} |
| 559 |
|
| 560 |
static target_ulong h_logical_store(PowerPCCPU *cpu, sPAPREnvironment *spapr,
|
| 561 |
target_ulong opcode, target_ulong *args) |
| 562 |
{
|
| 563 |
target_ulong size = args[0];
|
| 564 |
target_ulong addr = args[1];
|
| 565 |
target_ulong val = args[2];
|
| 566 |
|
| 567 |
switch (size) {
|
| 568 |
case 1: |
| 569 |
stb_phys(addr, val); |
| 570 |
return H_SUCCESS;
|
| 571 |
case 2: |
| 572 |
stw_phys(addr, val); |
| 573 |
return H_SUCCESS;
|
| 574 |
case 4: |
| 575 |
stl_phys(addr, val); |
| 576 |
return H_SUCCESS;
|
| 577 |
case 8: |
| 578 |
stq_phys(addr, val); |
| 579 |
return H_SUCCESS;
|
| 580 |
} |
| 581 |
return H_PARAMETER;
|
| 582 |
} |
| 583 |
|
| 584 |
static target_ulong h_logical_memop(PowerPCCPU *cpu, sPAPREnvironment *spapr,
|
| 585 |
target_ulong opcode, target_ulong *args) |
| 586 |
{
|
| 587 |
target_ulong dst = args[0]; /* Destination address */ |
| 588 |
target_ulong src = args[1]; /* Source address */ |
| 589 |
target_ulong esize = args[2]; /* Element size (0=1,1=2,2=4,3=8) */ |
| 590 |
target_ulong count = args[3]; /* Element count */ |
| 591 |
target_ulong op = args[4]; /* 0 = copy, 1 = invert */ |
| 592 |
uint64_t tmp; |
| 593 |
unsigned int mask = (1 << esize) - 1; |
| 594 |
int step = 1 << esize; |
| 595 |
|
| 596 |
if (count > 0x80000000) { |
| 597 |
return H_PARAMETER;
|
| 598 |
} |
| 599 |
|
| 600 |
if ((dst & mask) || (src & mask) || (op > 1)) { |
| 601 |
return H_PARAMETER;
|
| 602 |
} |
| 603 |
|
| 604 |
if (dst >= src && dst < (src + (count << esize))) {
|
| 605 |
dst = dst + ((count - 1) << esize);
|
| 606 |
src = src + ((count - 1) << esize);
|
| 607 |
step = -step; |
| 608 |
} |
| 609 |
|
| 610 |
while (count--) {
|
| 611 |
switch (esize) {
|
| 612 |
case 0: |
| 613 |
tmp = ldub_phys(src); |
| 614 |
break;
|
| 615 |
case 1: |
| 616 |
tmp = lduw_phys(src); |
| 617 |
break;
|
| 618 |
case 2: |
| 619 |
tmp = ldl_phys(src); |
| 620 |
break;
|
| 621 |
case 3: |
| 622 |
tmp = ldq_phys(src); |
| 623 |
break;
|
| 624 |
default:
|
| 625 |
return H_PARAMETER;
|
| 626 |
} |
| 627 |
if (op == 1) { |
| 628 |
tmp = ~tmp; |
| 629 |
} |
| 630 |
switch (esize) {
|
| 631 |
case 0: |
| 632 |
stb_phys(dst, tmp); |
| 633 |
break;
|
| 634 |
case 1: |
| 635 |
stw_phys(dst, tmp); |
| 636 |
break;
|
| 637 |
case 2: |
| 638 |
stl_phys(dst, tmp); |
| 639 |
break;
|
| 640 |
case 3: |
| 641 |
stq_phys(dst, tmp); |
| 642 |
break;
|
| 643 |
} |
| 644 |
dst = dst + step; |
| 645 |
src = src + step; |
| 646 |
} |
| 647 |
|
| 648 |
return H_SUCCESS;
|
| 649 |
} |
| 650 |
|
| 651 |
static target_ulong h_logical_icbi(PowerPCCPU *cpu, sPAPREnvironment *spapr,
|
| 652 |
target_ulong opcode, target_ulong *args) |
| 653 |
{
|
| 654 |
/* Nothing to do on emulation, KVM will trap this in the kernel */
|
| 655 |
return H_SUCCESS;
|
| 656 |
} |
| 657 |
|
| 658 |
static target_ulong h_logical_dcbf(PowerPCCPU *cpu, sPAPREnvironment *spapr,
|
| 659 |
target_ulong opcode, target_ulong *args) |
| 660 |
{
|
| 661 |
/* Nothing to do on emulation, KVM will trap this in the kernel */
|
| 662 |
return H_SUCCESS;
|
| 663 |
} |
| 664 |
|
| 665 |
static spapr_hcall_fn papr_hypercall_table[(MAX_HCALL_OPCODE / 4) + 1]; |
| 666 |
static spapr_hcall_fn kvmppc_hypercall_table[KVMPPC_HCALL_MAX - KVMPPC_HCALL_BASE + 1]; |
| 667 |
|
| 668 |
void spapr_register_hypercall(target_ulong opcode, spapr_hcall_fn fn)
|
| 669 |
{
|
| 670 |
spapr_hcall_fn *slot; |
| 671 |
|
| 672 |
if (opcode <= MAX_HCALL_OPCODE) {
|
| 673 |
assert((opcode & 0x3) == 0); |
| 674 |
|
| 675 |
slot = &papr_hypercall_table[opcode / 4];
|
| 676 |
} else {
|
| 677 |
assert((opcode >= KVMPPC_HCALL_BASE) && (opcode <= KVMPPC_HCALL_MAX)); |
| 678 |
|
| 679 |
slot = &kvmppc_hypercall_table[opcode - KVMPPC_HCALL_BASE]; |
| 680 |
} |
| 681 |
|
| 682 |
assert(!(*slot)); |
| 683 |
*slot = fn; |
| 684 |
} |
| 685 |
|
| 686 |
target_ulong spapr_hypercall(PowerPCCPU *cpu, target_ulong opcode, |
| 687 |
target_ulong *args) |
| 688 |
{
|
| 689 |
if ((opcode <= MAX_HCALL_OPCODE)
|
| 690 |
&& ((opcode & 0x3) == 0)) { |
| 691 |
spapr_hcall_fn fn = papr_hypercall_table[opcode / 4];
|
| 692 |
|
| 693 |
if (fn) {
|
| 694 |
return fn(cpu, spapr, opcode, args);
|
| 695 |
} |
| 696 |
} else if ((opcode >= KVMPPC_HCALL_BASE) && |
| 697 |
(opcode <= KVMPPC_HCALL_MAX)) {
|
| 698 |
spapr_hcall_fn fn = kvmppc_hypercall_table[opcode - KVMPPC_HCALL_BASE]; |
| 699 |
|
| 700 |
if (fn) {
|
| 701 |
return fn(cpu, spapr, opcode, args);
|
| 702 |
} |
| 703 |
} |
| 704 |
|
| 705 |
hcall_dprintf("Unimplemented hcall 0x" TARGET_FMT_lx "\n", opcode); |
| 706 |
return H_FUNCTION;
|
| 707 |
} |
| 708 |
|
| 709 |
static void hypercall_register_types(void) |
| 710 |
{
|
| 711 |
/* hcall-pft */
|
| 712 |
spapr_register_hypercall(H_ENTER, h_enter); |
| 713 |
spapr_register_hypercall(H_REMOVE, h_remove); |
| 714 |
spapr_register_hypercall(H_PROTECT, h_protect); |
| 715 |
|
| 716 |
/* hcall-bulk */
|
| 717 |
spapr_register_hypercall(H_BULK_REMOVE, h_bulk_remove); |
| 718 |
|
| 719 |
/* hcall-dabr */
|
| 720 |
spapr_register_hypercall(H_SET_DABR, h_set_dabr); |
| 721 |
|
| 722 |
/* hcall-splpar */
|
| 723 |
spapr_register_hypercall(H_REGISTER_VPA, h_register_vpa); |
| 724 |
spapr_register_hypercall(H_CEDE, h_cede); |
| 725 |
|
| 726 |
/* "debugger" hcalls (also used by SLOF). Note: We do -not- differenciate
|
| 727 |
* here between the "CI" and the "CACHE" variants, they will use whatever
|
| 728 |
* mapping attributes qemu is using. When using KVM, the kernel will
|
| 729 |
* enforce the attributes more strongly
|
| 730 |
*/
|
| 731 |
spapr_register_hypercall(H_LOGICAL_CI_LOAD, h_logical_load); |
| 732 |
spapr_register_hypercall(H_LOGICAL_CI_STORE, h_logical_store); |
| 733 |
spapr_register_hypercall(H_LOGICAL_CACHE_LOAD, h_logical_load); |
| 734 |
spapr_register_hypercall(H_LOGICAL_CACHE_STORE, h_logical_store); |
| 735 |
spapr_register_hypercall(H_LOGICAL_ICBI, h_logical_icbi); |
| 736 |
spapr_register_hypercall(H_LOGICAL_DCBF, h_logical_dcbf); |
| 737 |
spapr_register_hypercall(KVMPPC_H_LOGICAL_MEMOP, h_logical_memop); |
| 738 |
|
| 739 |
/* qemu/KVM-PPC specific hcalls */
|
| 740 |
spapr_register_hypercall(KVMPPC_H_RTAS, h_rtas); |
| 741 |
} |
| 742 |
|
| 743 |
type_init(hypercall_register_types) |