root / hw / m48t59.c @ 9c22a623
History | View | Annotate | Download (16.5 kB)
1 | a541f297 | bellard | /*
|
---|---|---|---|
2 | 819385c5 | bellard | * QEMU M48T59 and M48T08 NVRAM emulation for PPC PREP and Sparc platforms
|
3 | 5fafdf24 | ths | *
|
4 | 3ccacc4a | blueswir1 | * Copyright (c) 2003-2005, 2007 Jocelyn Mayer
|
5 | 5fafdf24 | ths | *
|
6 | a541f297 | bellard | * Permission is hereby granted, free of charge, to any person obtaining a copy
|
7 | a541f297 | bellard | * of this software and associated documentation files (the "Software"), to deal
|
8 | a541f297 | bellard | * in the Software without restriction, including without limitation the rights
|
9 | a541f297 | bellard | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
10 | a541f297 | bellard | * copies of the Software, and to permit persons to whom the Software is
|
11 | a541f297 | bellard | * furnished to do so, subject to the following conditions:
|
12 | a541f297 | bellard | *
|
13 | a541f297 | bellard | * The above copyright notice and this permission notice shall be included in
|
14 | a541f297 | bellard | * all copies or substantial portions of the Software.
|
15 | a541f297 | bellard | *
|
16 | a541f297 | bellard | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
17 | a541f297 | bellard | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
18 | a541f297 | bellard | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
19 | a541f297 | bellard | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
20 | a541f297 | bellard | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
21 | a541f297 | bellard | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
22 | a541f297 | bellard | * THE SOFTWARE.
|
23 | a541f297 | bellard | */
|
24 | 87ecb68b | pbrook | #include "hw.h" |
25 | 87ecb68b | pbrook | #include "nvram.h" |
26 | 87ecb68b | pbrook | #include "isa.h" |
27 | 87ecb68b | pbrook | #include "qemu-timer.h" |
28 | 87ecb68b | pbrook | #include "sysemu.h" |
29 | a541f297 | bellard | |
30 | 13ab5daa | bellard | //#define DEBUG_NVRAM
|
31 | a541f297 | bellard | |
32 | 13ab5daa | bellard | #if defined(DEBUG_NVRAM)
|
33 | a541f297 | bellard | #define NVRAM_PRINTF(fmt, args...) do { printf(fmt , ##args); } while (0) |
34 | a541f297 | bellard | #else
|
35 | a541f297 | bellard | #define NVRAM_PRINTF(fmt, args...) do { } while (0) |
36 | a541f297 | bellard | #endif
|
37 | a541f297 | bellard | |
38 | 819385c5 | bellard | /*
|
39 | 4aed2c33 | blueswir1 | * The M48T02, M48T08 and M48T59 chips are very similar. The newer '59 has
|
40 | 819385c5 | bellard | * alarm and a watchdog timer and related control registers. In the
|
41 | 819385c5 | bellard | * PPC platform there is also a nvram lock function.
|
42 | 819385c5 | bellard | */
|
43 | c5df018e | bellard | struct m48t59_t {
|
44 | 819385c5 | bellard | /* Model parameters */
|
45 | 4aed2c33 | blueswir1 | int type; // 2 = m48t02, 8 = m48t08, 59 = m48t59 |
46 | a541f297 | bellard | /* Hardware parameters */
|
47 | d537cf6c | pbrook | qemu_irq IRQ; |
48 | e1bb04f7 | bellard | int mem_index;
|
49 | a541f297 | bellard | uint32_t io_base; |
50 | a541f297 | bellard | uint16_t size; |
51 | a541f297 | bellard | /* RTC management */
|
52 | a541f297 | bellard | time_t time_offset; |
53 | a541f297 | bellard | time_t stop_time; |
54 | a541f297 | bellard | /* Alarm & watchdog */
|
55 | f6503059 | balrog | struct tm alarm;
|
56 | a541f297 | bellard | struct QEMUTimer *alrm_timer;
|
57 | a541f297 | bellard | struct QEMUTimer *wd_timer;
|
58 | a541f297 | bellard | /* NVRAM storage */
|
59 | 13ab5daa | bellard | uint8_t lock; |
60 | a541f297 | bellard | uint16_t addr; |
61 | a541f297 | bellard | uint8_t *buffer; |
62 | c5df018e | bellard | }; |
63 | a541f297 | bellard | |
64 | a541f297 | bellard | /* Fake timer functions */
|
65 | a541f297 | bellard | /* Generic helpers for BCD */
|
66 | a541f297 | bellard | static inline uint8_t toBCD (uint8_t value) |
67 | a541f297 | bellard | { |
68 | a541f297 | bellard | return (((value / 10) % 10) << 4) | (value % 10); |
69 | a541f297 | bellard | } |
70 | a541f297 | bellard | |
71 | a541f297 | bellard | static inline uint8_t fromBCD (uint8_t BCD) |
72 | a541f297 | bellard | { |
73 | a541f297 | bellard | return ((BCD >> 4) * 10) + (BCD & 0x0F); |
74 | a541f297 | bellard | } |
75 | a541f297 | bellard | |
76 | a541f297 | bellard | /* Alarm management */
|
77 | a541f297 | bellard | static void alarm_cb (void *opaque) |
78 | a541f297 | bellard | { |
79 | f6503059 | balrog | struct tm tm;
|
80 | a541f297 | bellard | uint64_t next_time; |
81 | a541f297 | bellard | m48t59_t *NVRAM = opaque; |
82 | a541f297 | bellard | |
83 | d537cf6c | pbrook | qemu_set_irq(NVRAM->IRQ, 1);
|
84 | 5fafdf24 | ths | if ((NVRAM->buffer[0x1FF5] & 0x80) == 0 && |
85 | a541f297 | bellard | (NVRAM->buffer[0x1FF4] & 0x80) == 0 && |
86 | a541f297 | bellard | (NVRAM->buffer[0x1FF3] & 0x80) == 0 && |
87 | a541f297 | bellard | (NVRAM->buffer[0x1FF2] & 0x80) == 0) { |
88 | f6503059 | balrog | /* Repeat once a month */
|
89 | f6503059 | balrog | qemu_get_timedate(&tm, NVRAM->time_offset); |
90 | f6503059 | balrog | tm.tm_mon++; |
91 | f6503059 | balrog | if (tm.tm_mon == 13) { |
92 | f6503059 | balrog | tm.tm_mon = 1;
|
93 | f6503059 | balrog | tm.tm_year++; |
94 | f6503059 | balrog | } |
95 | f6503059 | balrog | next_time = qemu_timedate_diff(&tm) - NVRAM->time_offset; |
96 | a541f297 | bellard | } else if ((NVRAM->buffer[0x1FF5] & 0x80) != 0 && |
97 | a541f297 | bellard | (NVRAM->buffer[0x1FF4] & 0x80) == 0 && |
98 | a541f297 | bellard | (NVRAM->buffer[0x1FF3] & 0x80) == 0 && |
99 | a541f297 | bellard | (NVRAM->buffer[0x1FF2] & 0x80) == 0) { |
100 | f6503059 | balrog | /* Repeat once a day */
|
101 | f6503059 | balrog | next_time = 24 * 60 * 60; |
102 | a541f297 | bellard | } else if ((NVRAM->buffer[0x1FF5] & 0x80) != 0 && |
103 | a541f297 | bellard | (NVRAM->buffer[0x1FF4] & 0x80) != 0 && |
104 | a541f297 | bellard | (NVRAM->buffer[0x1FF3] & 0x80) == 0 && |
105 | a541f297 | bellard | (NVRAM->buffer[0x1FF2] & 0x80) == 0) { |
106 | f6503059 | balrog | /* Repeat once an hour */
|
107 | f6503059 | balrog | next_time = 60 * 60; |
108 | a541f297 | bellard | } else if ((NVRAM->buffer[0x1FF5] & 0x80) != 0 && |
109 | a541f297 | bellard | (NVRAM->buffer[0x1FF4] & 0x80) != 0 && |
110 | a541f297 | bellard | (NVRAM->buffer[0x1FF3] & 0x80) != 0 && |
111 | a541f297 | bellard | (NVRAM->buffer[0x1FF2] & 0x80) == 0) { |
112 | f6503059 | balrog | /* Repeat once a minute */
|
113 | f6503059 | balrog | next_time = 60;
|
114 | a541f297 | bellard | } else {
|
115 | f6503059 | balrog | /* Repeat once a second */
|
116 | f6503059 | balrog | next_time = 1;
|
117 | a541f297 | bellard | } |
118 | f6503059 | balrog | qemu_mod_timer(NVRAM->alrm_timer, qemu_get_clock(vm_clock) + |
119 | f6503059 | balrog | next_time * 1000);
|
120 | d537cf6c | pbrook | qemu_set_irq(NVRAM->IRQ, 0);
|
121 | a541f297 | bellard | } |
122 | a541f297 | bellard | |
123 | f6503059 | balrog | static void set_alarm (m48t59_t *NVRAM) |
124 | f6503059 | balrog | { |
125 | f6503059 | balrog | int diff;
|
126 | f6503059 | balrog | if (NVRAM->alrm_timer != NULL) { |
127 | f6503059 | balrog | qemu_del_timer(NVRAM->alrm_timer); |
128 | f6503059 | balrog | diff = qemu_timedate_diff(&NVRAM->alarm) - NVRAM->time_offset; |
129 | f6503059 | balrog | if (diff > 0) |
130 | f6503059 | balrog | qemu_mod_timer(NVRAM->alrm_timer, diff * 1000);
|
131 | f6503059 | balrog | } |
132 | f6503059 | balrog | } |
133 | a541f297 | bellard | |
134 | f6503059 | balrog | /* RTC management helpers */
|
135 | f6503059 | balrog | static inline void get_time (m48t59_t *NVRAM, struct tm *tm) |
136 | a541f297 | bellard | { |
137 | f6503059 | balrog | qemu_get_timedate(tm, NVRAM->time_offset); |
138 | a541f297 | bellard | } |
139 | a541f297 | bellard | |
140 | f6503059 | balrog | static void set_time (m48t59_t *NVRAM, struct tm *tm) |
141 | a541f297 | bellard | { |
142 | f6503059 | balrog | NVRAM->time_offset = qemu_timedate_diff(tm); |
143 | f6503059 | balrog | set_alarm(NVRAM); |
144 | a541f297 | bellard | } |
145 | a541f297 | bellard | |
146 | a541f297 | bellard | /* Watchdog management */
|
147 | a541f297 | bellard | static void watchdog_cb (void *opaque) |
148 | a541f297 | bellard | { |
149 | a541f297 | bellard | m48t59_t *NVRAM = opaque; |
150 | a541f297 | bellard | |
151 | a541f297 | bellard | NVRAM->buffer[0x1FF0] |= 0x80; |
152 | a541f297 | bellard | if (NVRAM->buffer[0x1FF7] & 0x80) { |
153 | a541f297 | bellard | NVRAM->buffer[0x1FF7] = 0x00; |
154 | a541f297 | bellard | NVRAM->buffer[0x1FFC] &= ~0x40; |
155 | 13ab5daa | bellard | /* May it be a hw CPU Reset instead ? */
|
156 | d7d02e3c | bellard | qemu_system_reset_request(); |
157 | a541f297 | bellard | } else {
|
158 | d537cf6c | pbrook | qemu_set_irq(NVRAM->IRQ, 1);
|
159 | d537cf6c | pbrook | qemu_set_irq(NVRAM->IRQ, 0);
|
160 | a541f297 | bellard | } |
161 | a541f297 | bellard | } |
162 | a541f297 | bellard | |
163 | a541f297 | bellard | static void set_up_watchdog (m48t59_t *NVRAM, uint8_t value) |
164 | a541f297 | bellard | { |
165 | a541f297 | bellard | uint64_t interval; /* in 1/16 seconds */
|
166 | a541f297 | bellard | |
167 | 868d585a | j_mayer | NVRAM->buffer[0x1FF0] &= ~0x80; |
168 | a541f297 | bellard | if (NVRAM->wd_timer != NULL) { |
169 | a541f297 | bellard | qemu_del_timer(NVRAM->wd_timer); |
170 | 868d585a | j_mayer | if (value != 0) { |
171 | 868d585a | j_mayer | interval = (1 << (2 * (value & 0x03))) * ((value >> 2) & 0x1F); |
172 | 868d585a | j_mayer | qemu_mod_timer(NVRAM->wd_timer, ((uint64_t)time(NULL) * 1000) + |
173 | 868d585a | j_mayer | ((interval * 1000) >> 4)); |
174 | 868d585a | j_mayer | } |
175 | a541f297 | bellard | } |
176 | a541f297 | bellard | } |
177 | a541f297 | bellard | |
178 | a541f297 | bellard | /* Direct access to NVRAM */
|
179 | 897b4c6c | j_mayer | void m48t59_write (void *opaque, uint32_t addr, uint32_t val) |
180 | a541f297 | bellard | { |
181 | 897b4c6c | j_mayer | m48t59_t *NVRAM = opaque; |
182 | a541f297 | bellard | struct tm tm;
|
183 | a541f297 | bellard | int tmp;
|
184 | a541f297 | bellard | |
185 | 819385c5 | bellard | if (addr > 0x1FF8 && addr < 0x2000) |
186 | 819385c5 | bellard | NVRAM_PRINTF("%s: 0x%08x => 0x%08x\n", __func__, addr, val);
|
187 | 4aed2c33 | blueswir1 | |
188 | 4aed2c33 | blueswir1 | /* check for NVRAM access */
|
189 | 4aed2c33 | blueswir1 | if ((NVRAM->type == 2 && addr < 0x7f8) || |
190 | 4aed2c33 | blueswir1 | (NVRAM->type == 8 && addr < 0x1ff8) || |
191 | 4aed2c33 | blueswir1 | (NVRAM->type == 59 && addr < 0x1ff0)) |
192 | 819385c5 | bellard | goto do_write;
|
193 | 4aed2c33 | blueswir1 | |
194 | 4aed2c33 | blueswir1 | /* TOD access */
|
195 | 819385c5 | bellard | switch (addr) {
|
196 | a541f297 | bellard | case 0x1FF0: |
197 | a541f297 | bellard | /* flags register : read-only */
|
198 | a541f297 | bellard | break;
|
199 | a541f297 | bellard | case 0x1FF1: |
200 | a541f297 | bellard | /* unused */
|
201 | a541f297 | bellard | break;
|
202 | a541f297 | bellard | case 0x1FF2: |
203 | a541f297 | bellard | /* alarm seconds */
|
204 | 819385c5 | bellard | tmp = fromBCD(val & 0x7F);
|
205 | 819385c5 | bellard | if (tmp >= 0 && tmp <= 59) { |
206 | f6503059 | balrog | NVRAM->alarm.tm_sec = tmp; |
207 | 819385c5 | bellard | NVRAM->buffer[0x1FF2] = val;
|
208 | f6503059 | balrog | set_alarm(NVRAM); |
209 | 819385c5 | bellard | } |
210 | a541f297 | bellard | break;
|
211 | a541f297 | bellard | case 0x1FF3: |
212 | a541f297 | bellard | /* alarm minutes */
|
213 | 819385c5 | bellard | tmp = fromBCD(val & 0x7F);
|
214 | 819385c5 | bellard | if (tmp >= 0 && tmp <= 59) { |
215 | f6503059 | balrog | NVRAM->alarm.tm_min = tmp; |
216 | 819385c5 | bellard | NVRAM->buffer[0x1FF3] = val;
|
217 | f6503059 | balrog | set_alarm(NVRAM); |
218 | 819385c5 | bellard | } |
219 | a541f297 | bellard | break;
|
220 | a541f297 | bellard | case 0x1FF4: |
221 | a541f297 | bellard | /* alarm hours */
|
222 | 819385c5 | bellard | tmp = fromBCD(val & 0x3F);
|
223 | 819385c5 | bellard | if (tmp >= 0 && tmp <= 23) { |
224 | f6503059 | balrog | NVRAM->alarm.tm_hour = tmp; |
225 | 819385c5 | bellard | NVRAM->buffer[0x1FF4] = val;
|
226 | f6503059 | balrog | set_alarm(NVRAM); |
227 | 819385c5 | bellard | } |
228 | a541f297 | bellard | break;
|
229 | a541f297 | bellard | case 0x1FF5: |
230 | a541f297 | bellard | /* alarm date */
|
231 | 819385c5 | bellard | tmp = fromBCD(val & 0x1F);
|
232 | 819385c5 | bellard | if (tmp != 0) { |
233 | f6503059 | balrog | NVRAM->alarm.tm_mday = tmp; |
234 | 819385c5 | bellard | NVRAM->buffer[0x1FF5] = val;
|
235 | f6503059 | balrog | set_alarm(NVRAM); |
236 | 819385c5 | bellard | } |
237 | a541f297 | bellard | break;
|
238 | a541f297 | bellard | case 0x1FF6: |
239 | a541f297 | bellard | /* interrupts */
|
240 | 819385c5 | bellard | NVRAM->buffer[0x1FF6] = val;
|
241 | a541f297 | bellard | break;
|
242 | a541f297 | bellard | case 0x1FF7: |
243 | a541f297 | bellard | /* watchdog */
|
244 | 819385c5 | bellard | NVRAM->buffer[0x1FF7] = val;
|
245 | 819385c5 | bellard | set_up_watchdog(NVRAM, val); |
246 | a541f297 | bellard | break;
|
247 | a541f297 | bellard | case 0x1FF8: |
248 | 4aed2c33 | blueswir1 | case 0x07F8: |
249 | a541f297 | bellard | /* control */
|
250 | 4aed2c33 | blueswir1 | NVRAM->buffer[addr] = (val & ~0xA0) | 0x90; |
251 | a541f297 | bellard | break;
|
252 | a541f297 | bellard | case 0x1FF9: |
253 | 4aed2c33 | blueswir1 | case 0x07F9: |
254 | a541f297 | bellard | /* seconds (BCD) */
|
255 | a541f297 | bellard | tmp = fromBCD(val & 0x7F);
|
256 | a541f297 | bellard | if (tmp >= 0 && tmp <= 59) { |
257 | a541f297 | bellard | get_time(NVRAM, &tm); |
258 | a541f297 | bellard | tm.tm_sec = tmp; |
259 | a541f297 | bellard | set_time(NVRAM, &tm); |
260 | a541f297 | bellard | } |
261 | f6503059 | balrog | if ((val & 0x80) ^ (NVRAM->buffer[addr] & 0x80)) { |
262 | a541f297 | bellard | if (val & 0x80) { |
263 | a541f297 | bellard | NVRAM->stop_time = time(NULL);
|
264 | a541f297 | bellard | } else {
|
265 | a541f297 | bellard | NVRAM->time_offset += NVRAM->stop_time - time(NULL);
|
266 | a541f297 | bellard | NVRAM->stop_time = 0;
|
267 | a541f297 | bellard | } |
268 | a541f297 | bellard | } |
269 | f6503059 | balrog | NVRAM->buffer[addr] = val & 0x80;
|
270 | a541f297 | bellard | break;
|
271 | a541f297 | bellard | case 0x1FFA: |
272 | 4aed2c33 | blueswir1 | case 0x07FA: |
273 | a541f297 | bellard | /* minutes (BCD) */
|
274 | a541f297 | bellard | tmp = fromBCD(val & 0x7F);
|
275 | a541f297 | bellard | if (tmp >= 0 && tmp <= 59) { |
276 | a541f297 | bellard | get_time(NVRAM, &tm); |
277 | a541f297 | bellard | tm.tm_min = tmp; |
278 | a541f297 | bellard | set_time(NVRAM, &tm); |
279 | a541f297 | bellard | } |
280 | a541f297 | bellard | break;
|
281 | a541f297 | bellard | case 0x1FFB: |
282 | 4aed2c33 | blueswir1 | case 0x07FB: |
283 | a541f297 | bellard | /* hours (BCD) */
|
284 | a541f297 | bellard | tmp = fromBCD(val & 0x3F);
|
285 | a541f297 | bellard | if (tmp >= 0 && tmp <= 23) { |
286 | a541f297 | bellard | get_time(NVRAM, &tm); |
287 | a541f297 | bellard | tm.tm_hour = tmp; |
288 | a541f297 | bellard | set_time(NVRAM, &tm); |
289 | a541f297 | bellard | } |
290 | a541f297 | bellard | break;
|
291 | a541f297 | bellard | case 0x1FFC: |
292 | 4aed2c33 | blueswir1 | case 0x07FC: |
293 | a541f297 | bellard | /* day of the week / century */
|
294 | a541f297 | bellard | tmp = fromBCD(val & 0x07);
|
295 | a541f297 | bellard | get_time(NVRAM, &tm); |
296 | a541f297 | bellard | tm.tm_wday = tmp; |
297 | a541f297 | bellard | set_time(NVRAM, &tm); |
298 | 4aed2c33 | blueswir1 | NVRAM->buffer[addr] = val & 0x40;
|
299 | a541f297 | bellard | break;
|
300 | a541f297 | bellard | case 0x1FFD: |
301 | 4aed2c33 | blueswir1 | case 0x07FD: |
302 | a541f297 | bellard | /* date */
|
303 | a541f297 | bellard | tmp = fromBCD(val & 0x1F);
|
304 | a541f297 | bellard | if (tmp != 0) { |
305 | a541f297 | bellard | get_time(NVRAM, &tm); |
306 | a541f297 | bellard | tm.tm_mday = tmp; |
307 | a541f297 | bellard | set_time(NVRAM, &tm); |
308 | a541f297 | bellard | } |
309 | a541f297 | bellard | break;
|
310 | a541f297 | bellard | case 0x1FFE: |
311 | 4aed2c33 | blueswir1 | case 0x07FE: |
312 | a541f297 | bellard | /* month */
|
313 | a541f297 | bellard | tmp = fromBCD(val & 0x1F);
|
314 | a541f297 | bellard | if (tmp >= 1 && tmp <= 12) { |
315 | a541f297 | bellard | get_time(NVRAM, &tm); |
316 | a541f297 | bellard | tm.tm_mon = tmp - 1;
|
317 | a541f297 | bellard | set_time(NVRAM, &tm); |
318 | a541f297 | bellard | } |
319 | a541f297 | bellard | break;
|
320 | a541f297 | bellard | case 0x1FFF: |
321 | 4aed2c33 | blueswir1 | case 0x07FF: |
322 | a541f297 | bellard | /* year */
|
323 | a541f297 | bellard | tmp = fromBCD(val); |
324 | a541f297 | bellard | if (tmp >= 0 && tmp <= 99) { |
325 | a541f297 | bellard | get_time(NVRAM, &tm); |
326 | 180b700d | bellard | if (NVRAM->type == 8) |
327 | 180b700d | bellard | tm.tm_year = fromBCD(val) + 68; // Base year is 1968 |
328 | 180b700d | bellard | else
|
329 | 180b700d | bellard | tm.tm_year = fromBCD(val); |
330 | a541f297 | bellard | set_time(NVRAM, &tm); |
331 | a541f297 | bellard | } |
332 | a541f297 | bellard | break;
|
333 | a541f297 | bellard | default:
|
334 | 13ab5daa | bellard | /* Check lock registers state */
|
335 | 819385c5 | bellard | if (addr >= 0x20 && addr <= 0x2F && (NVRAM->lock & 1)) |
336 | 13ab5daa | bellard | break;
|
337 | 819385c5 | bellard | if (addr >= 0x30 && addr <= 0x3F && (NVRAM->lock & 2)) |
338 | 13ab5daa | bellard | break;
|
339 | 819385c5 | bellard | do_write:
|
340 | 819385c5 | bellard | if (addr < NVRAM->size) {
|
341 | 819385c5 | bellard | NVRAM->buffer[addr] = val & 0xFF;
|
342 | a541f297 | bellard | } |
343 | a541f297 | bellard | break;
|
344 | a541f297 | bellard | } |
345 | a541f297 | bellard | } |
346 | a541f297 | bellard | |
347 | 897b4c6c | j_mayer | uint32_t m48t59_read (void *opaque, uint32_t addr)
|
348 | a541f297 | bellard | { |
349 | 897b4c6c | j_mayer | m48t59_t *NVRAM = opaque; |
350 | a541f297 | bellard | struct tm tm;
|
351 | a541f297 | bellard | uint32_t retval = 0xFF;
|
352 | a541f297 | bellard | |
353 | 4aed2c33 | blueswir1 | /* check for NVRAM access */
|
354 | 4aed2c33 | blueswir1 | if ((NVRAM->type == 2 && addr < 0x078f) || |
355 | 4aed2c33 | blueswir1 | (NVRAM->type == 8 && addr < 0x1ff8) || |
356 | 4aed2c33 | blueswir1 | (NVRAM->type == 59 && addr < 0x1ff0)) |
357 | 819385c5 | bellard | goto do_read;
|
358 | 4aed2c33 | blueswir1 | |
359 | 4aed2c33 | blueswir1 | /* TOD access */
|
360 | 819385c5 | bellard | switch (addr) {
|
361 | a541f297 | bellard | case 0x1FF0: |
362 | a541f297 | bellard | /* flags register */
|
363 | a541f297 | bellard | goto do_read;
|
364 | a541f297 | bellard | case 0x1FF1: |
365 | a541f297 | bellard | /* unused */
|
366 | a541f297 | bellard | retval = 0;
|
367 | a541f297 | bellard | break;
|
368 | a541f297 | bellard | case 0x1FF2: |
369 | a541f297 | bellard | /* alarm seconds */
|
370 | a541f297 | bellard | goto do_read;
|
371 | a541f297 | bellard | case 0x1FF3: |
372 | a541f297 | bellard | /* alarm minutes */
|
373 | a541f297 | bellard | goto do_read;
|
374 | a541f297 | bellard | case 0x1FF4: |
375 | a541f297 | bellard | /* alarm hours */
|
376 | a541f297 | bellard | goto do_read;
|
377 | a541f297 | bellard | case 0x1FF5: |
378 | a541f297 | bellard | /* alarm date */
|
379 | a541f297 | bellard | goto do_read;
|
380 | a541f297 | bellard | case 0x1FF6: |
381 | a541f297 | bellard | /* interrupts */
|
382 | a541f297 | bellard | goto do_read;
|
383 | a541f297 | bellard | case 0x1FF7: |
384 | a541f297 | bellard | /* A read resets the watchdog */
|
385 | a541f297 | bellard | set_up_watchdog(NVRAM, NVRAM->buffer[0x1FF7]);
|
386 | a541f297 | bellard | goto do_read;
|
387 | a541f297 | bellard | case 0x1FF8: |
388 | 4aed2c33 | blueswir1 | case 0x07F8: |
389 | a541f297 | bellard | /* control */
|
390 | a541f297 | bellard | goto do_read;
|
391 | a541f297 | bellard | case 0x1FF9: |
392 | 4aed2c33 | blueswir1 | case 0x07F9: |
393 | a541f297 | bellard | /* seconds (BCD) */
|
394 | a541f297 | bellard | get_time(NVRAM, &tm); |
395 | 4aed2c33 | blueswir1 | retval = (NVRAM->buffer[addr] & 0x80) | toBCD(tm.tm_sec);
|
396 | a541f297 | bellard | break;
|
397 | a541f297 | bellard | case 0x1FFA: |
398 | 4aed2c33 | blueswir1 | case 0x07FA: |
399 | a541f297 | bellard | /* minutes (BCD) */
|
400 | a541f297 | bellard | get_time(NVRAM, &tm); |
401 | a541f297 | bellard | retval = toBCD(tm.tm_min); |
402 | a541f297 | bellard | break;
|
403 | a541f297 | bellard | case 0x1FFB: |
404 | 4aed2c33 | blueswir1 | case 0x07FB: |
405 | a541f297 | bellard | /* hours (BCD) */
|
406 | a541f297 | bellard | get_time(NVRAM, &tm); |
407 | a541f297 | bellard | retval = toBCD(tm.tm_hour); |
408 | a541f297 | bellard | break;
|
409 | a541f297 | bellard | case 0x1FFC: |
410 | 4aed2c33 | blueswir1 | case 0x07FC: |
411 | a541f297 | bellard | /* day of the week / century */
|
412 | a541f297 | bellard | get_time(NVRAM, &tm); |
413 | 4aed2c33 | blueswir1 | retval = NVRAM->buffer[addr] | tm.tm_wday; |
414 | a541f297 | bellard | break;
|
415 | a541f297 | bellard | case 0x1FFD: |
416 | 4aed2c33 | blueswir1 | case 0x07FD: |
417 | a541f297 | bellard | /* date */
|
418 | a541f297 | bellard | get_time(NVRAM, &tm); |
419 | a541f297 | bellard | retval = toBCD(tm.tm_mday); |
420 | a541f297 | bellard | break;
|
421 | a541f297 | bellard | case 0x1FFE: |
422 | 4aed2c33 | blueswir1 | case 0x07FE: |
423 | a541f297 | bellard | /* month */
|
424 | a541f297 | bellard | get_time(NVRAM, &tm); |
425 | a541f297 | bellard | retval = toBCD(tm.tm_mon + 1);
|
426 | a541f297 | bellard | break;
|
427 | a541f297 | bellard | case 0x1FFF: |
428 | 4aed2c33 | blueswir1 | case 0x07FF: |
429 | a541f297 | bellard | /* year */
|
430 | a541f297 | bellard | get_time(NVRAM, &tm); |
431 | 5fafdf24 | ths | if (NVRAM->type == 8) |
432 | 180b700d | bellard | retval = toBCD(tm.tm_year - 68); // Base year is 1968 |
433 | 180b700d | bellard | else
|
434 | 180b700d | bellard | retval = toBCD(tm.tm_year); |
435 | a541f297 | bellard | break;
|
436 | a541f297 | bellard | default:
|
437 | 13ab5daa | bellard | /* Check lock registers state */
|
438 | 819385c5 | bellard | if (addr >= 0x20 && addr <= 0x2F && (NVRAM->lock & 1)) |
439 | 13ab5daa | bellard | break;
|
440 | 819385c5 | bellard | if (addr >= 0x30 && addr <= 0x3F && (NVRAM->lock & 2)) |
441 | 13ab5daa | bellard | break;
|
442 | 819385c5 | bellard | do_read:
|
443 | 819385c5 | bellard | if (addr < NVRAM->size) {
|
444 | 819385c5 | bellard | retval = NVRAM->buffer[addr]; |
445 | a541f297 | bellard | } |
446 | a541f297 | bellard | break;
|
447 | a541f297 | bellard | } |
448 | 819385c5 | bellard | if (addr > 0x1FF9 && addr < 0x2000) |
449 | 9ed1e667 | blueswir1 | NVRAM_PRINTF("%s: 0x%08x <= 0x%08x\n", __func__, addr, retval);
|
450 | a541f297 | bellard | |
451 | a541f297 | bellard | return retval;
|
452 | a541f297 | bellard | } |
453 | a541f297 | bellard | |
454 | 897b4c6c | j_mayer | void m48t59_set_addr (void *opaque, uint32_t addr) |
455 | a541f297 | bellard | { |
456 | 897b4c6c | j_mayer | m48t59_t *NVRAM = opaque; |
457 | 897b4c6c | j_mayer | |
458 | a541f297 | bellard | NVRAM->addr = addr; |
459 | a541f297 | bellard | } |
460 | a541f297 | bellard | |
461 | 897b4c6c | j_mayer | void m48t59_toggle_lock (void *opaque, int lock) |
462 | 13ab5daa | bellard | { |
463 | 897b4c6c | j_mayer | m48t59_t *NVRAM = opaque; |
464 | 897b4c6c | j_mayer | |
465 | 13ab5daa | bellard | NVRAM->lock ^= 1 << lock;
|
466 | 13ab5daa | bellard | } |
467 | 13ab5daa | bellard | |
468 | a541f297 | bellard | /* IO access to NVRAM */
|
469 | a541f297 | bellard | static void NVRAM_writeb (void *opaque, uint32_t addr, uint32_t val) |
470 | a541f297 | bellard | { |
471 | a541f297 | bellard | m48t59_t *NVRAM = opaque; |
472 | a541f297 | bellard | |
473 | a541f297 | bellard | addr -= NVRAM->io_base; |
474 | 9ed1e667 | blueswir1 | NVRAM_PRINTF("%s: 0x%08x => 0x%08x\n", __func__, addr, val);
|
475 | a541f297 | bellard | switch (addr) {
|
476 | a541f297 | bellard | case 0: |
477 | a541f297 | bellard | NVRAM->addr &= ~0x00FF;
|
478 | a541f297 | bellard | NVRAM->addr |= val; |
479 | a541f297 | bellard | break;
|
480 | a541f297 | bellard | case 1: |
481 | a541f297 | bellard | NVRAM->addr &= ~0xFF00;
|
482 | a541f297 | bellard | NVRAM->addr |= val << 8;
|
483 | a541f297 | bellard | break;
|
484 | a541f297 | bellard | case 3: |
485 | 819385c5 | bellard | m48t59_write(NVRAM, val, NVRAM->addr); |
486 | a541f297 | bellard | NVRAM->addr = 0x0000;
|
487 | a541f297 | bellard | break;
|
488 | a541f297 | bellard | default:
|
489 | a541f297 | bellard | break;
|
490 | a541f297 | bellard | } |
491 | a541f297 | bellard | } |
492 | a541f297 | bellard | |
493 | a541f297 | bellard | static uint32_t NVRAM_readb (void *opaque, uint32_t addr) |
494 | a541f297 | bellard | { |
495 | a541f297 | bellard | m48t59_t *NVRAM = opaque; |
496 | 13ab5daa | bellard | uint32_t retval; |
497 | a541f297 | bellard | |
498 | 13ab5daa | bellard | addr -= NVRAM->io_base; |
499 | 13ab5daa | bellard | switch (addr) {
|
500 | 13ab5daa | bellard | case 3: |
501 | 819385c5 | bellard | retval = m48t59_read(NVRAM, NVRAM->addr); |
502 | 13ab5daa | bellard | break;
|
503 | 13ab5daa | bellard | default:
|
504 | 13ab5daa | bellard | retval = -1;
|
505 | 13ab5daa | bellard | break;
|
506 | 13ab5daa | bellard | } |
507 | 9ed1e667 | blueswir1 | NVRAM_PRINTF("%s: 0x%08x <= 0x%08x\n", __func__, addr, retval);
|
508 | a541f297 | bellard | |
509 | 13ab5daa | bellard | return retval;
|
510 | a541f297 | bellard | } |
511 | a541f297 | bellard | |
512 | e1bb04f7 | bellard | static void nvram_writeb (void *opaque, target_phys_addr_t addr, uint32_t value) |
513 | e1bb04f7 | bellard | { |
514 | e1bb04f7 | bellard | m48t59_t *NVRAM = opaque; |
515 | 3b46e624 | ths | |
516 | 819385c5 | bellard | m48t59_write(NVRAM, addr, value & 0xff);
|
517 | e1bb04f7 | bellard | } |
518 | e1bb04f7 | bellard | |
519 | e1bb04f7 | bellard | static void nvram_writew (void *opaque, target_phys_addr_t addr, uint32_t value) |
520 | e1bb04f7 | bellard | { |
521 | e1bb04f7 | bellard | m48t59_t *NVRAM = opaque; |
522 | 3b46e624 | ths | |
523 | 819385c5 | bellard | m48t59_write(NVRAM, addr, (value >> 8) & 0xff); |
524 | 819385c5 | bellard | m48t59_write(NVRAM, addr + 1, value & 0xff); |
525 | e1bb04f7 | bellard | } |
526 | e1bb04f7 | bellard | |
527 | e1bb04f7 | bellard | static void nvram_writel (void *opaque, target_phys_addr_t addr, uint32_t value) |
528 | e1bb04f7 | bellard | { |
529 | e1bb04f7 | bellard | m48t59_t *NVRAM = opaque; |
530 | 3b46e624 | ths | |
531 | 819385c5 | bellard | m48t59_write(NVRAM, addr, (value >> 24) & 0xff); |
532 | 819385c5 | bellard | m48t59_write(NVRAM, addr + 1, (value >> 16) & 0xff); |
533 | 819385c5 | bellard | m48t59_write(NVRAM, addr + 2, (value >> 8) & 0xff); |
534 | 819385c5 | bellard | m48t59_write(NVRAM, addr + 3, value & 0xff); |
535 | e1bb04f7 | bellard | } |
536 | e1bb04f7 | bellard | |
537 | e1bb04f7 | bellard | static uint32_t nvram_readb (void *opaque, target_phys_addr_t addr) |
538 | e1bb04f7 | bellard | { |
539 | e1bb04f7 | bellard | m48t59_t *NVRAM = opaque; |
540 | 819385c5 | bellard | uint32_t retval; |
541 | 3b46e624 | ths | |
542 | 819385c5 | bellard | retval = m48t59_read(NVRAM, addr); |
543 | e1bb04f7 | bellard | return retval;
|
544 | e1bb04f7 | bellard | } |
545 | e1bb04f7 | bellard | |
546 | e1bb04f7 | bellard | static uint32_t nvram_readw (void *opaque, target_phys_addr_t addr) |
547 | e1bb04f7 | bellard | { |
548 | e1bb04f7 | bellard | m48t59_t *NVRAM = opaque; |
549 | 819385c5 | bellard | uint32_t retval; |
550 | 3b46e624 | ths | |
551 | 819385c5 | bellard | retval = m48t59_read(NVRAM, addr) << 8;
|
552 | 819385c5 | bellard | retval |= m48t59_read(NVRAM, addr + 1);
|
553 | e1bb04f7 | bellard | return retval;
|
554 | e1bb04f7 | bellard | } |
555 | e1bb04f7 | bellard | |
556 | e1bb04f7 | bellard | static uint32_t nvram_readl (void *opaque, target_phys_addr_t addr) |
557 | e1bb04f7 | bellard | { |
558 | e1bb04f7 | bellard | m48t59_t *NVRAM = opaque; |
559 | 819385c5 | bellard | uint32_t retval; |
560 | e1bb04f7 | bellard | |
561 | 819385c5 | bellard | retval = m48t59_read(NVRAM, addr) << 24;
|
562 | 819385c5 | bellard | retval |= m48t59_read(NVRAM, addr + 1) << 16; |
563 | 819385c5 | bellard | retval |= m48t59_read(NVRAM, addr + 2) << 8; |
564 | 819385c5 | bellard | retval |= m48t59_read(NVRAM, addr + 3);
|
565 | e1bb04f7 | bellard | return retval;
|
566 | e1bb04f7 | bellard | } |
567 | e1bb04f7 | bellard | |
568 | e1bb04f7 | bellard | static CPUWriteMemoryFunc *nvram_write[] = {
|
569 | e1bb04f7 | bellard | &nvram_writeb, |
570 | e1bb04f7 | bellard | &nvram_writew, |
571 | e1bb04f7 | bellard | &nvram_writel, |
572 | e1bb04f7 | bellard | }; |
573 | e1bb04f7 | bellard | |
574 | e1bb04f7 | bellard | static CPUReadMemoryFunc *nvram_read[] = {
|
575 | e1bb04f7 | bellard | &nvram_readb, |
576 | e1bb04f7 | bellard | &nvram_readw, |
577 | e1bb04f7 | bellard | &nvram_readl, |
578 | e1bb04f7 | bellard | }; |
579 | 819385c5 | bellard | |
580 | 3ccacc4a | blueswir1 | static void m48t59_save(QEMUFile *f, void *opaque) |
581 | 3ccacc4a | blueswir1 | { |
582 | 3ccacc4a | blueswir1 | m48t59_t *s = opaque; |
583 | 3ccacc4a | blueswir1 | |
584 | 3ccacc4a | blueswir1 | qemu_put_8s(f, &s->lock); |
585 | 3ccacc4a | blueswir1 | qemu_put_be16s(f, &s->addr); |
586 | 3ccacc4a | blueswir1 | qemu_put_buffer(f, s->buffer, s->size); |
587 | 3ccacc4a | blueswir1 | } |
588 | 3ccacc4a | blueswir1 | |
589 | 3ccacc4a | blueswir1 | static int m48t59_load(QEMUFile *f, void *opaque, int version_id) |
590 | 3ccacc4a | blueswir1 | { |
591 | 3ccacc4a | blueswir1 | m48t59_t *s = opaque; |
592 | 3ccacc4a | blueswir1 | |
593 | 3ccacc4a | blueswir1 | if (version_id != 1) |
594 | 3ccacc4a | blueswir1 | return -EINVAL;
|
595 | 3ccacc4a | blueswir1 | |
596 | 3ccacc4a | blueswir1 | qemu_get_8s(f, &s->lock); |
597 | 3ccacc4a | blueswir1 | qemu_get_be16s(f, &s->addr); |
598 | 3ccacc4a | blueswir1 | qemu_get_buffer(f, s->buffer, s->size); |
599 | 3ccacc4a | blueswir1 | |
600 | 3ccacc4a | blueswir1 | return 0; |
601 | 3ccacc4a | blueswir1 | } |
602 | 3ccacc4a | blueswir1 | |
603 | 3ccacc4a | blueswir1 | static void m48t59_reset(void *opaque) |
604 | 3ccacc4a | blueswir1 | { |
605 | 3ccacc4a | blueswir1 | m48t59_t *NVRAM = opaque; |
606 | 3ccacc4a | blueswir1 | |
607 | 6e6b7363 | blueswir1 | NVRAM->addr = 0;
|
608 | 6e6b7363 | blueswir1 | NVRAM->lock = 0;
|
609 | 3ccacc4a | blueswir1 | if (NVRAM->alrm_timer != NULL) |
610 | 3ccacc4a | blueswir1 | qemu_del_timer(NVRAM->alrm_timer); |
611 | 3ccacc4a | blueswir1 | |
612 | 3ccacc4a | blueswir1 | if (NVRAM->wd_timer != NULL) |
613 | 3ccacc4a | blueswir1 | qemu_del_timer(NVRAM->wd_timer); |
614 | 3ccacc4a | blueswir1 | } |
615 | 3ccacc4a | blueswir1 | |
616 | a541f297 | bellard | /* Initialisation routine */
|
617 | 5dcb6b91 | blueswir1 | m48t59_t *m48t59_init (qemu_irq IRQ, target_phys_addr_t mem_base, |
618 | 819385c5 | bellard | uint32_t io_base, uint16_t size, |
619 | 819385c5 | bellard | int type)
|
620 | a541f297 | bellard | { |
621 | c5df018e | bellard | m48t59_t *s; |
622 | 5dcb6b91 | blueswir1 | target_phys_addr_t save_base; |
623 | a541f297 | bellard | |
624 | c5df018e | bellard | s = qemu_mallocz(sizeof(m48t59_t));
|
625 | c5df018e | bellard | s->buffer = qemu_mallocz(size); |
626 | c5df018e | bellard | s->IRQ = IRQ; |
627 | c5df018e | bellard | s->size = size; |
628 | c5df018e | bellard | s->io_base = io_base; |
629 | 819385c5 | bellard | s->type = type; |
630 | 819385c5 | bellard | if (io_base != 0) { |
631 | 819385c5 | bellard | register_ioport_read(io_base, 0x04, 1, NVRAM_readb, s); |
632 | 819385c5 | bellard | register_ioport_write(io_base, 0x04, 1, NVRAM_writeb, s); |
633 | 819385c5 | bellard | } |
634 | e1bb04f7 | bellard | if (mem_base != 0) { |
635 | e1bb04f7 | bellard | s->mem_index = cpu_register_io_memory(0, nvram_read, nvram_write, s);
|
636 | 4aed2c33 | blueswir1 | cpu_register_physical_memory(mem_base, size, s->mem_index); |
637 | e1bb04f7 | bellard | } |
638 | 819385c5 | bellard | if (type == 59) { |
639 | 819385c5 | bellard | s->alrm_timer = qemu_new_timer(vm_clock, &alarm_cb, s); |
640 | 819385c5 | bellard | s->wd_timer = qemu_new_timer(vm_clock, &watchdog_cb, s); |
641 | 819385c5 | bellard | } |
642 | f6503059 | balrog | qemu_get_timedate(&s->alarm, 0);
|
643 | 13ab5daa | bellard | |
644 | 3ccacc4a | blueswir1 | qemu_register_reset(m48t59_reset, s); |
645 | 3ccacc4a | blueswir1 | save_base = mem_base ? mem_base : io_base; |
646 | 3ccacc4a | blueswir1 | register_savevm("m48t59", save_base, 1, m48t59_save, m48t59_load, s); |
647 | 3ccacc4a | blueswir1 | |
648 | c5df018e | bellard | return s;
|
649 | a541f297 | bellard | } |