root / hw / tusb6010.c @ 9c22a623
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1 | 942ac052 | balrog | /*
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2 | 942ac052 | balrog | * Texas Instruments TUSB6010 emulation.
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3 | 942ac052 | balrog | * Based on reverse-engineering of a linux driver.
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4 | 942ac052 | balrog | *
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5 | 942ac052 | balrog | * Copyright (C) 2008 Nokia Corporation
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6 | 942ac052 | balrog | * Written by Andrzej Zaborowski <andrew@openedhand.com>
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7 | 942ac052 | balrog | *
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8 | 942ac052 | balrog | * This program is free software; you can redistribute it and/or
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9 | 942ac052 | balrog | * modify it under the terms of the GNU General Public License as
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10 | 942ac052 | balrog | * published by the Free Software Foundation; either version 2 or
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11 | 942ac052 | balrog | * (at your option) version 3 of the License.
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12 | 942ac052 | balrog | *
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13 | 942ac052 | balrog | * This program is distributed in the hope that it will be useful,
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14 | 942ac052 | balrog | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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15 | 942ac052 | balrog | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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16 | 942ac052 | balrog | * GNU General Public License for more details.
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17 | 942ac052 | balrog | *
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18 | fad6cb1a | aurel32 | * You should have received a copy of the GNU General Public License along
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19 | fad6cb1a | aurel32 | * with this program; if not, write to the Free Software Foundation, Inc.,
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20 | fad6cb1a | aurel32 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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21 | 942ac052 | balrog | */
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22 | 942ac052 | balrog | #include "qemu-common.h" |
23 | 942ac052 | balrog | #include "qemu-timer.h" |
24 | 942ac052 | balrog | #include "usb.h" |
25 | 942ac052 | balrog | #include "omap.h" |
26 | 942ac052 | balrog | #include "irq.h" |
27 | b1d8e52e | blueswir1 | #include "devices.h" |
28 | 942ac052 | balrog | |
29 | 942ac052 | balrog | struct tusb_s {
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30 | 942ac052 | balrog | int iomemtype[2]; |
31 | 942ac052 | balrog | qemu_irq irq; |
32 | 942ac052 | balrog | struct musb_s *musb;
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33 | 942ac052 | balrog | QEMUTimer *otg_timer; |
34 | 942ac052 | balrog | QEMUTimer *pwr_timer; |
35 | 942ac052 | balrog | |
36 | 942ac052 | balrog | int power;
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37 | 942ac052 | balrog | uint32_t scratch; |
38 | 942ac052 | balrog | uint16_t test_reset; |
39 | 942ac052 | balrog | uint32_t prcm_config; |
40 | 942ac052 | balrog | uint32_t prcm_mngmt; |
41 | 942ac052 | balrog | uint16_t otg_status; |
42 | 942ac052 | balrog | uint32_t dev_config; |
43 | 942ac052 | balrog | int host_mode;
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44 | 942ac052 | balrog | uint32_t intr; |
45 | 942ac052 | balrog | uint32_t intr_ok; |
46 | 942ac052 | balrog | uint32_t mask; |
47 | 942ac052 | balrog | uint32_t usbip_intr; |
48 | 942ac052 | balrog | uint32_t usbip_mask; |
49 | 942ac052 | balrog | uint32_t gpio_intr; |
50 | 942ac052 | balrog | uint32_t gpio_mask; |
51 | 942ac052 | balrog | uint32_t gpio_config; |
52 | 942ac052 | balrog | uint32_t dma_intr; |
53 | 942ac052 | balrog | uint32_t dma_mask; |
54 | 942ac052 | balrog | uint32_t dma_map; |
55 | 942ac052 | balrog | uint32_t dma_config; |
56 | 942ac052 | balrog | uint32_t ep0_config; |
57 | 942ac052 | balrog | uint32_t rx_config[15];
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58 | 942ac052 | balrog | uint32_t tx_config[15];
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59 | 942ac052 | balrog | uint32_t wkup_mask; |
60 | 942ac052 | balrog | uint32_t pullup[2];
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61 | 942ac052 | balrog | uint32_t control_config; |
62 | 942ac052 | balrog | uint32_t otg_timer_val; |
63 | 942ac052 | balrog | }; |
64 | 942ac052 | balrog | |
65 | 942ac052 | balrog | #define TUSB_DEVCLOCK 60000000 /* 60 MHz */ |
66 | 942ac052 | balrog | |
67 | 942ac052 | balrog | #define TUSB_VLYNQ_CTRL 0x004 |
68 | 942ac052 | balrog | |
69 | 942ac052 | balrog | /* Mentor Graphics OTG core registers. */
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70 | 942ac052 | balrog | #define TUSB_BASE_OFFSET 0x400 |
71 | 942ac052 | balrog | |
72 | 942ac052 | balrog | /* FIFO registers, 32-bit. */
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73 | 942ac052 | balrog | #define TUSB_FIFO_BASE 0x600 |
74 | 942ac052 | balrog | |
75 | 942ac052 | balrog | /* Device System & Control registers, 32-bit. */
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76 | 942ac052 | balrog | #define TUSB_SYS_REG_BASE 0x800 |
77 | 942ac052 | balrog | |
78 | 942ac052 | balrog | #define TUSB_DEV_CONF (TUSB_SYS_REG_BASE + 0x000) |
79 | 942ac052 | balrog | #define TUSB_DEV_CONF_USB_HOST_MODE (1 << 16) |
80 | 942ac052 | balrog | #define TUSB_DEV_CONF_PROD_TEST_MODE (1 << 15) |
81 | 942ac052 | balrog | #define TUSB_DEV_CONF_SOFT_ID (1 << 1) |
82 | 942ac052 | balrog | #define TUSB_DEV_CONF_ID_SEL (1 << 0) |
83 | 942ac052 | balrog | |
84 | 942ac052 | balrog | #define TUSB_PHY_OTG_CTRL_ENABLE (TUSB_SYS_REG_BASE + 0x004) |
85 | 942ac052 | balrog | #define TUSB_PHY_OTG_CTRL (TUSB_SYS_REG_BASE + 0x008) |
86 | 942ac052 | balrog | #define TUSB_PHY_OTG_CTRL_WRPROTECT (0xa5 << 24) |
87 | 942ac052 | balrog | #define TUSB_PHY_OTG_CTRL_O_ID_PULLUP (1 << 23) |
88 | 942ac052 | balrog | #define TUSB_PHY_OTG_CTRL_O_VBUS_DET_EN (1 << 19) |
89 | 942ac052 | balrog | #define TUSB_PHY_OTG_CTRL_O_SESS_END_EN (1 << 18) |
90 | 942ac052 | balrog | #define TUSB_PHY_OTG_CTRL_TESTM2 (1 << 17) |
91 | 942ac052 | balrog | #define TUSB_PHY_OTG_CTRL_TESTM1 (1 << 16) |
92 | 942ac052 | balrog | #define TUSB_PHY_OTG_CTRL_TESTM0 (1 << 15) |
93 | 942ac052 | balrog | #define TUSB_PHY_OTG_CTRL_TX_DATA2 (1 << 14) |
94 | 942ac052 | balrog | #define TUSB_PHY_OTG_CTRL_TX_GZ2 (1 << 13) |
95 | 942ac052 | balrog | #define TUSB_PHY_OTG_CTRL_TX_ENABLE2 (1 << 12) |
96 | 942ac052 | balrog | #define TUSB_PHY_OTG_CTRL_DM_PULLDOWN (1 << 11) |
97 | 942ac052 | balrog | #define TUSB_PHY_OTG_CTRL_DP_PULLDOWN (1 << 10) |
98 | 942ac052 | balrog | #define TUSB_PHY_OTG_CTRL_OSC_EN (1 << 9) |
99 | 942ac052 | balrog | #define TUSB_PHY_OTG_CTRL_PHYREF_CLK(v) (((v) & 3) << 7) |
100 | 942ac052 | balrog | #define TUSB_PHY_OTG_CTRL_PD (1 << 6) |
101 | 942ac052 | balrog | #define TUSB_PHY_OTG_CTRL_PLL_ON (1 << 5) |
102 | 942ac052 | balrog | #define TUSB_PHY_OTG_CTRL_EXT_RPU (1 << 4) |
103 | 942ac052 | balrog | #define TUSB_PHY_OTG_CTRL_PWR_GOOD (1 << 3) |
104 | 942ac052 | balrog | #define TUSB_PHY_OTG_CTRL_RESET (1 << 2) |
105 | 942ac052 | balrog | #define TUSB_PHY_OTG_CTRL_SUSPENDM (1 << 1) |
106 | 942ac052 | balrog | #define TUSB_PHY_OTG_CTRL_CLK_MODE (1 << 0) |
107 | 942ac052 | balrog | |
108 | 942ac052 | balrog | /* OTG status register */
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109 | 942ac052 | balrog | #define TUSB_DEV_OTG_STAT (TUSB_SYS_REG_BASE + 0x00c) |
110 | 942ac052 | balrog | #define TUSB_DEV_OTG_STAT_PWR_CLK_GOOD (1 << 8) |
111 | 942ac052 | balrog | #define TUSB_DEV_OTG_STAT_SESS_END (1 << 7) |
112 | 942ac052 | balrog | #define TUSB_DEV_OTG_STAT_SESS_VALID (1 << 6) |
113 | 942ac052 | balrog | #define TUSB_DEV_OTG_STAT_VBUS_VALID (1 << 5) |
114 | 942ac052 | balrog | #define TUSB_DEV_OTG_STAT_VBUS_SENSE (1 << 4) |
115 | 942ac052 | balrog | #define TUSB_DEV_OTG_STAT_ID_STATUS (1 << 3) |
116 | 942ac052 | balrog | #define TUSB_DEV_OTG_STAT_HOST_DISCON (1 << 2) |
117 | 942ac052 | balrog | #define TUSB_DEV_OTG_STAT_LINE_STATE (3 << 0) |
118 | 942ac052 | balrog | #define TUSB_DEV_OTG_STAT_DP_ENABLE (1 << 1) |
119 | 942ac052 | balrog | #define TUSB_DEV_OTG_STAT_DM_ENABLE (1 << 0) |
120 | 942ac052 | balrog | |
121 | 942ac052 | balrog | #define TUSB_DEV_OTG_TIMER (TUSB_SYS_REG_BASE + 0x010) |
122 | 942ac052 | balrog | #define TUSB_DEV_OTG_TIMER_ENABLE (1 << 31) |
123 | 942ac052 | balrog | #define TUSB_DEV_OTG_TIMER_VAL(v) ((v) & 0x07ffffff) |
124 | 942ac052 | balrog | #define TUSB_PRCM_REV (TUSB_SYS_REG_BASE + 0x014) |
125 | 942ac052 | balrog | |
126 | 942ac052 | balrog | /* PRCM configuration register */
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127 | 942ac052 | balrog | #define TUSB_PRCM_CONF (TUSB_SYS_REG_BASE + 0x018) |
128 | 942ac052 | balrog | #define TUSB_PRCM_CONF_SFW_CPEN (1 << 24) |
129 | 942ac052 | balrog | #define TUSB_PRCM_CONF_SYS_CLKSEL(v) (((v) & 3) << 16) |
130 | 942ac052 | balrog | |
131 | 942ac052 | balrog | /* PRCM management register */
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132 | 942ac052 | balrog | #define TUSB_PRCM_MNGMT (TUSB_SYS_REG_BASE + 0x01c) |
133 | 942ac052 | balrog | #define TUSB_PRCM_MNGMT_SRP_FIX_TMR(v) (((v) & 0xf) << 25) |
134 | 942ac052 | balrog | #define TUSB_PRCM_MNGMT_SRP_FIX_EN (1 << 24) |
135 | 942ac052 | balrog | #define TUSB_PRCM_MNGMT_VBUS_VAL_TMR(v) (((v) & 0xf) << 20) |
136 | 942ac052 | balrog | #define TUSB_PRCM_MNGMT_VBUS_VAL_FLT_EN (1 << 19) |
137 | 942ac052 | balrog | #define TUSB_PRCM_MNGMT_DFT_CLK_DIS (1 << 18) |
138 | 942ac052 | balrog | #define TUSB_PRCM_MNGMT_VLYNQ_CLK_DIS (1 << 17) |
139 | 942ac052 | balrog | #define TUSB_PRCM_MNGMT_OTG_SESS_END_EN (1 << 10) |
140 | 942ac052 | balrog | #define TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN (1 << 9) |
141 | 942ac052 | balrog | #define TUSB_PRCM_MNGMT_OTG_ID_PULLUP (1 << 8) |
142 | 942ac052 | balrog | #define TUSB_PRCM_MNGMT_15_SW_EN (1 << 4) |
143 | 942ac052 | balrog | #define TUSB_PRCM_MNGMT_33_SW_EN (1 << 3) |
144 | 942ac052 | balrog | #define TUSB_PRCM_MNGMT_5V_CPEN (1 << 2) |
145 | 942ac052 | balrog | #define TUSB_PRCM_MNGMT_PM_IDLE (1 << 1) |
146 | 942ac052 | balrog | #define TUSB_PRCM_MNGMT_DEV_IDLE (1 << 0) |
147 | 942ac052 | balrog | |
148 | 942ac052 | balrog | /* Wake-up source clear and mask registers */
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149 | 942ac052 | balrog | #define TUSB_PRCM_WAKEUP_SOURCE (TUSB_SYS_REG_BASE + 0x020) |
150 | 942ac052 | balrog | #define TUSB_PRCM_WAKEUP_CLEAR (TUSB_SYS_REG_BASE + 0x028) |
151 | 942ac052 | balrog | #define TUSB_PRCM_WAKEUP_MASK (TUSB_SYS_REG_BASE + 0x02c) |
152 | 942ac052 | balrog | #define TUSB_PRCM_WAKEUP_RESERVED_BITS (0xffffe << 13) |
153 | 942ac052 | balrog | #define TUSB_PRCM_WGPIO_7 (1 << 12) |
154 | 942ac052 | balrog | #define TUSB_PRCM_WGPIO_6 (1 << 11) |
155 | 942ac052 | balrog | #define TUSB_PRCM_WGPIO_5 (1 << 10) |
156 | 942ac052 | balrog | #define TUSB_PRCM_WGPIO_4 (1 << 9) |
157 | 942ac052 | balrog | #define TUSB_PRCM_WGPIO_3 (1 << 8) |
158 | 942ac052 | balrog | #define TUSB_PRCM_WGPIO_2 (1 << 7) |
159 | 942ac052 | balrog | #define TUSB_PRCM_WGPIO_1 (1 << 6) |
160 | 942ac052 | balrog | #define TUSB_PRCM_WGPIO_0 (1 << 5) |
161 | 942ac052 | balrog | #define TUSB_PRCM_WHOSTDISCON (1 << 4) /* Host disconnect */ |
162 | 942ac052 | balrog | #define TUSB_PRCM_WBUS (1 << 3) /* USB bus resume */ |
163 | 942ac052 | balrog | #define TUSB_PRCM_WNORCS (1 << 2) /* NOR chip select */ |
164 | 942ac052 | balrog | #define TUSB_PRCM_WVBUS (1 << 1) /* OTG PHY VBUS */ |
165 | 942ac052 | balrog | #define TUSB_PRCM_WID (1 << 0) /* OTG PHY ID detect */ |
166 | 942ac052 | balrog | |
167 | 942ac052 | balrog | #define TUSB_PULLUP_1_CTRL (TUSB_SYS_REG_BASE + 0x030) |
168 | 942ac052 | balrog | #define TUSB_PULLUP_2_CTRL (TUSB_SYS_REG_BASE + 0x034) |
169 | 942ac052 | balrog | #define TUSB_INT_CTRL_REV (TUSB_SYS_REG_BASE + 0x038) |
170 | 942ac052 | balrog | #define TUSB_INT_CTRL_CONF (TUSB_SYS_REG_BASE + 0x03c) |
171 | 942ac052 | balrog | #define TUSB_USBIP_INT_SRC (TUSB_SYS_REG_BASE + 0x040) |
172 | 942ac052 | balrog | #define TUSB_USBIP_INT_SET (TUSB_SYS_REG_BASE + 0x044) |
173 | 942ac052 | balrog | #define TUSB_USBIP_INT_CLEAR (TUSB_SYS_REG_BASE + 0x048) |
174 | 942ac052 | balrog | #define TUSB_USBIP_INT_MASK (TUSB_SYS_REG_BASE + 0x04c) |
175 | 942ac052 | balrog | #define TUSB_DMA_INT_SRC (TUSB_SYS_REG_BASE + 0x050) |
176 | 942ac052 | balrog | #define TUSB_DMA_INT_SET (TUSB_SYS_REG_BASE + 0x054) |
177 | 942ac052 | balrog | #define TUSB_DMA_INT_CLEAR (TUSB_SYS_REG_BASE + 0x058) |
178 | 942ac052 | balrog | #define TUSB_DMA_INT_MASK (TUSB_SYS_REG_BASE + 0x05c) |
179 | 942ac052 | balrog | #define TUSB_GPIO_INT_SRC (TUSB_SYS_REG_BASE + 0x060) |
180 | 942ac052 | balrog | #define TUSB_GPIO_INT_SET (TUSB_SYS_REG_BASE + 0x064) |
181 | 942ac052 | balrog | #define TUSB_GPIO_INT_CLEAR (TUSB_SYS_REG_BASE + 0x068) |
182 | 942ac052 | balrog | #define TUSB_GPIO_INT_MASK (TUSB_SYS_REG_BASE + 0x06c) |
183 | 942ac052 | balrog | |
184 | 942ac052 | balrog | /* NOR flash interrupt source registers */
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185 | 942ac052 | balrog | #define TUSB_INT_SRC (TUSB_SYS_REG_BASE + 0x070) |
186 | 942ac052 | balrog | #define TUSB_INT_SRC_SET (TUSB_SYS_REG_BASE + 0x074) |
187 | 942ac052 | balrog | #define TUSB_INT_SRC_CLEAR (TUSB_SYS_REG_BASE + 0x078) |
188 | 942ac052 | balrog | #define TUSB_INT_MASK (TUSB_SYS_REG_BASE + 0x07c) |
189 | 942ac052 | balrog | #define TUSB_INT_SRC_TXRX_DMA_DONE (1 << 24) |
190 | 942ac052 | balrog | #define TUSB_INT_SRC_USB_IP_CORE (1 << 17) |
191 | 942ac052 | balrog | #define TUSB_INT_SRC_OTG_TIMEOUT (1 << 16) |
192 | 942ac052 | balrog | #define TUSB_INT_SRC_VBUS_SENSE_CHNG (1 << 15) |
193 | 942ac052 | balrog | #define TUSB_INT_SRC_ID_STATUS_CHNG (1 << 14) |
194 | 942ac052 | balrog | #define TUSB_INT_SRC_DEV_WAKEUP (1 << 13) |
195 | 942ac052 | balrog | #define TUSB_INT_SRC_DEV_READY (1 << 12) |
196 | 942ac052 | balrog | #define TUSB_INT_SRC_USB_IP_TX (1 << 9) |
197 | 942ac052 | balrog | #define TUSB_INT_SRC_USB_IP_RX (1 << 8) |
198 | 942ac052 | balrog | #define TUSB_INT_SRC_USB_IP_VBUS_ERR (1 << 7) |
199 | 942ac052 | balrog | #define TUSB_INT_SRC_USB_IP_VBUS_REQ (1 << 6) |
200 | 942ac052 | balrog | #define TUSB_INT_SRC_USB_IP_DISCON (1 << 5) |
201 | 942ac052 | balrog | #define TUSB_INT_SRC_USB_IP_CONN (1 << 4) |
202 | 942ac052 | balrog | #define TUSB_INT_SRC_USB_IP_SOF (1 << 3) |
203 | 942ac052 | balrog | #define TUSB_INT_SRC_USB_IP_RST_BABBLE (1 << 2) |
204 | 942ac052 | balrog | #define TUSB_INT_SRC_USB_IP_RESUME (1 << 1) |
205 | 942ac052 | balrog | #define TUSB_INT_SRC_USB_IP_SUSPEND (1 << 0) |
206 | 942ac052 | balrog | |
207 | 942ac052 | balrog | #define TUSB_GPIO_REV (TUSB_SYS_REG_BASE + 0x080) |
208 | 942ac052 | balrog | #define TUSB_GPIO_CONF (TUSB_SYS_REG_BASE + 0x084) |
209 | 942ac052 | balrog | #define TUSB_DMA_CTRL_REV (TUSB_SYS_REG_BASE + 0x100) |
210 | 942ac052 | balrog | #define TUSB_DMA_REQ_CONF (TUSB_SYS_REG_BASE + 0x104) |
211 | 942ac052 | balrog | #define TUSB_EP0_CONF (TUSB_SYS_REG_BASE + 0x108) |
212 | 942ac052 | balrog | #define TUSB_EP_IN_SIZE (TUSB_SYS_REG_BASE + 0x10c) |
213 | 942ac052 | balrog | #define TUSB_DMA_EP_MAP (TUSB_SYS_REG_BASE + 0x148) |
214 | 942ac052 | balrog | #define TUSB_EP_OUT_SIZE (TUSB_SYS_REG_BASE + 0x14c) |
215 | 942ac052 | balrog | #define TUSB_EP_MAX_PACKET_SIZE_OFFSET (TUSB_SYS_REG_BASE + 0x188) |
216 | 942ac052 | balrog | #define TUSB_SCRATCH_PAD (TUSB_SYS_REG_BASE + 0x1c4) |
217 | 942ac052 | balrog | #define TUSB_WAIT_COUNT (TUSB_SYS_REG_BASE + 0x1c8) |
218 | 942ac052 | balrog | #define TUSB_PROD_TEST_RESET (TUSB_SYS_REG_BASE + 0x1d8) |
219 | 942ac052 | balrog | |
220 | 942ac052 | balrog | #define TUSB_DIDR1_LO (TUSB_SYS_REG_BASE + 0x1f8) |
221 | 942ac052 | balrog | #define TUSB_DIDR1_HI (TUSB_SYS_REG_BASE + 0x1fc) |
222 | 942ac052 | balrog | |
223 | 942ac052 | balrog | /* Device System & Control register bitfields */
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224 | 942ac052 | balrog | #define TUSB_INT_CTRL_CONF_INT_RLCYC(v) (((v) & 0x7) << 18) |
225 | 942ac052 | balrog | #define TUSB_INT_CTRL_CONF_INT_POLARITY (1 << 17) |
226 | 942ac052 | balrog | #define TUSB_INT_CTRL_CONF_INT_MODE (1 << 16) |
227 | 942ac052 | balrog | #define TUSB_GPIO_CONF_DMAREQ(v) (((v) & 0x3f) << 24) |
228 | 942ac052 | balrog | #define TUSB_DMA_REQ_CONF_BURST_SIZE(v) (((v) & 3) << 26) |
229 | 942ac052 | balrog | #define TUSB_DMA_REQ_CONF_DMA_RQ_EN(v) (((v) & 0x3f) << 20) |
230 | 942ac052 | balrog | #define TUSB_DMA_REQ_CONF_DMA_RQ_ASR(v) (((v) & 0xf) << 16) |
231 | 942ac052 | balrog | #define TUSB_EP0_CONFIG_SW_EN (1 << 8) |
232 | 942ac052 | balrog | #define TUSB_EP0_CONFIG_DIR_TX (1 << 7) |
233 | 942ac052 | balrog | #define TUSB_EP0_CONFIG_XFR_SIZE(v) ((v) & 0x7f) |
234 | 942ac052 | balrog | #define TUSB_EP_CONFIG_SW_EN (1 << 31) |
235 | 942ac052 | balrog | #define TUSB_EP_CONFIG_XFR_SIZE(v) ((v) & 0x7fffffff) |
236 | 942ac052 | balrog | #define TUSB_PROD_TEST_RESET_VAL 0xa596 |
237 | 942ac052 | balrog | |
238 | 942ac052 | balrog | int tusb6010_sync_io(struct tusb_s *s) |
239 | 942ac052 | balrog | { |
240 | 942ac052 | balrog | return s->iomemtype[0]; |
241 | 942ac052 | balrog | } |
242 | 942ac052 | balrog | |
243 | 942ac052 | balrog | int tusb6010_async_io(struct tusb_s *s) |
244 | 942ac052 | balrog | { |
245 | 942ac052 | balrog | return s->iomemtype[1]; |
246 | 942ac052 | balrog | } |
247 | 942ac052 | balrog | |
248 | 942ac052 | balrog | static void tusb_intr_update(struct tusb_s *s) |
249 | 942ac052 | balrog | { |
250 | 942ac052 | balrog | if (s->control_config & TUSB_INT_CTRL_CONF_INT_POLARITY)
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251 | 942ac052 | balrog | qemu_set_irq(s->irq, s->intr & ~s->mask & s->intr_ok); |
252 | 942ac052 | balrog | else
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253 | 942ac052 | balrog | qemu_set_irq(s->irq, (!(s->intr & ~s->mask)) & s->intr_ok); |
254 | 942ac052 | balrog | } |
255 | 942ac052 | balrog | |
256 | 942ac052 | balrog | static void tusb_usbip_intr_update(struct tusb_s *s) |
257 | 942ac052 | balrog | { |
258 | 942ac052 | balrog | /* TX interrupt in the MUSB */
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259 | 942ac052 | balrog | if (s->usbip_intr & 0x0000ffff & ~s->usbip_mask) |
260 | 942ac052 | balrog | s->intr |= TUSB_INT_SRC_USB_IP_TX; |
261 | 942ac052 | balrog | else
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262 | 942ac052 | balrog | s->intr &= ~TUSB_INT_SRC_USB_IP_TX; |
263 | 942ac052 | balrog | |
264 | 942ac052 | balrog | /* RX interrupt in the MUSB */
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265 | 942ac052 | balrog | if (s->usbip_intr & 0xffff0000 & ~s->usbip_mask) |
266 | 942ac052 | balrog | s->intr |= TUSB_INT_SRC_USB_IP_RX; |
267 | 942ac052 | balrog | else
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268 | 942ac052 | balrog | s->intr &= ~TUSB_INT_SRC_USB_IP_RX; |
269 | 942ac052 | balrog | |
270 | 942ac052 | balrog | /* XXX: What about TUSB_INT_SRC_USB_IP_CORE? */
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271 | 942ac052 | balrog | |
272 | 942ac052 | balrog | tusb_intr_update(s); |
273 | 942ac052 | balrog | } |
274 | 942ac052 | balrog | |
275 | 942ac052 | balrog | static void tusb_dma_intr_update(struct tusb_s *s) |
276 | 942ac052 | balrog | { |
277 | 942ac052 | balrog | if (s->dma_intr & ~s->dma_mask)
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278 | 942ac052 | balrog | s->intr |= TUSB_INT_SRC_TXRX_DMA_DONE; |
279 | 942ac052 | balrog | else
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280 | 942ac052 | balrog | s->intr &= ~TUSB_INT_SRC_TXRX_DMA_DONE; |
281 | 942ac052 | balrog | |
282 | 942ac052 | balrog | tusb_intr_update(s); |
283 | 942ac052 | balrog | } |
284 | 942ac052 | balrog | |
285 | 942ac052 | balrog | static void tusb_gpio_intr_update(struct tusb_s *s) |
286 | 942ac052 | balrog | { |
287 | 942ac052 | balrog | /* TODO: How is this signalled? */
|
288 | 942ac052 | balrog | } |
289 | 942ac052 | balrog | |
290 | 942ac052 | balrog | extern CPUReadMemoryFunc *musb_read[];
|
291 | 942ac052 | balrog | extern CPUWriteMemoryFunc *musb_write[];
|
292 | 942ac052 | balrog | |
293 | 942ac052 | balrog | static uint32_t tusb_async_readb(void *opaque, target_phys_addr_t addr) |
294 | 942ac052 | balrog | { |
295 | 942ac052 | balrog | struct tusb_s *s = (struct tusb_s *) opaque; |
296 | 942ac052 | balrog | |
297 | 942ac052 | balrog | switch (addr & 0xfff) { |
298 | 942ac052 | balrog | case TUSB_BASE_OFFSET ... (TUSB_BASE_OFFSET | 0x1ff): |
299 | 942ac052 | balrog | return musb_read[0](s->musb, addr & 0x1ff); |
300 | 942ac052 | balrog | |
301 | 942ac052 | balrog | case TUSB_FIFO_BASE ... (TUSB_FIFO_BASE | 0x1ff): |
302 | 942ac052 | balrog | return musb_read[0](s->musb, 0x20 + ((addr >> 3) & 0x3c)); |
303 | 942ac052 | balrog | } |
304 | 942ac052 | balrog | |
305 | 942ac052 | balrog | printf("%s: unknown register at %03x\n",
|
306 | 942ac052 | balrog | __FUNCTION__, (int) (addr & 0xfff)); |
307 | 942ac052 | balrog | return 0; |
308 | 942ac052 | balrog | } |
309 | 942ac052 | balrog | |
310 | 942ac052 | balrog | static uint32_t tusb_async_readh(void *opaque, target_phys_addr_t addr) |
311 | 942ac052 | balrog | { |
312 | 942ac052 | balrog | struct tusb_s *s = (struct tusb_s *) opaque; |
313 | 942ac052 | balrog | |
314 | 942ac052 | balrog | switch (addr & 0xfff) { |
315 | 942ac052 | balrog | case TUSB_BASE_OFFSET ... (TUSB_BASE_OFFSET | 0x1ff): |
316 | 942ac052 | balrog | return musb_read[1](s->musb, addr & 0x1ff); |
317 | 942ac052 | balrog | |
318 | 942ac052 | balrog | case TUSB_FIFO_BASE ... (TUSB_FIFO_BASE | 0x1ff): |
319 | 942ac052 | balrog | return musb_read[1](s->musb, 0x20 + ((addr >> 3) & 0x3c)); |
320 | 942ac052 | balrog | } |
321 | 942ac052 | balrog | |
322 | 942ac052 | balrog | printf("%s: unknown register at %03x\n",
|
323 | 942ac052 | balrog | __FUNCTION__, (int) (addr & 0xfff)); |
324 | 942ac052 | balrog | return 0; |
325 | 942ac052 | balrog | } |
326 | 942ac052 | balrog | |
327 | 942ac052 | balrog | static uint32_t tusb_async_readw(void *opaque, target_phys_addr_t addr) |
328 | 942ac052 | balrog | { |
329 | 942ac052 | balrog | struct tusb_s *s = (struct tusb_s *) opaque; |
330 | 942ac052 | balrog | int offset = addr & 0xfff; |
331 | 942ac052 | balrog | int epnum;
|
332 | 942ac052 | balrog | uint32_t ret; |
333 | 942ac052 | balrog | |
334 | 942ac052 | balrog | switch (offset) {
|
335 | 942ac052 | balrog | case TUSB_DEV_CONF:
|
336 | 942ac052 | balrog | return s->dev_config;
|
337 | 942ac052 | balrog | |
338 | 942ac052 | balrog | case TUSB_BASE_OFFSET ... (TUSB_BASE_OFFSET | 0x1ff): |
339 | 942ac052 | balrog | return musb_read[2](s->musb, offset & 0x1ff); |
340 | 942ac052 | balrog | |
341 | 942ac052 | balrog | case TUSB_FIFO_BASE ... (TUSB_FIFO_BASE | 0x1ff): |
342 | 942ac052 | balrog | return musb_read[2](s->musb, 0x20 + ((addr >> 3) & 0x3c)); |
343 | 942ac052 | balrog | |
344 | 942ac052 | balrog | case TUSB_PHY_OTG_CTRL_ENABLE:
|
345 | 942ac052 | balrog | case TUSB_PHY_OTG_CTRL:
|
346 | 942ac052 | balrog | return 0x00; /* TODO */ |
347 | 942ac052 | balrog | |
348 | 942ac052 | balrog | case TUSB_DEV_OTG_STAT:
|
349 | 942ac052 | balrog | ret = s->otg_status; |
350 | 942ac052 | balrog | #if 0
|
351 | 942ac052 | balrog | if (!(s->prcm_mngmt & TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN))
|
352 | 942ac052 | balrog | ret &= ~TUSB_DEV_OTG_STAT_VBUS_VALID;
|
353 | 942ac052 | balrog | #endif
|
354 | 942ac052 | balrog | return ret;
|
355 | 942ac052 | balrog | case TUSB_DEV_OTG_TIMER:
|
356 | 942ac052 | balrog | return s->otg_timer_val;
|
357 | 942ac052 | balrog | |
358 | 942ac052 | balrog | case TUSB_PRCM_REV:
|
359 | 942ac052 | balrog | return 0x20; |
360 | 942ac052 | balrog | case TUSB_PRCM_CONF:
|
361 | 942ac052 | balrog | return s->prcm_config;
|
362 | 942ac052 | balrog | case TUSB_PRCM_MNGMT:
|
363 | 942ac052 | balrog | return s->prcm_mngmt;
|
364 | 942ac052 | balrog | case TUSB_PRCM_WAKEUP_SOURCE:
|
365 | 942ac052 | balrog | case TUSB_PRCM_WAKEUP_CLEAR: /* TODO: What does this one return? */ |
366 | 942ac052 | balrog | return 0x00000000; |
367 | 942ac052 | balrog | case TUSB_PRCM_WAKEUP_MASK:
|
368 | 942ac052 | balrog | return s->wkup_mask;
|
369 | 942ac052 | balrog | |
370 | 942ac052 | balrog | case TUSB_PULLUP_1_CTRL:
|
371 | 942ac052 | balrog | return s->pullup[0]; |
372 | 942ac052 | balrog | case TUSB_PULLUP_2_CTRL:
|
373 | 942ac052 | balrog | return s->pullup[1]; |
374 | 942ac052 | balrog | |
375 | 942ac052 | balrog | case TUSB_INT_CTRL_REV:
|
376 | 942ac052 | balrog | return 0x20; |
377 | 942ac052 | balrog | case TUSB_INT_CTRL_CONF:
|
378 | 942ac052 | balrog | return s->control_config;
|
379 | 942ac052 | balrog | |
380 | 942ac052 | balrog | case TUSB_USBIP_INT_SRC:
|
381 | 942ac052 | balrog | case TUSB_USBIP_INT_SET: /* TODO: What do these two return? */ |
382 | 942ac052 | balrog | case TUSB_USBIP_INT_CLEAR:
|
383 | 942ac052 | balrog | return s->usbip_intr;
|
384 | 942ac052 | balrog | case TUSB_USBIP_INT_MASK:
|
385 | 942ac052 | balrog | return s->usbip_mask;
|
386 | 942ac052 | balrog | |
387 | 942ac052 | balrog | case TUSB_DMA_INT_SRC:
|
388 | 942ac052 | balrog | case TUSB_DMA_INT_SET: /* TODO: What do these two return? */ |
389 | 942ac052 | balrog | case TUSB_DMA_INT_CLEAR:
|
390 | 942ac052 | balrog | return s->dma_intr;
|
391 | 942ac052 | balrog | case TUSB_DMA_INT_MASK:
|
392 | 942ac052 | balrog | return s->dma_mask;
|
393 | 942ac052 | balrog | |
394 | 942ac052 | balrog | case TUSB_GPIO_INT_SRC: /* TODO: What do these two return? */ |
395 | 942ac052 | balrog | case TUSB_GPIO_INT_SET:
|
396 | 942ac052 | balrog | case TUSB_GPIO_INT_CLEAR:
|
397 | 942ac052 | balrog | return s->gpio_intr;
|
398 | 942ac052 | balrog | case TUSB_GPIO_INT_MASK:
|
399 | 942ac052 | balrog | return s->gpio_mask;
|
400 | 942ac052 | balrog | |
401 | 942ac052 | balrog | case TUSB_INT_SRC:
|
402 | 942ac052 | balrog | case TUSB_INT_SRC_SET: /* TODO: What do these two return? */ |
403 | 942ac052 | balrog | case TUSB_INT_SRC_CLEAR:
|
404 | 942ac052 | balrog | return s->intr;
|
405 | 942ac052 | balrog | case TUSB_INT_MASK:
|
406 | 942ac052 | balrog | return s->mask;
|
407 | 942ac052 | balrog | |
408 | 942ac052 | balrog | case TUSB_GPIO_REV:
|
409 | 942ac052 | balrog | return 0x30; |
410 | 942ac052 | balrog | case TUSB_GPIO_CONF:
|
411 | 942ac052 | balrog | return s->gpio_config;
|
412 | 942ac052 | balrog | |
413 | 942ac052 | balrog | case TUSB_DMA_CTRL_REV:
|
414 | 942ac052 | balrog | return 0x30; |
415 | 942ac052 | balrog | case TUSB_DMA_REQ_CONF:
|
416 | 942ac052 | balrog | return s->dma_config;
|
417 | 942ac052 | balrog | case TUSB_EP0_CONF:
|
418 | 942ac052 | balrog | return s->ep0_config;
|
419 | 942ac052 | balrog | case TUSB_EP_IN_SIZE ... (TUSB_EP_IN_SIZE + 0x3b): |
420 | 942ac052 | balrog | epnum = (offset - TUSB_EP_IN_SIZE) >> 2;
|
421 | 942ac052 | balrog | return s->tx_config[epnum];
|
422 | 942ac052 | balrog | case TUSB_DMA_EP_MAP:
|
423 | 942ac052 | balrog | return s->dma_map;
|
424 | 942ac052 | balrog | case TUSB_EP_OUT_SIZE ... (TUSB_EP_OUT_SIZE + 0x3b): |
425 | 942ac052 | balrog | epnum = (offset - TUSB_EP_OUT_SIZE) >> 2;
|
426 | 942ac052 | balrog | return s->rx_config[epnum];
|
427 | 942ac052 | balrog | case TUSB_EP_MAX_PACKET_SIZE_OFFSET ...
|
428 | 942ac052 | balrog | (TUSB_EP_MAX_PACKET_SIZE_OFFSET + 0x3b):
|
429 | 942ac052 | balrog | epnum = (offset - TUSB_EP_MAX_PACKET_SIZE_OFFSET) >> 2;
|
430 | 942ac052 | balrog | return 0x00000000; /* TODO */ |
431 | 942ac052 | balrog | case TUSB_WAIT_COUNT:
|
432 | 942ac052 | balrog | return 0x00; /* TODO */ |
433 | 942ac052 | balrog | |
434 | 942ac052 | balrog | case TUSB_SCRATCH_PAD:
|
435 | 942ac052 | balrog | return s->scratch;
|
436 | 942ac052 | balrog | |
437 | 942ac052 | balrog | case TUSB_PROD_TEST_RESET:
|
438 | 942ac052 | balrog | return s->test_reset;
|
439 | 942ac052 | balrog | |
440 | 942ac052 | balrog | /* DIE IDs */
|
441 | 942ac052 | balrog | case TUSB_DIDR1_LO:
|
442 | 942ac052 | balrog | return 0xa9453c59; |
443 | 942ac052 | balrog | case TUSB_DIDR1_HI:
|
444 | 942ac052 | balrog | return 0x54059adf; |
445 | 942ac052 | balrog | } |
446 | 942ac052 | balrog | |
447 | 942ac052 | balrog | printf("%s: unknown register at %03x\n", __FUNCTION__, offset);
|
448 | 942ac052 | balrog | return 0; |
449 | 942ac052 | balrog | } |
450 | 942ac052 | balrog | |
451 | 942ac052 | balrog | static void tusb_async_writeb(void *opaque, target_phys_addr_t addr, |
452 | 942ac052 | balrog | uint32_t value) |
453 | 942ac052 | balrog | { |
454 | 942ac052 | balrog | struct tusb_s *s = (struct tusb_s *) opaque; |
455 | 942ac052 | balrog | |
456 | 942ac052 | balrog | switch (addr & 0xfff) { |
457 | 942ac052 | balrog | case TUSB_BASE_OFFSET ... (TUSB_BASE_OFFSET | 0x1ff): |
458 | 942ac052 | balrog | musb_write[0](s->musb, addr & 0x1ff, value); |
459 | 942ac052 | balrog | break;
|
460 | 942ac052 | balrog | |
461 | 942ac052 | balrog | case TUSB_FIFO_BASE ... (TUSB_FIFO_BASE | 0x1ff): |
462 | 942ac052 | balrog | musb_write[0](s->musb, 0x20 + ((addr >> 3) & 0x3c), value); |
463 | 942ac052 | balrog | break;
|
464 | 942ac052 | balrog | |
465 | 942ac052 | balrog | default:
|
466 | 942ac052 | balrog | printf("%s: unknown register at %03x\n",
|
467 | 942ac052 | balrog | __FUNCTION__, (int) (addr & 0xfff)); |
468 | 942ac052 | balrog | return;
|
469 | 942ac052 | balrog | } |
470 | 942ac052 | balrog | } |
471 | 942ac052 | balrog | |
472 | 942ac052 | balrog | static void tusb_async_writeh(void *opaque, target_phys_addr_t addr, |
473 | 942ac052 | balrog | uint32_t value) |
474 | 942ac052 | balrog | { |
475 | 942ac052 | balrog | struct tusb_s *s = (struct tusb_s *) opaque; |
476 | 942ac052 | balrog | |
477 | 942ac052 | balrog | switch (addr & 0xfff) { |
478 | 942ac052 | balrog | case TUSB_BASE_OFFSET ... (TUSB_BASE_OFFSET | 0x1ff): |
479 | 942ac052 | balrog | musb_write[1](s->musb, addr & 0x1ff, value); |
480 | 942ac052 | balrog | break;
|
481 | 942ac052 | balrog | |
482 | 942ac052 | balrog | case TUSB_FIFO_BASE ... (TUSB_FIFO_BASE | 0x1ff): |
483 | 942ac052 | balrog | musb_write[1](s->musb, 0x20 + ((addr >> 3) & 0x3c), value); |
484 | 942ac052 | balrog | break;
|
485 | 942ac052 | balrog | |
486 | 942ac052 | balrog | default:
|
487 | 942ac052 | balrog | printf("%s: unknown register at %03x\n",
|
488 | 942ac052 | balrog | __FUNCTION__, (int) (addr & 0xfff)); |
489 | 942ac052 | balrog | return;
|
490 | 942ac052 | balrog | } |
491 | 942ac052 | balrog | } |
492 | 942ac052 | balrog | |
493 | 942ac052 | balrog | static void tusb_async_writew(void *opaque, target_phys_addr_t addr, |
494 | 942ac052 | balrog | uint32_t value) |
495 | 942ac052 | balrog | { |
496 | 942ac052 | balrog | struct tusb_s *s = (struct tusb_s *) opaque; |
497 | 942ac052 | balrog | int offset = addr & 0xfff; |
498 | 942ac052 | balrog | int epnum;
|
499 | 942ac052 | balrog | |
500 | 942ac052 | balrog | switch (offset) {
|
501 | 942ac052 | balrog | case TUSB_VLYNQ_CTRL:
|
502 | 942ac052 | balrog | break;
|
503 | 942ac052 | balrog | |
504 | 942ac052 | balrog | case TUSB_BASE_OFFSET ... (TUSB_BASE_OFFSET | 0x1ff): |
505 | 942ac052 | balrog | musb_write[2](s->musb, offset & 0x1ff, value); |
506 | 942ac052 | balrog | break;
|
507 | 942ac052 | balrog | |
508 | 942ac052 | balrog | case TUSB_FIFO_BASE ... (TUSB_FIFO_BASE | 0x1ff): |
509 | 942ac052 | balrog | musb_write[2](s->musb, 0x20 + ((addr >> 3) & 0x3c), value); |
510 | 942ac052 | balrog | break;
|
511 | 942ac052 | balrog | |
512 | 942ac052 | balrog | case TUSB_DEV_CONF:
|
513 | 942ac052 | balrog | s->dev_config = value; |
514 | 942ac052 | balrog | s->host_mode = (value & TUSB_DEV_CONF_USB_HOST_MODE); |
515 | 942ac052 | balrog | if (value & TUSB_DEV_CONF_PROD_TEST_MODE)
|
516 | 942ac052 | balrog | cpu_abort(cpu_single_env, "%s: Product Test mode not allowed\n",
|
517 | 942ac052 | balrog | __FUNCTION__); |
518 | 942ac052 | balrog | break;
|
519 | 942ac052 | balrog | |
520 | 942ac052 | balrog | case TUSB_PHY_OTG_CTRL_ENABLE:
|
521 | 942ac052 | balrog | case TUSB_PHY_OTG_CTRL:
|
522 | 942ac052 | balrog | return; /* TODO */ |
523 | 942ac052 | balrog | case TUSB_DEV_OTG_TIMER:
|
524 | 942ac052 | balrog | s->otg_timer_val = value; |
525 | 942ac052 | balrog | if (value & TUSB_DEV_OTG_TIMER_ENABLE)
|
526 | 942ac052 | balrog | qemu_mod_timer(s->otg_timer, qemu_get_clock(vm_clock) + |
527 | 942ac052 | balrog | muldiv64(TUSB_DEV_OTG_TIMER_VAL(value), |
528 | 942ac052 | balrog | ticks_per_sec, TUSB_DEVCLOCK)); |
529 | 942ac052 | balrog | else
|
530 | 942ac052 | balrog | qemu_del_timer(s->otg_timer); |
531 | 942ac052 | balrog | break;
|
532 | 942ac052 | balrog | |
533 | 942ac052 | balrog | case TUSB_PRCM_CONF:
|
534 | 942ac052 | balrog | s->prcm_config = value; |
535 | 942ac052 | balrog | break;
|
536 | 942ac052 | balrog | case TUSB_PRCM_MNGMT:
|
537 | 942ac052 | balrog | s->prcm_mngmt = value; |
538 | 942ac052 | balrog | break;
|
539 | 942ac052 | balrog | case TUSB_PRCM_WAKEUP_CLEAR:
|
540 | 942ac052 | balrog | break;
|
541 | 942ac052 | balrog | case TUSB_PRCM_WAKEUP_MASK:
|
542 | 942ac052 | balrog | s->wkup_mask = value; |
543 | 942ac052 | balrog | break;
|
544 | 942ac052 | balrog | |
545 | 942ac052 | balrog | case TUSB_PULLUP_1_CTRL:
|
546 | 942ac052 | balrog | s->pullup[0] = value;
|
547 | 942ac052 | balrog | break;
|
548 | 942ac052 | balrog | case TUSB_PULLUP_2_CTRL:
|
549 | 942ac052 | balrog | s->pullup[1] = value;
|
550 | 942ac052 | balrog | break;
|
551 | 942ac052 | balrog | case TUSB_INT_CTRL_CONF:
|
552 | 942ac052 | balrog | s->control_config = value; |
553 | 942ac052 | balrog | tusb_intr_update(s); |
554 | 942ac052 | balrog | break;
|
555 | 942ac052 | balrog | |
556 | 942ac052 | balrog | case TUSB_USBIP_INT_SET:
|
557 | 942ac052 | balrog | s->usbip_intr |= value; |
558 | 942ac052 | balrog | tusb_usbip_intr_update(s); |
559 | 942ac052 | balrog | break;
|
560 | 942ac052 | balrog | case TUSB_USBIP_INT_CLEAR:
|
561 | 942ac052 | balrog | s->usbip_intr &= ~value; |
562 | 942ac052 | balrog | tusb_usbip_intr_update(s); |
563 | 942ac052 | balrog | musb_core_intr_clear(s->musb, ~value); |
564 | 942ac052 | balrog | break;
|
565 | 942ac052 | balrog | case TUSB_USBIP_INT_MASK:
|
566 | 942ac052 | balrog | s->usbip_mask = value; |
567 | 942ac052 | balrog | tusb_usbip_intr_update(s); |
568 | 942ac052 | balrog | break;
|
569 | 942ac052 | balrog | |
570 | 942ac052 | balrog | case TUSB_DMA_INT_SET:
|
571 | 942ac052 | balrog | s->dma_intr |= value; |
572 | 942ac052 | balrog | tusb_dma_intr_update(s); |
573 | 942ac052 | balrog | break;
|
574 | 942ac052 | balrog | case TUSB_DMA_INT_CLEAR:
|
575 | 942ac052 | balrog | s->dma_intr &= ~value; |
576 | 942ac052 | balrog | tusb_dma_intr_update(s); |
577 | 942ac052 | balrog | break;
|
578 | 942ac052 | balrog | case TUSB_DMA_INT_MASK:
|
579 | 942ac052 | balrog | s->dma_mask = value; |
580 | 942ac052 | balrog | tusb_dma_intr_update(s); |
581 | 942ac052 | balrog | break;
|
582 | 942ac052 | balrog | |
583 | 942ac052 | balrog | case TUSB_GPIO_INT_SET:
|
584 | 942ac052 | balrog | s->gpio_intr |= value; |
585 | 942ac052 | balrog | tusb_gpio_intr_update(s); |
586 | 942ac052 | balrog | break;
|
587 | 942ac052 | balrog | case TUSB_GPIO_INT_CLEAR:
|
588 | 942ac052 | balrog | s->gpio_intr &= ~value; |
589 | 942ac052 | balrog | tusb_gpio_intr_update(s); |
590 | 942ac052 | balrog | break;
|
591 | 942ac052 | balrog | case TUSB_GPIO_INT_MASK:
|
592 | 942ac052 | balrog | s->gpio_mask = value; |
593 | 942ac052 | balrog | tusb_gpio_intr_update(s); |
594 | 942ac052 | balrog | break;
|
595 | 942ac052 | balrog | |
596 | 942ac052 | balrog | case TUSB_INT_SRC_SET:
|
597 | 942ac052 | balrog | s->intr |= value; |
598 | 942ac052 | balrog | tusb_intr_update(s); |
599 | 942ac052 | balrog | break;
|
600 | 942ac052 | balrog | case TUSB_INT_SRC_CLEAR:
|
601 | 942ac052 | balrog | s->intr &= ~value; |
602 | 942ac052 | balrog | tusb_intr_update(s); |
603 | 942ac052 | balrog | break;
|
604 | 942ac052 | balrog | case TUSB_INT_MASK:
|
605 | 942ac052 | balrog | s->mask = value; |
606 | 942ac052 | balrog | tusb_intr_update(s); |
607 | 942ac052 | balrog | break;
|
608 | 942ac052 | balrog | |
609 | 942ac052 | balrog | case TUSB_GPIO_CONF:
|
610 | 942ac052 | balrog | s->gpio_config = value; |
611 | 942ac052 | balrog | break;
|
612 | 942ac052 | balrog | case TUSB_DMA_REQ_CONF:
|
613 | 942ac052 | balrog | s->dma_config = value; |
614 | 942ac052 | balrog | break;
|
615 | 942ac052 | balrog | case TUSB_EP0_CONF:
|
616 | 942ac052 | balrog | s->ep0_config = value & 0x1ff;
|
617 | 942ac052 | balrog | musb_set_size(s->musb, 0, TUSB_EP0_CONFIG_XFR_SIZE(value),
|
618 | 942ac052 | balrog | value & TUSB_EP0_CONFIG_DIR_TX); |
619 | 942ac052 | balrog | break;
|
620 | 942ac052 | balrog | case TUSB_EP_IN_SIZE ... (TUSB_EP_IN_SIZE + 0x3b): |
621 | 942ac052 | balrog | epnum = (offset - TUSB_EP_IN_SIZE) >> 2;
|
622 | 942ac052 | balrog | s->tx_config[epnum] = value; |
623 | 942ac052 | balrog | musb_set_size(s->musb, epnum + 1, TUSB_EP_CONFIG_XFR_SIZE(value), 1); |
624 | 942ac052 | balrog | break;
|
625 | 942ac052 | balrog | case TUSB_DMA_EP_MAP:
|
626 | 942ac052 | balrog | s->dma_map = value; |
627 | 942ac052 | balrog | break;
|
628 | 942ac052 | balrog | case TUSB_EP_OUT_SIZE ... (TUSB_EP_OUT_SIZE + 0x3b): |
629 | 942ac052 | balrog | epnum = (offset - TUSB_EP_OUT_SIZE) >> 2;
|
630 | 942ac052 | balrog | s->rx_config[epnum] = value; |
631 | 942ac052 | balrog | musb_set_size(s->musb, epnum + 1, TUSB_EP_CONFIG_XFR_SIZE(value), 0); |
632 | 942ac052 | balrog | break;
|
633 | 942ac052 | balrog | case TUSB_EP_MAX_PACKET_SIZE_OFFSET ...
|
634 | 942ac052 | balrog | (TUSB_EP_MAX_PACKET_SIZE_OFFSET + 0x3b):
|
635 | 942ac052 | balrog | epnum = (offset - TUSB_EP_MAX_PACKET_SIZE_OFFSET) >> 2;
|
636 | 942ac052 | balrog | return; /* TODO */ |
637 | 942ac052 | balrog | case TUSB_WAIT_COUNT:
|
638 | 942ac052 | balrog | return; /* TODO */ |
639 | 942ac052 | balrog | |
640 | 942ac052 | balrog | case TUSB_SCRATCH_PAD:
|
641 | 942ac052 | balrog | s->scratch = value; |
642 | 942ac052 | balrog | break;
|
643 | 942ac052 | balrog | |
644 | 942ac052 | balrog | case TUSB_PROD_TEST_RESET:
|
645 | 942ac052 | balrog | s->test_reset = value; |
646 | 942ac052 | balrog | break;
|
647 | 942ac052 | balrog | |
648 | 942ac052 | balrog | default:
|
649 | 942ac052 | balrog | printf("%s: unknown register at %03x\n", __FUNCTION__, offset);
|
650 | 942ac052 | balrog | return;
|
651 | 942ac052 | balrog | } |
652 | 942ac052 | balrog | } |
653 | 942ac052 | balrog | |
654 | 942ac052 | balrog | static CPUReadMemoryFunc *tusb_async_readfn[] = {
|
655 | 942ac052 | balrog | tusb_async_readb, |
656 | 942ac052 | balrog | tusb_async_readh, |
657 | 942ac052 | balrog | tusb_async_readw, |
658 | 942ac052 | balrog | }; |
659 | 942ac052 | balrog | |
660 | 942ac052 | balrog | static CPUWriteMemoryFunc *tusb_async_writefn[] = {
|
661 | 942ac052 | balrog | tusb_async_writeb, |
662 | 942ac052 | balrog | tusb_async_writeh, |
663 | 942ac052 | balrog | tusb_async_writew, |
664 | 942ac052 | balrog | }; |
665 | 942ac052 | balrog | |
666 | 942ac052 | balrog | static void tusb_otg_tick(void *opaque) |
667 | 942ac052 | balrog | { |
668 | 942ac052 | balrog | struct tusb_s *s = (struct tusb_s *) opaque; |
669 | 942ac052 | balrog | |
670 | 942ac052 | balrog | s->otg_timer_val = 0;
|
671 | 942ac052 | balrog | s->intr |= TUSB_INT_SRC_OTG_TIMEOUT; |
672 | 942ac052 | balrog | tusb_intr_update(s); |
673 | 942ac052 | balrog | } |
674 | 942ac052 | balrog | |
675 | 942ac052 | balrog | static void tusb_power_tick(void *opaque) |
676 | 942ac052 | balrog | { |
677 | 942ac052 | balrog | struct tusb_s *s = (struct tusb_s *) opaque; |
678 | 942ac052 | balrog | |
679 | 942ac052 | balrog | if (s->power) {
|
680 | 942ac052 | balrog | s->intr_ok = ~0;
|
681 | 942ac052 | balrog | tusb_intr_update(s); |
682 | 942ac052 | balrog | } |
683 | 942ac052 | balrog | } |
684 | 942ac052 | balrog | |
685 | 942ac052 | balrog | static void tusb_musb_core_intr(void *opaque, int source, int level) |
686 | 942ac052 | balrog | { |
687 | 942ac052 | balrog | struct tusb_s *s = (struct tusb_s *) opaque; |
688 | 942ac052 | balrog | uint16_t otg_status = s->otg_status; |
689 | 942ac052 | balrog | |
690 | 942ac052 | balrog | switch (source) {
|
691 | 942ac052 | balrog | case musb_set_vbus:
|
692 | 942ac052 | balrog | if (level)
|
693 | 942ac052 | balrog | otg_status |= TUSB_DEV_OTG_STAT_VBUS_VALID; |
694 | 942ac052 | balrog | else
|
695 | 942ac052 | balrog | otg_status &= ~TUSB_DEV_OTG_STAT_VBUS_VALID; |
696 | 942ac052 | balrog | |
697 | 942ac052 | balrog | /* XXX: only if TUSB_PHY_OTG_CTRL_OTG_VBUS_DET_EN set? */
|
698 | 942ac052 | balrog | /* XXX: only if TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN set? */
|
699 | 942ac052 | balrog | if (s->otg_status != otg_status) {
|
700 | 942ac052 | balrog | s->otg_status = otg_status; |
701 | 942ac052 | balrog | s->intr |= TUSB_INT_SRC_VBUS_SENSE_CHNG; |
702 | 942ac052 | balrog | tusb_intr_update(s); |
703 | 942ac052 | balrog | } |
704 | 942ac052 | balrog | break;
|
705 | 942ac052 | balrog | |
706 | 942ac052 | balrog | case musb_set_session:
|
707 | 942ac052 | balrog | /* XXX: only if TUSB_PHY_OTG_CTRL_OTG_SESS_END_EN set? */
|
708 | 942ac052 | balrog | /* XXX: only if TUSB_PRCM_MNGMT_OTG_SESS_END_EN set? */
|
709 | 942ac052 | balrog | if (level) {
|
710 | 942ac052 | balrog | s->otg_status |= TUSB_DEV_OTG_STAT_SESS_VALID; |
711 | 942ac052 | balrog | s->otg_status &= ~TUSB_DEV_OTG_STAT_SESS_END; |
712 | 942ac052 | balrog | } else {
|
713 | 942ac052 | balrog | s->otg_status &= ~TUSB_DEV_OTG_STAT_SESS_VALID; |
714 | 942ac052 | balrog | s->otg_status |= TUSB_DEV_OTG_STAT_SESS_END; |
715 | 942ac052 | balrog | } |
716 | 942ac052 | balrog | |
717 | 942ac052 | balrog | /* XXX: some IRQ or anything? */
|
718 | 942ac052 | balrog | break;
|
719 | 942ac052 | balrog | |
720 | 942ac052 | balrog | case musb_irq_tx:
|
721 | 942ac052 | balrog | case musb_irq_rx:
|
722 | 942ac052 | balrog | s->usbip_intr = musb_core_intr_get(s->musb); |
723 | 942ac052 | balrog | /* Fall through. */
|
724 | 942ac052 | balrog | default:
|
725 | 942ac052 | balrog | if (level)
|
726 | 942ac052 | balrog | s->intr |= 1 << source;
|
727 | 942ac052 | balrog | else
|
728 | 942ac052 | balrog | s->intr &= ~(1 << source);
|
729 | 942ac052 | balrog | tusb_intr_update(s); |
730 | 942ac052 | balrog | break;
|
731 | 942ac052 | balrog | } |
732 | 942ac052 | balrog | } |
733 | 942ac052 | balrog | |
734 | 942ac052 | balrog | struct tusb_s *tusb6010_init(qemu_irq intr)
|
735 | 942ac052 | balrog | { |
736 | 942ac052 | balrog | struct tusb_s *s = qemu_mallocz(sizeof(*s)); |
737 | 942ac052 | balrog | |
738 | 942ac052 | balrog | s->test_reset = TUSB_PROD_TEST_RESET_VAL; |
739 | 942ac052 | balrog | s->host_mode = 0;
|
740 | 942ac052 | balrog | s->dev_config = 0;
|
741 | 942ac052 | balrog | s->otg_status = 0; /* !TUSB_DEV_OTG_STAT_ID_STATUS means host mode */ |
742 | 942ac052 | balrog | s->power = 0;
|
743 | 942ac052 | balrog | s->mask = 0xffffffff;
|
744 | 942ac052 | balrog | s->intr = 0x00000000;
|
745 | 942ac052 | balrog | s->otg_timer_val = 0;
|
746 | 942ac052 | balrog | s->iomemtype[1] = cpu_register_io_memory(0, tusb_async_readfn, |
747 | 942ac052 | balrog | tusb_async_writefn, s); |
748 | 942ac052 | balrog | s->irq = intr; |
749 | 942ac052 | balrog | s->otg_timer = qemu_new_timer(vm_clock, tusb_otg_tick, s); |
750 | 942ac052 | balrog | s->pwr_timer = qemu_new_timer(vm_clock, tusb_power_tick, s); |
751 | 942ac052 | balrog | s->musb = musb_init(qemu_allocate_irqs(tusb_musb_core_intr, s, |
752 | 942ac052 | balrog | __musb_irq_max)); |
753 | 942ac052 | balrog | |
754 | 942ac052 | balrog | return s;
|
755 | 942ac052 | balrog | } |
756 | 942ac052 | balrog | |
757 | 942ac052 | balrog | void tusb6010_power(struct tusb_s *s, int on) |
758 | 942ac052 | balrog | { |
759 | 942ac052 | balrog | if (!on)
|
760 | 942ac052 | balrog | s->power = 0;
|
761 | 942ac052 | balrog | else if (!s->power && on) { |
762 | 942ac052 | balrog | s->power = 1;
|
763 | 942ac052 | balrog | |
764 | 942ac052 | balrog | /* Pull the interrupt down after TUSB6010 comes up. */
|
765 | 942ac052 | balrog | s->intr_ok = 0;
|
766 | 942ac052 | balrog | tusb_intr_update(s); |
767 | 942ac052 | balrog | qemu_mod_timer(s->pwr_timer, |
768 | 942ac052 | balrog | qemu_get_clock(vm_clock) + ticks_per_sec / 2);
|
769 | 942ac052 | balrog | } |
770 | 942ac052 | balrog | } |