root / hw / pl031.c @ 9c22a623
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/*
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* ARM AMBA PrimeCell PL031 RTC
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*
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* Copyright (c) 2007 CodeSourcery
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*
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* This file is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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*/
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#include "hw.h" |
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#include "primecell.h" |
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#include "qemu-timer.h" |
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#include "sysemu.h" |
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//#define DEBUG_PL031
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#ifdef DEBUG_PL031
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#define DPRINTF(fmt, args...) \
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do { printf("pl031: " fmt , ##args); } while (0) |
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#else
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#define DPRINTF(fmt, args...) do {} while(0) |
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#endif
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#define RTC_DR 0x00 /* Data read register */ |
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#define RTC_MR 0x04 /* Match register */ |
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#define RTC_LR 0x08 /* Data load register */ |
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#define RTC_CR 0x0c /* Control register */ |
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#define RTC_IMSC 0x10 /* Interrupt mask and set register */ |
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#define RTC_RIS 0x14 /* Raw interrupt status register */ |
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#define RTC_MIS 0x18 /* Masked interrupt status register */ |
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#define RTC_ICR 0x1c /* Interrupt clear register */ |
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typedef struct { |
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QEMUTimer *timer; |
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qemu_irq irq; |
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uint32_t tick_offset; |
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uint32_t mr; |
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uint32_t lr; |
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uint32_t cr; |
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uint32_t im; |
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uint32_t is; |
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} pl031_state; |
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static const unsigned char pl031_id[] = { |
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0x31, 0x10, 0x14, 0x00, /* Device ID */ |
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0x0d, 0xf0, 0x05, 0xb1 /* Cell ID */ |
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}; |
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static void pl031_update(pl031_state *s) |
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{ |
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qemu_set_irq(s->irq, s->is & s->im); |
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} |
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static void pl031_interrupt(void * opaque) |
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{ |
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pl031_state *s = (pl031_state *)opaque; |
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s->im = 1;
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DPRINTF("Alarm raised\n");
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pl031_update(s); |
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} |
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static uint32_t pl031_get_count(pl031_state *s)
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{ |
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/* This assumes qemu_get_clock returns the time since the machine was
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created. */
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return s->tick_offset + qemu_get_clock(vm_clock) / ticks_per_sec;
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} |
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static void pl031_set_alarm(pl031_state *s) |
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{ |
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int64_t now; |
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uint32_t ticks; |
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now = qemu_get_clock(vm_clock); |
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ticks = s->tick_offset + now / ticks_per_sec; |
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/* The timer wraps around. This subtraction also wraps in the same way,
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and gives correct results when alarm < now_ticks. */
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ticks = s->mr - ticks; |
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DPRINTF("Alarm set in %ud ticks\n", ticks);
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if (ticks == 0) { |
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qemu_del_timer(s->timer); |
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pl031_interrupt(s); |
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} else {
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qemu_mod_timer(s->timer, now + (int64_t)ticks * ticks_per_sec); |
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} |
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} |
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static uint32_t pl031_read(void *opaque, target_phys_addr_t offset) |
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{ |
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pl031_state *s = (pl031_state *)opaque; |
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if (offset >= 0xfe0 && offset < 0x1000) |
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return pl031_id[(offset - 0xfe0) >> 2]; |
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switch (offset) {
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case RTC_DR:
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return pl031_get_count(s);
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case RTC_MR:
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return s->mr;
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case RTC_IMSC:
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return s->im;
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case RTC_RIS:
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return s->is;
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case RTC_LR:
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return s->lr;
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case RTC_CR:
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/* RTC is permanently enabled. */
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return 1; |
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case RTC_MIS:
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return s->is & s->im;
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case RTC_ICR:
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fprintf(stderr, "qemu: pl031_read: Unexpected offset 0x%x\n",
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(int)offset);
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break;
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default:
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cpu_abort(cpu_single_env, "pl031_read: Bad offset 0x%x\n",
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(int)offset);
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break;
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} |
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return 0; |
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} |
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static void pl031_write(void * opaque, target_phys_addr_t offset, |
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uint32_t value) |
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{ |
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pl031_state *s = (pl031_state *)opaque; |
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switch (offset) {
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case RTC_LR:
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s->tick_offset += value - pl031_get_count(s); |
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pl031_set_alarm(s); |
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break;
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case RTC_MR:
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s->mr = value; |
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pl031_set_alarm(s); |
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break;
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case RTC_IMSC:
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s->im = value & 1;
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DPRINTF("Interrupt mask %d\n", s->im);
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pl031_update(s); |
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break;
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case RTC_ICR:
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/* The PL031 documentation (DDI0224B) states that the interupt is
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cleared when bit 0 of the written value is set. However the
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arm926e documentation (DDI0287B) states that the interrupt is
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cleared when any value is written. */
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DPRINTF("Interrupt cleared");
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s->is = 0;
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pl031_update(s); |
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break;
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case RTC_CR:
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/* Written value is ignored. */
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break;
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case RTC_DR:
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case RTC_MIS:
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case RTC_RIS:
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fprintf(stderr, "qemu: pl031_write: Unexpected offset 0x%x\n",
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(int)offset);
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break;
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default:
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cpu_abort(cpu_single_env, "pl031_write: Bad offset 0x%x\n",
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(int)offset);
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break;
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} |
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} |
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static CPUWriteMemoryFunc * pl031_writefn[] = {
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pl031_write, |
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pl031_write, |
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pl031_write |
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}; |
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static CPUReadMemoryFunc * pl031_readfn[] = {
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pl031_read, |
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pl031_read, |
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pl031_read |
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}; |
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void pl031_init(uint32_t base, qemu_irq irq)
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{ |
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int iomemtype;
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pl031_state *s; |
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struct tm tm;
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s = qemu_mallocz(sizeof(pl031_state));
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iomemtype = cpu_register_io_memory(0, pl031_readfn, pl031_writefn, s);
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if (iomemtype == -1) |
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cpu_abort(cpu_single_env, "pl031_init: Can't register I/O memory\n");
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cpu_register_physical_memory(base, 0x00001000, iomemtype);
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s->irq = irq; |
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/* ??? We assume vm_clock is zero at this point. */
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qemu_get_timedate(&tm, 0);
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s->tick_offset = mktimegm(&tm); |
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s->timer = qemu_new_timer(vm_clock, pl031_interrupt, s); |
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} |