Revision 9c7d4893

b/hw/arm/vexpress.c
156 156
    uint32_t proc_id;
157 157
    uint32_t num_voltage_sensors;
158 158
    const uint32_t *voltages;
159
    uint32_t num_clocks;
160
    const uint32_t *clocks;
159 161
    DBoardInitFn *init;
160 162
};
161 163

  
......
260 262
    3300000, /* VCC3V3 : 3.3V : local board supply for misc external logic */
261 263
};
262 264

  
265
/* Reset values for daughterboard oscillators (in Hz) */
266
static const uint32_t a9_clocks[] = {
267
    45000000, /* AMBA AXI ACLK: 45MHz */
268
    23750000, /* daughterboard CLCD clock: 23.75MHz */
269
    66670000, /* Test chip reference clock: 66.67MHz */
270
};
271

  
263 272
static const VEDBoardInfo a9_daughterboard = {
264 273
    .motherboard_map = motherboard_legacy_map,
265 274
    .loader_start = 0x60000000,
......
267 276
    .proc_id = 0x0c000191,
268 277
    .num_voltage_sensors = ARRAY_SIZE(a9_voltages),
269 278
    .voltages = a9_voltages,
279
    .num_clocks = ARRAY_SIZE(a9_clocks),
280
    .clocks = a9_clocks,
270 281
    .init = a9_daughterboard_init,
271 282
};
272 283

  
......
358 369
    900000, /* Vcore: 0.9V : CPU core voltage */
359 370
};
360 371

  
372
static const uint32_t a15_clocks[] = {
373
    60000000, /* OSCCLK0: 60MHz : CPU_CLK reference */
374
    0, /* OSCCLK1: reserved */
375
    0, /* OSCCLK2: reserved */
376
    0, /* OSCCLK3: reserved */
377
    40000000, /* OSCCLK4: 40MHz : external AXI master clock */
378
    23750000, /* OSCCLK5: 23.75MHz : HDLCD PLL reference */
379
    50000000, /* OSCCLK6: 50MHz : static memory controller clock */
380
    60000000, /* OSCCLK7: 60MHz : SYSCLK reference */
381
    40000000, /* OSCCLK8: 40MHz : DDR2 PLL reference */
382
};
383

  
361 384
static const VEDBoardInfo a15_daughterboard = {
362 385
    .motherboard_map = motherboard_aseries_map,
363 386
    .loader_start = 0x80000000,
......
365 388
    .proc_id = 0x14000237,
366 389
    .num_voltage_sensors = ARRAY_SIZE(a15_voltages),
367 390
    .voltages = a15_voltages,
391
    .num_clocks = ARRAY_SIZE(a15_clocks),
392
    .clocks = a15_clocks,
368 393
    .init = a15_daughterboard_init,
369 394
};
370 395

  
......
400 425
        qdev_prop_set_uint32(sysctl, propname, daughterboard->voltages[i]);
401 426
        g_free(propname);
402 427
    }
428
    qdev_prop_set_uint32(sysctl, "len-db-clock",
429
                         daughterboard->num_clocks);
430
    for (i = 0; i < daughterboard->num_clocks; i++) {
431
        char *propname = g_strdup_printf("db-clock[%d]", i);
432
        qdev_prop_set_uint32(sysctl, propname, daughterboard->clocks[i]);
433
        g_free(propname);
434
    }
403 435
    qdev_init_nofail(sysctl);
404 436
    sysbus_mmio_map(SYS_BUS_DEVICE(sysctl), 0, map[VE_SYSREGS]);
405 437

  

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