Archipelago » qemu

/*

 * QEMU PCI bus manager

 *

 * Copyright (c) 2004 Fabrice Bellard

 *

 * Permission is hereby granted, free of charge, to any person obtaining a copy

 * of this software and associated documentation files (the "Software"), to deal

 * in the Software without restriction, including without limitation the rights

 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell

 * copies of the Software, and to permit persons to whom the Software is

 * furnished to do so, subject to the following conditions:

 *

 * The above copyright notice and this permission notice shall be included in

 * all copies or substantial portions of the Software.

 *

 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL

 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER

 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,

 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN

 * THE SOFTWARE.

 */

#include "hw.h"

#include "pci.h"

#include "pci_host.h"

#include "monitor.h"

#include "net.h"

#include "sysemu.h"

//#define DEBUG_PCI

#ifdef DEBUG_PCI

# define PCI_DPRINTF(format, ...)       printf(format, ## __VA_ARGS__)

#else

# define PCI_DPRINTF(format, ...)       do { } while (0)

#endif

struct PCIBus {

    BusState qbus;

    int devfn_min;

    pci_set_irq_fn set_irq;

    pci_map_irq_fn map_irq;

    pci_hotplug_fn hotplug;

    uint32_t config_reg; /* XXX: suppress */

    void *irq_opaque;

    PCIDevice *devices[256];

    PCIDevice *parent_dev;

    QLIST_HEAD(, PCIBus) child; /* this will be replaced by qdev later */

    QLIST_ENTRY(PCIBus) sibling;/* this will be replaced by qdev later */

    /* The bus IRQ state is the logical OR of the connected devices.

       Keep a count of the number of devices with raised IRQs.  */

    int nirq;

    int *irq_count;

};

static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent);

static struct BusInfo pci_bus_info = {

    .name       = "PCI",

    .size       = sizeof(PCIBus),

    .print_dev  = pcibus_dev_print,

    .props      = (Property[]) {

        DEFINE_PROP_PCI_DEVFN("addr", PCIDevice, devfn, -1),

        DEFINE_PROP_END_OF_LIST()

    }

};

static void pci_update_mappings(PCIDevice *d);

static void pci_set_irq(void *opaque, int irq_num, int level);

target_phys_addr_t pci_mem_base;

static uint16_t pci_default_sub_vendor_id = PCI_SUBVENDOR_ID_REDHAT_QUMRANET;

static uint16_t pci_default_sub_device_id = PCI_SUBDEVICE_ID_QEMU;

struct PCIHostBus {

    int domain;

    struct PCIBus *bus;

    QLIST_ENTRY(PCIHostBus) next;

};

static QLIST_HEAD(, PCIHostBus) host_buses;

static const VMStateDescription vmstate_pcibus = {

    .name = "PCIBUS",

    .version_id = 1,

    .minimum_version_id = 1,

    .minimum_version_id_old = 1,

    .fields      = (VMStateField []) {

        VMSTATE_INT32_EQUAL(nirq, PCIBus),

        VMSTATE_VARRAY_INT32(irq_count, PCIBus, nirq, 0, vmstate_info_int32, int32_t),

        VMSTATE_END_OF_LIST()

    }

};

static int pci_bar(PCIDevice *d, int reg)

{

    uint8_t type;

    if (reg != PCI_ROM_SLOT)

        return PCI_BASE_ADDRESS_0 + reg * 4;

    type = d->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION;

    return type == PCI_HEADER_TYPE_BRIDGE ? PCI_ROM_ADDRESS1 : PCI_ROM_ADDRESS;

}

static void pci_device_reset(PCIDevice *dev)

{

    int r;

    memset(dev->irq_state, 0, sizeof dev->irq_state);

    dev->config[PCI_COMMAND] &= ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY |

                                  PCI_COMMAND_MASTER);

    dev->config[PCI_CACHE_LINE_SIZE] = 0x0;

    dev->config[PCI_INTERRUPT_LINE] = 0x0;

    for (r = 0; r < PCI_NUM_REGIONS; ++r) {

        if (!dev->io_regions[r].size) {

            continue;

        }

        pci_set_long(dev->config + pci_bar(dev, r), dev->io_regions[r].type);

    }

    pci_update_mappings(dev);

}

static void pci_bus_reset(void *opaque)

{

    PCIBus *bus = opaque;

    int i;

    for (i = 0; i < bus->nirq; i++) {

        bus->irq_count[i] = 0;

    }

    for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) {

        if (bus->devices[i]) {

            pci_device_reset(bus->devices[i]);

        }

    }

}

static void pci_host_bus_register(int domain, PCIBus *bus)

{

    struct PCIHostBus *host;

    host = qemu_mallocz(sizeof(*host));

    host->domain = domain;

    host->bus = bus;

    QLIST_INSERT_HEAD(&host_buses, host, next);

}

PCIBus *pci_find_host_bus(int domain)

{

    struct PCIHostBus *host;

    QLIST_FOREACH(host, &host_buses, next) {

        if (host->domain == domain) {

            return host->bus;

        }

    }

    return NULL;

}

void pci_bus_new_inplace(PCIBus *bus, DeviceState *parent,

                         const char *name, int devfn_min)

{

    static int nbus = 0;

    qbus_create_inplace(&bus->qbus, &pci_bus_info, parent, name);

    bus->devfn_min = devfn_min;

    /* host bridge */

    QLIST_INIT(&bus->child);

    pci_host_bus_register(0, bus); /* for now only pci domain 0 is supported */

    vmstate_register(nbus++, &vmstate_pcibus, bus);

    qemu_register_reset(pci_bus_reset, bus);

}

PCIBus *pci_bus_new(DeviceState *parent, const char *name, int devfn_min)

{

    PCIBus *bus;

    bus = qemu_mallocz(sizeof(*bus));

    bus->qbus.qdev_allocated = 1;

    pci_bus_new_inplace(bus, parent, name, devfn_min);

    return bus;

}

void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,

                  void *irq_opaque, int nirq)

{

    bus->set_irq = set_irq;

    bus->map_irq = map_irq;

    bus->irq_opaque = irq_opaque;

    bus->nirq = nirq;

    bus->irq_count = qemu_mallocz(nirq * sizeof(bus->irq_count[0]));

}

void pci_bus_hotplug(PCIBus *bus, pci_hotplug_fn hotplug)

{

    bus->qbus.allow_hotplug = 1;

    bus->hotplug = hotplug;

}

PCIBus *pci_register_bus(DeviceState *parent, const char *name,

                         pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,

                         void *irq_opaque, int devfn_min, int nirq)

{

    PCIBus *bus;

    bus = pci_bus_new(parent, name, devfn_min);

    pci_bus_irqs(bus, set_irq, map_irq, irq_opaque, nirq);

    return bus;

}

static void pci_register_secondary_bus(PCIBus *parent,

                                       PCIBus *bus,

                                       PCIDevice *dev,

                                       pci_map_irq_fn map_irq,

                                       const char *name)

{

    qbus_create_inplace(&bus->qbus, &pci_bus_info, &dev->qdev, name);

    bus->map_irq = map_irq;

    bus->parent_dev = dev;

    QLIST_INIT(&bus->child);

    QLIST_INSERT_HEAD(&parent->child, bus, sibling);

}

static void pci_unregister_secondary_bus(PCIBus *bus)

{

    assert(QLIST_EMPTY(&bus->child));

    QLIST_REMOVE(bus, sibling);

}

int pci_bus_num(PCIBus *s)

{

    if (!s->parent_dev)

        return 0;       /* pci host bridge */

    return s->parent_dev->config[PCI_SECONDARY_BUS];

}

static uint8_t pci_sub_bus(PCIBus *s)

{

    if (!s->parent_dev)

        return 255;     /* pci host bridge */

    return s->parent_dev->config[PCI_SUBORDINATE_BUS];

}

static int get_pci_config_device(QEMUFile *f, void *pv, size_t size)

{

    PCIDevice *s = container_of(pv, PCIDevice, config);

    uint8_t *config;

    int i;

    assert(size == pci_config_size(s));

    config = qemu_malloc(size);

    qemu_get_buffer(f, config, size);

    for (i = 0; i < size; ++i) {

        if ((config[i] ^ s->config[i]) & s->cmask[i] & ~s->wmask[i]) {

            qemu_free(config);

            return -EINVAL;

        }

    }

    memcpy(s->config, config, size);

    pci_update_mappings(s);

    qemu_free(config);

    return 0;

}

/* just put buffer */

static void put_pci_config_device(QEMUFile *f, void *pv, size_t size)

{

    const uint8_t **v = pv;

    assert(size == pci_config_size(container_of(pv, PCIDevice, config)));

    qemu_put_buffer(f, *v, size);

}

static VMStateInfo vmstate_info_pci_config = {

    .name = "pci config",

    .get  = get_pci_config_device,

    .put  = put_pci_config_device,

};

const VMStateDescription vmstate_pci_device = {

    .name = "PCIDevice",

    .version_id = 2,

    .minimum_version_id = 1,

    .minimum_version_id_old = 1,

    .fields      = (VMStateField []) {

        VMSTATE_INT32_LE(version_id, PCIDevice),

        VMSTATE_BUFFER_UNSAFE_INFO(config, PCIDevice, 0,

                                   vmstate_info_pci_config,

                                   PCI_CONFIG_SPACE_SIZE),

        VMSTATE_INT32_ARRAY_V(irq_state, PCIDevice, PCI_NUM_PINS, 2),

        VMSTATE_END_OF_LIST()

    }

};

const VMStateDescription vmstate_pcie_device = {

    .name = "PCIDevice",

    .version_id = 2,

    .minimum_version_id = 1,

    .minimum_version_id_old = 1,

    .fields      = (VMStateField []) {

        VMSTATE_INT32_LE(version_id, PCIDevice),

        VMSTATE_BUFFER_UNSAFE_INFO(config, PCIDevice, 0,

                                   vmstate_info_pci_config,

                                   PCIE_CONFIG_SPACE_SIZE),

        VMSTATE_INT32_ARRAY_V(irq_state, PCIDevice, PCI_NUM_PINS, 2),

        VMSTATE_END_OF_LIST()

    }

};

static inline const VMStateDescription *pci_get_vmstate(PCIDevice *s)

{

    return pci_is_express(s) ? &vmstate_pcie_device : &vmstate_pci_device;

}

void pci_device_save(PCIDevice *s, QEMUFile *f)

{

    vmstate_save_state(f, pci_get_vmstate(s), s);

}

int pci_device_load(PCIDevice *s, QEMUFile *f)

{

    return vmstate_load_state(f, pci_get_vmstate(s), s, s->version_id);

}

static int pci_set_default_subsystem_id(PCIDevice *pci_dev)

{

    uint16_t *id;

    id = (void*)(&pci_dev->config[PCI_SUBVENDOR_ID]);

    id[0] = cpu_to_le16(pci_default_sub_vendor_id);

    id[1] = cpu_to_le16(pci_default_sub_device_id);

    return 0;

}

/*

 * Parse [[<domain>:]<bus>:]<slot>, return -1 on error

 */

static int pci_parse_devaddr(const char *addr, int *domp, int *busp, unsigned *slotp)

{

    const char *p;

    char *e;

    unsigned long val;

    unsigned long dom = 0, bus = 0;

    unsigned slot = 0;

    p = addr;

    val = strtoul(p, &e, 16);

    if (e == p)

        return -1;

    if (*e == ':') {

        bus = val;

        p = e + 1;

        val = strtoul(p, &e, 16);

        if (e == p)

            return -1;

        if (*e == ':') {

            dom = bus;

            bus = val;

            p = e + 1;

            val = strtoul(p, &e, 16);

            if (e == p)

                return -1;

        }

    }

    if (dom > 0xffff || bus > 0xff || val > 0x1f)

        return -1;

    slot = val;

    if (*e)

        return -1;

    /* Note: QEMU doesn't implement domains other than 0 */

    if (!pci_find_bus(pci_find_host_bus(dom), bus))

        return -1;

    *domp = dom;

    *busp = bus;

    *slotp = slot;

    return 0;

}

int pci_read_devaddr(Monitor *mon, const char *addr, int *domp, int *busp,

                     unsigned *slotp)

{

    /* strip legacy tag */

    if (!strncmp(addr, "pci_addr=", 9)) {

        addr += 9;

    }

    if (pci_parse_devaddr(addr, domp, busp, slotp)) {

        monitor_printf(mon, "Invalid pci address\n");

        return -1;

    }

    return 0;

}

PCIBus *pci_get_bus_devfn(int *devfnp, const char *devaddr)

{

    int dom, bus;

    unsigned slot;

    if (!devaddr) {

        *devfnp = -1;

        return pci_find_bus(pci_find_host_bus(0), 0);

    }

    if (pci_parse_devaddr(devaddr, &dom, &bus, &slot) < 0) {

        return NULL;

    }

    *devfnp = slot << 3;

    return pci_find_bus(pci_find_host_bus(0), bus);

}

static void pci_init_cmask(PCIDevice *dev)

{

    pci_set_word(dev->cmask + PCI_VENDOR_ID, 0xffff);

    pci_set_word(dev->cmask + PCI_DEVICE_ID, 0xffff);

    dev->cmask[PCI_STATUS] = PCI_STATUS_CAP_LIST;

    dev->cmask[PCI_REVISION_ID] = 0xff;

    dev->cmask[PCI_CLASS_PROG] = 0xff;

    pci_set_word(dev->cmask + PCI_CLASS_DEVICE, 0xffff);

    dev->cmask[PCI_HEADER_TYPE] = 0xff;

    dev->cmask[PCI_CAPABILITY_LIST] = 0xff;

}

static void pci_init_wmask(PCIDevice *dev)

{

    int i;

    int config_size = pci_config_size(dev);

    dev->wmask[PCI_CACHE_LINE_SIZE] = 0xff;

    dev->wmask[PCI_INTERRUPT_LINE] = 0xff;

    pci_set_word(dev->wmask + PCI_COMMAND,

                 PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);

    for (i = PCI_CONFIG_HEADER_SIZE; i < config_size; ++i)

        dev->wmask[i] = 0xff;

}

static void pci_init_wmask_bridge(PCIDevice *d)

{

    /* PCI_PRIMARY_BUS, PCI_SECONDARY_BUS, PCI_SUBORDINATE_BUS and

       PCI_SEC_LETENCY_TIMER */

    memset(d->wmask + PCI_PRIMARY_BUS, 0xff, 4);

    /* base and limit */

    d->wmask[PCI_IO_BASE] = PCI_IO_RANGE_MASK & 0xff;

    d->wmask[PCI_IO_LIMIT] = PCI_IO_RANGE_MASK & 0xff;

    pci_set_word(d->wmask + PCI_MEMORY_BASE,

                 PCI_MEMORY_RANGE_MASK & 0xffff);

    pci_set_word(d->wmask + PCI_MEMORY_LIMIT,

                 PCI_MEMORY_RANGE_MASK & 0xffff);

    pci_set_word(d->wmask + PCI_PREF_MEMORY_BASE,

                 PCI_PREF_RANGE_MASK & 0xffff);

    pci_set_word(d->wmask + PCI_PREF_MEMORY_LIMIT,

                 PCI_PREF_RANGE_MASK & 0xffff);

    /* PCI_PREF_BASE_UPPER32 and PCI_PREF_LIMIT_UPPER32 */

    memset(d->wmask + PCI_PREF_BASE_UPPER32, 0xff, 8);

    pci_set_word(d->wmask + PCI_BRIDGE_CONTROL, 0xffff);

}

static void pci_config_alloc(PCIDevice *pci_dev)

{

    int config_size = pci_config_size(pci_dev);

    pci_dev->config = qemu_mallocz(config_size);

    pci_dev->cmask = qemu_mallocz(config_size);

    pci_dev->wmask = qemu_mallocz(config_size);

    pci_dev->used = qemu_mallocz(config_size);

}

static void pci_config_free(PCIDevice *pci_dev)

{

    qemu_free(pci_dev->config);

    qemu_free(pci_dev->cmask);

    qemu_free(pci_dev->wmask);

    qemu_free(pci_dev->used);

}

/* -1 for devfn means auto assign */

static PCIDevice *do_pci_register_device(PCIDevice *pci_dev, PCIBus *bus,

                                         const char *name, int devfn,

                                         PCIConfigReadFunc *config_read,

                                         PCIConfigWriteFunc *config_write,

                                         uint8_t header_type)

{

    if (devfn < 0) {

        for(devfn = bus->devfn_min ; devfn < 256; devfn += 8) {

            if (!bus->devices[devfn])

                goto found;

        }

        hw_error("PCI: no devfn available for %s, all in use\n", name);

    found: ;

    } else if (bus->devices[devfn]) {

        hw_error("PCI: devfn %d not available for %s, in use by %s\n", devfn,

                 name, bus->devices[devfn]->name);

    }

    pci_dev->bus = bus;

    pci_dev->devfn = devfn;

    pstrcpy(pci_dev->name, sizeof(pci_dev->name), name);

    memset(pci_dev->irq_state, 0, sizeof(pci_dev->irq_state));

    pci_config_alloc(pci_dev);

    header_type &= ~PCI_HEADER_TYPE_MULTI_FUNCTION;

    if (header_type == PCI_HEADER_TYPE_NORMAL) {

        pci_set_default_subsystem_id(pci_dev);

    }

    pci_init_cmask(pci_dev);

    pci_init_wmask(pci_dev);

    if (header_type == PCI_HEADER_TYPE_BRIDGE) {

        pci_init_wmask_bridge(pci_dev);

    }

    if (!config_read)

        config_read = pci_default_read_config;

    if (!config_write)

        config_write = pci_default_write_config;

    pci_dev->config_read = config_read;

    pci_dev->config_write = config_write;

    bus->devices[devfn] = pci_dev;

    pci_dev->irq = qemu_allocate_irqs(pci_set_irq, pci_dev, PCI_NUM_PINS);

    pci_dev->version_id = 2; /* Current pci device vmstate version */

    return pci_dev;

}

PCIDevice *pci_register_device(PCIBus *bus, const char *name,

                               int instance_size, int devfn,

                               PCIConfigReadFunc *config_read,

                               PCIConfigWriteFunc *config_write)

{

    PCIDevice *pci_dev;

    pci_dev = qemu_mallocz(instance_size);

    pci_dev = do_pci_register_device(pci_dev, bus, name, devfn,

                                     config_read, config_write,

                                     PCI_HEADER_TYPE_NORMAL);

    return pci_dev;

}

static target_phys_addr_t pci_to_cpu_addr(target_phys_addr_t addr)

{

    return addr + pci_mem_base;

}

static void pci_unregister_io_regions(PCIDevice *pci_dev)

{

    PCIIORegion *r;

    int i;

    for(i = 0; i < PCI_NUM_REGIONS; i++) {

        r = &pci_dev->io_regions[i];

        if (!r->size || r->addr == PCI_BAR_UNMAPPED)

            continue;

        if (r->type == PCI_BASE_ADDRESS_SPACE_IO) {

            isa_unassign_ioport(r->addr, r->filtered_size);

        } else {

            cpu_register_physical_memory(pci_to_cpu_addr(r->addr),

                                                     r->filtered_size,

                                                     IO_MEM_UNASSIGNED);

        }

    }

}

static int pci_unregister_device(DeviceState *dev)

{

    PCIDevice *pci_dev = DO_UPCAST(PCIDevice, qdev, dev);

    PCIDeviceInfo *info = DO_UPCAST(PCIDeviceInfo, qdev, dev->info);

    int ret = 0;

    if (info->exit)

        ret = info->exit(pci_dev);

    if (ret)

        return ret;

    pci_unregister_io_regions(pci_dev);

    qemu_free_irqs(pci_dev->irq);

    pci_dev->bus->devices[pci_dev->devfn] = NULL;

    pci_config_free(pci_dev);

    return 0;

}

void pci_register_bar(PCIDevice *pci_dev, int region_num,

                            pcibus_t size, int type,

                            PCIMapIORegionFunc *map_func)

{

    PCIIORegion *r;

    uint32_t addr;

    pcibus_t wmask;

    if ((unsigned int)region_num >= PCI_NUM_REGIONS)

        return;

    if (size & (size-1)) {

        fprintf(stderr, "ERROR: PCI region size must be pow2 "

                    "type=0x%x, size=0x%"FMT_PCIBUS"\n", type, size);

        exit(1);

    }

    r = &pci_dev->io_regions[region_num];

    r->addr = PCI_BAR_UNMAPPED;

    r->size = size;

    r->filtered_size = size;

    r->type = type;

    r->map_func = map_func;

    wmask = ~(size - 1);

    addr = pci_bar(pci_dev, region_num);

    if (region_num == PCI_ROM_SLOT) {

        /* ROM enable bit is writeable */

        wmask |= PCI_ROM_ADDRESS_ENABLE;

    }

    pci_set_long(pci_dev->config + addr, type);

    if (!(r->type & PCI_BASE_ADDRESS_SPACE_IO) &&

        r->type & PCI_BASE_ADDRESS_MEM_TYPE_64) {

        pci_set_quad(pci_dev->wmask + addr, wmask);

        pci_set_quad(pci_dev->cmask + addr, ~0ULL);

    } else {

        pci_set_long(pci_dev->wmask + addr, wmask & 0xffffffff);

        pci_set_long(pci_dev->cmask + addr, 0xffffffff);

    }

}

static uint32_t pci_config_get_io_base(PCIDevice *d,

                                       uint32_t base, uint32_t base_upper16)

{

    uint32_t val;

    val = ((uint32_t)d->config[base] & PCI_IO_RANGE_MASK) << 8;

    if (d->config[base] & PCI_IO_RANGE_TYPE_32) {

        val |= (uint32_t)pci_get_word(d->config + PCI_IO_BASE_UPPER16) << 16;

    }

    return val;

}

static uint64_t pci_config_get_memory_base(PCIDevice *d, uint32_t base)

{

    return ((uint64_t)pci_get_word(d->config + base) & PCI_MEMORY_RANGE_MASK)

        << 16;

}

static uint64_t pci_config_get_pref_base(PCIDevice *d,

                                         uint32_t base, uint32_t upper)

{

    uint64_t val;

    val = ((uint64_t)pci_get_word(d->config + base) &

           PCI_PREF_RANGE_MASK) << 16;

    val |= (uint64_t)pci_get_long(d->config + upper) << 32;

    return val;

}

static pcibus_t pci_bridge_get_base(PCIDevice *bridge, uint8_t type)

{

    pcibus_t base;

    if (type & PCI_BASE_ADDRESS_SPACE_IO) {

        base = pci_config_get_io_base(bridge,

                                      PCI_IO_BASE, PCI_IO_BASE_UPPER16);

    } else {

        if (type & PCI_BASE_ADDRESS_MEM_PREFETCH) {

            base = pci_config_get_pref_base(

                bridge, PCI_PREF_MEMORY_BASE, PCI_PREF_BASE_UPPER32);

        } else {

            base = pci_config_get_memory_base(bridge, PCI_MEMORY_BASE);

        }

    }

    return base;

}

static pcibus_t pci_bridge_get_limit(PCIDevice *bridge, uint8_t type)

{

    pcibus_t limit;

    if (type & PCI_BASE_ADDRESS_SPACE_IO) {

        limit = pci_config_get_io_base(bridge,

                                      PCI_IO_LIMIT, PCI_IO_LIMIT_UPPER16);

        limit |= 0xfff;         /* PCI bridge spec 3.2.5.6. */

    } else {

        if (type & PCI_BASE_ADDRESS_MEM_PREFETCH) {

            limit = pci_config_get_pref_base(

                bridge, PCI_PREF_MEMORY_LIMIT, PCI_PREF_LIMIT_UPPER32);

        } else {

            limit = pci_config_get_memory_base(bridge, PCI_MEMORY_LIMIT);

        }

        limit |= 0xfffff;       /* PCI bridge spec 3.2.5.{1, 8}. */

    }

    return limit;

}

static void pci_bridge_filter(PCIDevice *d, pcibus_t *addr, pcibus_t *size,

                              uint8_t type)

{

    pcibus_t base = *addr;

    pcibus_t limit = *addr + *size - 1;

    PCIDevice *br;

    for (br = d->bus->parent_dev; br; br = br->bus->parent_dev) {

        uint16_t cmd = pci_get_word(d->config + PCI_COMMAND);

        if (type & PCI_BASE_ADDRESS_SPACE_IO) {

            if (!(cmd & PCI_COMMAND_IO)) {

                goto no_map;

            }

        } else {

            if (!(cmd & PCI_COMMAND_MEMORY)) {

                goto no_map;

            }

        }

        base = MAX(base, pci_bridge_get_base(br, type));

        limit = MIN(limit, pci_bridge_get_limit(br, type));

    }

    if (base > limit) {

    no_map:

        *addr = PCI_BAR_UNMAPPED;

        *size = 0;

    } else {

        *addr = base;

        *size = limit - base + 1;

    }

}

static void pci_update_mappings(PCIDevice *d)

{

    PCIIORegion *r;

    int cmd, i;

    pcibus_t last_addr, new_addr;

    pcibus_t filtered_size;

    cmd = pci_get_word(d->config + PCI_COMMAND);

    for(i = 0; i < PCI_NUM_REGIONS; i++) {

        r = &d->io_regions[i];

        /* this region isn't registered */

        if (r->size == 0)

            continue;

        if (r->type & PCI_BASE_ADDRESS_SPACE_IO) {

            if (cmd & PCI_COMMAND_IO) {

                new_addr = pci_get_long(d->config + pci_bar(d, i));

                new_addr = new_addr & ~(r->size - 1);

                last_addr = new_addr + r->size - 1;

                /* NOTE: we have only 64K ioports on PC */

                if (last_addr <= new_addr || new_addr == 0 ||

                    last_addr >= 0x10000) {

                    new_addr = PCI_BAR_UNMAPPED;

                }

            } else {

                new_addr = PCI_BAR_UNMAPPED;

            }

        } else {

            if (cmd & PCI_COMMAND_MEMORY) {

                if (r->type & PCI_BASE_ADDRESS_MEM_TYPE_64) {

                    new_addr = pci_get_quad(d->config + pci_bar(d, i));

                } else {

                    new_addr = pci_get_long(d->config + pci_bar(d, i));

                }

                /* the ROM slot has a specific enable bit */

                if (i == PCI_ROM_SLOT && !(new_addr & PCI_ROM_ADDRESS_ENABLE))

                    goto no_mem_map;

                new_addr = new_addr & ~(r->size - 1);

                last_addr = new_addr + r->size - 1;

                /* NOTE: we do not support wrapping */

                /* XXX: as we cannot support really dynamic

                   mappings, we handle specific values as invalid

                   mappings. */

                if (last_addr <= new_addr || new_addr == 0 ||

                    last_addr == PCI_BAR_UNMAPPED ||

                    /* Now pcibus_t is 64bit.

                     * Check if 32 bit BAR wrap around explicitly.

                     * Without this, PC ide doesn't work well.

                     * TODO: remove this work around.

                     */

                    (!(r->type & PCI_BASE_ADDRESS_MEM_TYPE_64) &&

                     last_addr >= UINT32_MAX) ||

                    /*

                     * OS is allowed to set BAR beyond its addressable

                     * bits. For example, 32 bit OS can set 64bit bar

                     * to >4G. Check it.

                     */

                    last_addr >= TARGET_PHYS_ADDR_MAX) {

                    new_addr = PCI_BAR_UNMAPPED;

                }

            } else {

            no_mem_map:

                new_addr = PCI_BAR_UNMAPPED;

            }

        }

        /* bridge filtering */

        filtered_size = r->size;

        if (new_addr != PCI_BAR_UNMAPPED) {

            pci_bridge_filter(d, &new_addr, &filtered_size, r->type);

        }

        /* This bar isn't changed */

        if (new_addr == r->addr && filtered_size == r->filtered_size)

            continue;

        /* now do the real mapping */

        if (r->addr != PCI_BAR_UNMAPPED) {

            if (r->type & PCI_BASE_ADDRESS_SPACE_IO) {

                int class;

                /* NOTE: specific hack for IDE in PC case:

                   only one byte must be mapped. */

                class = pci_get_word(d->config + PCI_CLASS_DEVICE);

                if (class == 0x0101 && r->size == 4) {

                    isa_unassign_ioport(r->addr + 2, 1);

                } else {

                    isa_unassign_ioport(r->addr, r->filtered_size);

                }

            } else {

                cpu_register_physical_memory(pci_to_cpu_addr(r->addr),

                                             r->filtered_size,

                                             IO_MEM_UNASSIGNED);

                qemu_unregister_coalesced_mmio(r->addr, r->filtered_size);

            }

        }

        r->addr = new_addr;

        r->filtered_size = filtered_size;

        if (r->addr != PCI_BAR_UNMAPPED) {

            /*

             * TODO: currently almost all the map funcions assumes

             * filtered_size == size and addr & ~(size - 1) == addr.

             * However with bridge filtering, they aren't always true.

             * Teach them such cases, such that filtered_size < size and

             * addr & (size - 1) != 0.

             */

            r->map_func(d, i, r->addr, r->filtered_size, r->type);

        }

    }

}

uint32_t pci_default_read_config(PCIDevice *d,

                                 uint32_t address, int len)

{

    uint32_t val = 0;

    assert(len == 1 || len == 2 || len == 4);

    len = MIN(len, pci_config_size(d) - address);

    memcpy(&val, d->config + address, len);

    return le32_to_cpu(val);

}

void pci_default_write_config(PCIDevice *d, uint32_t addr, uint32_t val, int l)

{

    int i;

    uint32_t config_size = pci_config_size(d);

    for (i = 0; i < l && addr + i < config_size; val >>= 8, ++i) {

        uint8_t wmask = d->wmask[addr + i];

        d->config[addr + i] = (d->config[addr + i] & ~wmask) | (val & wmask);

    }

    if (ranges_overlap(addr, l, PCI_BASE_ADDRESS_0, 24) ||

        ranges_overlap(addr, l, PCI_ROM_ADDRESS, 4) ||

        ranges_overlap(addr, l, PCI_ROM_ADDRESS1, 4) ||

        range_covers_byte(addr, l, PCI_COMMAND))

        pci_update_mappings(d);

}

/***********************************************************/

/* generic PCI irq support */

/* 0 <= irq_num <= 3. level must be 0 or 1 */

static void pci_set_irq(void *opaque, int irq_num, int level)

{

    PCIDevice *pci_dev = opaque;

    PCIBus *bus;

    int change;

    change = level - pci_dev->irq_state[irq_num];

    if (!change)

        return;

    pci_dev->irq_state[irq_num] = level;

    for (;;) {

        bus = pci_dev->bus;

        irq_num = bus->map_irq(pci_dev, irq_num);

        if (bus->set_irq)

            break;

        pci_dev = bus->parent_dev;

    }

    bus->irq_count[irq_num] += change;

    bus->set_irq(bus->irq_opaque, irq_num, bus->irq_count[irq_num] != 0);

}

/***********************************************************/

/* monitor info on PCI */

typedef struct {

    uint16_t class;

    const char *desc;

} pci_class_desc;

static const pci_class_desc pci_class_descriptions[] =

{

    { 0x0100, "SCSI controller"},

    { 0x0101, "IDE controller"},

    { 0x0102, "Floppy controller"},

    { 0x0103, "IPI controller"},

    { 0x0104, "RAID controller"},