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1 | b92e5a22 | bellard | /*
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2 | b92e5a22 | bellard | * Software MMU support
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3 | 5fafdf24 | ths | *
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4 | b92e5a22 | bellard | * Copyright (c) 2003 Fabrice Bellard
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5 | b92e5a22 | bellard | *
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6 | b92e5a22 | bellard | * This library is free software; you can redistribute it and/or
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7 | b92e5a22 | bellard | * modify it under the terms of the GNU Lesser General Public
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8 | b92e5a22 | bellard | * License as published by the Free Software Foundation; either
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9 | b92e5a22 | bellard | * version 2 of the License, or (at your option) any later version.
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10 | b92e5a22 | bellard | *
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11 | b92e5a22 | bellard | * This library is distributed in the hope that it will be useful,
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12 | b92e5a22 | bellard | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 | b92e5a22 | bellard | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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14 | b92e5a22 | bellard | * Lesser General Public License for more details.
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15 | b92e5a22 | bellard | *
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16 | b92e5a22 | bellard | * You should have received a copy of the GNU Lesser General Public
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17 | 8167ee88 | Blue Swirl | * License along with this library; if not, see <http://www.gnu.org/licenses/>.
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18 | b92e5a22 | bellard | */
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19 | b92e5a22 | bellard | #define DATA_SIZE (1 << SHIFT) |
20 | b92e5a22 | bellard | |
21 | b92e5a22 | bellard | #if DATA_SIZE == 8 |
22 | b92e5a22 | bellard | #define SUFFIX q
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23 | 61382a50 | bellard | #define USUFFIX q
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24 | b92e5a22 | bellard | #define DATA_TYPE uint64_t
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25 | b92e5a22 | bellard | #elif DATA_SIZE == 4 |
26 | b92e5a22 | bellard | #define SUFFIX l
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27 | 61382a50 | bellard | #define USUFFIX l
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28 | b92e5a22 | bellard | #define DATA_TYPE uint32_t
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29 | b92e5a22 | bellard | #elif DATA_SIZE == 2 |
30 | b92e5a22 | bellard | #define SUFFIX w
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31 | 61382a50 | bellard | #define USUFFIX uw
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32 | b92e5a22 | bellard | #define DATA_TYPE uint16_t
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33 | b92e5a22 | bellard | #elif DATA_SIZE == 1 |
34 | b92e5a22 | bellard | #define SUFFIX b
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35 | 61382a50 | bellard | #define USUFFIX ub
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36 | b92e5a22 | bellard | #define DATA_TYPE uint8_t
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37 | b92e5a22 | bellard | #else
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38 | b92e5a22 | bellard | #error unsupported data size
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39 | b92e5a22 | bellard | #endif
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40 | b92e5a22 | bellard | |
41 | b769d8fe | bellard | #ifdef SOFTMMU_CODE_ACCESS
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42 | b769d8fe | bellard | #define READ_ACCESS_TYPE 2 |
43 | 84b7b8e7 | bellard | #define ADDR_READ addr_code
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44 | b769d8fe | bellard | #else
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45 | b769d8fe | bellard | #define READ_ACCESS_TYPE 0 |
46 | 84b7b8e7 | bellard | #define ADDR_READ addr_read
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47 | b769d8fe | bellard | #endif
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48 | b769d8fe | bellard | |
49 | 5fafdf24 | ths | static DATA_TYPE glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(target_ulong addr,
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50 | 6ebbf390 | j_mayer | int mmu_idx,
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51 | 61382a50 | bellard | void *retaddr);
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52 | c227f099 | Anthony Liguori | static inline DATA_TYPE glue(io_read, SUFFIX)(target_phys_addr_t physaddr, |
53 | 2e70f6ef | pbrook | target_ulong addr, |
54 | 2e70f6ef | pbrook | void *retaddr)
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55 | b92e5a22 | bellard | { |
56 | b92e5a22 | bellard | DATA_TYPE res; |
57 | b92e5a22 | bellard | int index;
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58 | 0f459d16 | pbrook | index = (physaddr >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1);
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59 | 0f459d16 | pbrook | physaddr = (physaddr & TARGET_PAGE_MASK) + addr; |
60 | 2e70f6ef | pbrook | env->mem_io_pc = (unsigned long)retaddr; |
61 | 2e70f6ef | pbrook | if (index > (IO_MEM_NOTDIRTY >> IO_MEM_SHIFT)
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62 | 2e70f6ef | pbrook | && !can_do_io(env)) { |
63 | 2e70f6ef | pbrook | cpu_io_recompile(env, retaddr); |
64 | 2e70f6ef | pbrook | } |
65 | b92e5a22 | bellard | |
66 | db8886d3 | aliguori | env->mem_io_vaddr = addr; |
67 | b92e5a22 | bellard | #if SHIFT <= 2 |
68 | a4193c8a | bellard | res = io_mem_read[index][SHIFT](io_mem_opaque[index], physaddr); |
69 | b92e5a22 | bellard | #else
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70 | b92e5a22 | bellard | #ifdef TARGET_WORDS_BIGENDIAN
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71 | a4193c8a | bellard | res = (uint64_t)io_mem_read[index][2](io_mem_opaque[index], physaddr) << 32; |
72 | a4193c8a | bellard | res |= io_mem_read[index][2](io_mem_opaque[index], physaddr + 4); |
73 | b92e5a22 | bellard | #else
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74 | a4193c8a | bellard | res = io_mem_read[index][2](io_mem_opaque[index], physaddr);
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75 | a4193c8a | bellard | res |= (uint64_t)io_mem_read[index][2](io_mem_opaque[index], physaddr + 4) << 32; |
76 | b92e5a22 | bellard | #endif
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77 | b92e5a22 | bellard | #endif /* SHIFT > 2 */ |
78 | b92e5a22 | bellard | return res;
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79 | b92e5a22 | bellard | } |
80 | b92e5a22 | bellard | |
81 | b92e5a22 | bellard | /* handle all cases except unaligned access which span two pages */
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82 | d656469f | bellard | DATA_TYPE REGPARM glue(glue(__ld, SUFFIX), MMUSUFFIX)(target_ulong addr, |
83 | d656469f | bellard | int mmu_idx)
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84 | b92e5a22 | bellard | { |
85 | b92e5a22 | bellard | DATA_TYPE res; |
86 | 61382a50 | bellard | int index;
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87 | c27004ec | bellard | target_ulong tlb_addr; |
88 | c227f099 | Anthony Liguori | target_phys_addr_t addend; |
89 | b92e5a22 | bellard | void *retaddr;
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90 | 3b46e624 | ths | |
91 | b92e5a22 | bellard | /* test if there is match for unaligned or IO access */
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92 | b92e5a22 | bellard | /* XXX: could done more in memory macro in a non portable way */
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93 | b92e5a22 | bellard | index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
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94 | b92e5a22 | bellard | redo:
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95 | 6ebbf390 | j_mayer | tlb_addr = env->tlb_table[mmu_idx][index].ADDR_READ; |
96 | b92e5a22 | bellard | if ((addr & TARGET_PAGE_MASK) == (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
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97 | b92e5a22 | bellard | if (tlb_addr & ~TARGET_PAGE_MASK) {
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98 | b92e5a22 | bellard | /* IO access */
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99 | b92e5a22 | bellard | if ((addr & (DATA_SIZE - 1)) != 0) |
100 | b92e5a22 | bellard | goto do_unaligned_access;
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101 | 2e70f6ef | pbrook | retaddr = GETPC(); |
102 | 0f459d16 | pbrook | addend = env->iotlb[mmu_idx][index]; |
103 | 2e70f6ef | pbrook | res = glue(io_read, SUFFIX)(addend, addr, retaddr); |
104 | 98699967 | bellard | } else if (((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1) >= TARGET_PAGE_SIZE) { |
105 | b92e5a22 | bellard | /* slow unaligned access (it spans two pages or IO) */
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106 | b92e5a22 | bellard | do_unaligned_access:
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107 | 61382a50 | bellard | retaddr = GETPC(); |
108 | a64d4718 | bellard | #ifdef ALIGNED_ONLY
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109 | 6ebbf390 | j_mayer | do_unaligned_access(addr, READ_ACCESS_TYPE, mmu_idx, retaddr); |
110 | a64d4718 | bellard | #endif
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111 | 5fafdf24 | ths | res = glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(addr, |
112 | 6ebbf390 | j_mayer | mmu_idx, retaddr); |
113 | b92e5a22 | bellard | } else {
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114 | a64d4718 | bellard | /* unaligned/aligned access in the same page */
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115 | a64d4718 | bellard | #ifdef ALIGNED_ONLY
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116 | a64d4718 | bellard | if ((addr & (DATA_SIZE - 1)) != 0) { |
117 | a64d4718 | bellard | retaddr = GETPC(); |
118 | 6ebbf390 | j_mayer | do_unaligned_access(addr, READ_ACCESS_TYPE, mmu_idx, retaddr); |
119 | a64d4718 | bellard | } |
120 | a64d4718 | bellard | #endif
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121 | 0f459d16 | pbrook | addend = env->tlb_table[mmu_idx][index].addend; |
122 | 0f459d16 | pbrook | res = glue(glue(ld, USUFFIX), _raw)((uint8_t *)(long)(addr+addend));
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123 | b92e5a22 | bellard | } |
124 | b92e5a22 | bellard | } else {
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125 | b92e5a22 | bellard | /* the page is not in the TLB : fill it */
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126 | 61382a50 | bellard | retaddr = GETPC(); |
127 | a64d4718 | bellard | #ifdef ALIGNED_ONLY
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128 | a64d4718 | bellard | if ((addr & (DATA_SIZE - 1)) != 0) |
129 | 6ebbf390 | j_mayer | do_unaligned_access(addr, READ_ACCESS_TYPE, mmu_idx, retaddr); |
130 | a64d4718 | bellard | #endif
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131 | 6ebbf390 | j_mayer | tlb_fill(addr, READ_ACCESS_TYPE, mmu_idx, retaddr); |
132 | b92e5a22 | bellard | goto redo;
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133 | b92e5a22 | bellard | } |
134 | b92e5a22 | bellard | return res;
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135 | b92e5a22 | bellard | } |
136 | b92e5a22 | bellard | |
137 | b92e5a22 | bellard | /* handle all unaligned cases */
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138 | 5fafdf24 | ths | static DATA_TYPE glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(target_ulong addr,
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139 | 6ebbf390 | j_mayer | int mmu_idx,
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140 | 61382a50 | bellard | void *retaddr)
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141 | b92e5a22 | bellard | { |
142 | b92e5a22 | bellard | DATA_TYPE res, res1, res2; |
143 | 61382a50 | bellard | int index, shift;
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144 | c227f099 | Anthony Liguori | target_phys_addr_t addend; |
145 | c27004ec | bellard | target_ulong tlb_addr, addr1, addr2; |
146 | b92e5a22 | bellard | |
147 | b92e5a22 | bellard | index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
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148 | b92e5a22 | bellard | redo:
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149 | 6ebbf390 | j_mayer | tlb_addr = env->tlb_table[mmu_idx][index].ADDR_READ; |
150 | b92e5a22 | bellard | if ((addr & TARGET_PAGE_MASK) == (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
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151 | b92e5a22 | bellard | if (tlb_addr & ~TARGET_PAGE_MASK) {
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152 | b92e5a22 | bellard | /* IO access */
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153 | b92e5a22 | bellard | if ((addr & (DATA_SIZE - 1)) != 0) |
154 | b92e5a22 | bellard | goto do_unaligned_access;
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155 | 2e70f6ef | pbrook | retaddr = GETPC(); |
156 | 0f459d16 | pbrook | addend = env->iotlb[mmu_idx][index]; |
157 | 2e70f6ef | pbrook | res = glue(io_read, SUFFIX)(addend, addr, retaddr); |
158 | 98699967 | bellard | } else if (((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1) >= TARGET_PAGE_SIZE) { |
159 | b92e5a22 | bellard | do_unaligned_access:
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160 | b92e5a22 | bellard | /* slow unaligned access (it spans two pages) */
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161 | b92e5a22 | bellard | addr1 = addr & ~(DATA_SIZE - 1);
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162 | b92e5a22 | bellard | addr2 = addr1 + DATA_SIZE; |
163 | 5fafdf24 | ths | res1 = glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(addr1, |
164 | 6ebbf390 | j_mayer | mmu_idx, retaddr); |
165 | 5fafdf24 | ths | res2 = glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(addr2, |
166 | 6ebbf390 | j_mayer | mmu_idx, retaddr); |
167 | b92e5a22 | bellard | shift = (addr & (DATA_SIZE - 1)) * 8; |
168 | b92e5a22 | bellard | #ifdef TARGET_WORDS_BIGENDIAN
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169 | b92e5a22 | bellard | res = (res1 << shift) | (res2 >> ((DATA_SIZE * 8) - shift));
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170 | b92e5a22 | bellard | #else
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171 | b92e5a22 | bellard | res = (res1 >> shift) | (res2 << ((DATA_SIZE * 8) - shift));
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172 | b92e5a22 | bellard | #endif
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173 | 6986f88c | bellard | res = (DATA_TYPE)res; |
174 | b92e5a22 | bellard | } else {
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175 | b92e5a22 | bellard | /* unaligned/aligned access in the same page */
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176 | 0f459d16 | pbrook | addend = env->tlb_table[mmu_idx][index].addend; |
177 | 0f459d16 | pbrook | res = glue(glue(ld, USUFFIX), _raw)((uint8_t *)(long)(addr+addend));
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178 | b92e5a22 | bellard | } |
179 | b92e5a22 | bellard | } else {
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180 | b92e5a22 | bellard | /* the page is not in the TLB : fill it */
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181 | 6ebbf390 | j_mayer | tlb_fill(addr, READ_ACCESS_TYPE, mmu_idx, retaddr); |
182 | b92e5a22 | bellard | goto redo;
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183 | b92e5a22 | bellard | } |
184 | b92e5a22 | bellard | return res;
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185 | b92e5a22 | bellard | } |
186 | b92e5a22 | bellard | |
187 | b769d8fe | bellard | #ifndef SOFTMMU_CODE_ACCESS
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188 | b769d8fe | bellard | |
189 | 5fafdf24 | ths | static void glue(glue(slow_st, SUFFIX), MMUSUFFIX)(target_ulong addr, |
190 | 5fafdf24 | ths | DATA_TYPE val, |
191 | 6ebbf390 | j_mayer | int mmu_idx,
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192 | b769d8fe | bellard | void *retaddr);
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193 | b769d8fe | bellard | |
194 | c227f099 | Anthony Liguori | static inline void glue(io_write, SUFFIX)(target_phys_addr_t physaddr, |
195 | b769d8fe | bellard | DATA_TYPE val, |
196 | 0f459d16 | pbrook | target_ulong addr, |
197 | b769d8fe | bellard | void *retaddr)
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198 | b769d8fe | bellard | { |
199 | b769d8fe | bellard | int index;
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200 | 0f459d16 | pbrook | index = (physaddr >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1);
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201 | 0f459d16 | pbrook | physaddr = (physaddr & TARGET_PAGE_MASK) + addr; |
202 | 2e70f6ef | pbrook | if (index > (IO_MEM_NOTDIRTY >> IO_MEM_SHIFT)
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203 | 2e70f6ef | pbrook | && !can_do_io(env)) { |
204 | 2e70f6ef | pbrook | cpu_io_recompile(env, retaddr); |
205 | 2e70f6ef | pbrook | } |
206 | b769d8fe | bellard | |
207 | 2e70f6ef | pbrook | env->mem_io_vaddr = addr; |
208 | 2e70f6ef | pbrook | env->mem_io_pc = (unsigned long)retaddr; |
209 | b769d8fe | bellard | #if SHIFT <= 2 |
210 | b769d8fe | bellard | io_mem_write[index][SHIFT](io_mem_opaque[index], physaddr, val); |
211 | b769d8fe | bellard | #else
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212 | b769d8fe | bellard | #ifdef TARGET_WORDS_BIGENDIAN
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213 | b769d8fe | bellard | io_mem_write[index][2](io_mem_opaque[index], physaddr, val >> 32); |
214 | b769d8fe | bellard | io_mem_write[index][2](io_mem_opaque[index], physaddr + 4, val); |
215 | b769d8fe | bellard | #else
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216 | b769d8fe | bellard | io_mem_write[index][2](io_mem_opaque[index], physaddr, val);
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217 | b769d8fe | bellard | io_mem_write[index][2](io_mem_opaque[index], physaddr + 4, val >> 32); |
218 | b769d8fe | bellard | #endif
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219 | b769d8fe | bellard | #endif /* SHIFT > 2 */ |
220 | b769d8fe | bellard | } |
221 | b92e5a22 | bellard | |
222 | d656469f | bellard | void REGPARM glue(glue(__st, SUFFIX), MMUSUFFIX)(target_ulong addr,
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223 | d656469f | bellard | DATA_TYPE val, |
224 | d656469f | bellard | int mmu_idx)
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225 | b92e5a22 | bellard | { |
226 | c227f099 | Anthony Liguori | target_phys_addr_t addend; |
227 | c27004ec | bellard | target_ulong tlb_addr; |
228 | b92e5a22 | bellard | void *retaddr;
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229 | 61382a50 | bellard | int index;
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230 | 3b46e624 | ths | |
231 | b92e5a22 | bellard | index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
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232 | b92e5a22 | bellard | redo:
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233 | 6ebbf390 | j_mayer | tlb_addr = env->tlb_table[mmu_idx][index].addr_write; |
234 | b92e5a22 | bellard | if ((addr & TARGET_PAGE_MASK) == (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
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235 | b92e5a22 | bellard | if (tlb_addr & ~TARGET_PAGE_MASK) {
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236 | b92e5a22 | bellard | /* IO access */
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237 | b92e5a22 | bellard | if ((addr & (DATA_SIZE - 1)) != 0) |
238 | b92e5a22 | bellard | goto do_unaligned_access;
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239 | d720b93d | bellard | retaddr = GETPC(); |
240 | 0f459d16 | pbrook | addend = env->iotlb[mmu_idx][index]; |
241 | 0f459d16 | pbrook | glue(io_write, SUFFIX)(addend, val, addr, retaddr); |
242 | 98699967 | bellard | } else if (((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1) >= TARGET_PAGE_SIZE) { |
243 | b92e5a22 | bellard | do_unaligned_access:
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244 | 61382a50 | bellard | retaddr = GETPC(); |
245 | a64d4718 | bellard | #ifdef ALIGNED_ONLY
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246 | 6ebbf390 | j_mayer | do_unaligned_access(addr, 1, mmu_idx, retaddr);
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247 | a64d4718 | bellard | #endif
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248 | 5fafdf24 | ths | glue(glue(slow_st, SUFFIX), MMUSUFFIX)(addr, val, |
249 | 6ebbf390 | j_mayer | mmu_idx, retaddr); |
250 | b92e5a22 | bellard | } else {
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251 | b92e5a22 | bellard | /* aligned/unaligned access in the same page */
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252 | a64d4718 | bellard | #ifdef ALIGNED_ONLY
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253 | a64d4718 | bellard | if ((addr & (DATA_SIZE - 1)) != 0) { |
254 | a64d4718 | bellard | retaddr = GETPC(); |
255 | 6ebbf390 | j_mayer | do_unaligned_access(addr, 1, mmu_idx, retaddr);
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256 | a64d4718 | bellard | } |
257 | a64d4718 | bellard | #endif
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258 | 0f459d16 | pbrook | addend = env->tlb_table[mmu_idx][index].addend; |
259 | 0f459d16 | pbrook | glue(glue(st, SUFFIX), _raw)((uint8_t *)(long)(addr+addend), val);
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260 | b92e5a22 | bellard | } |
261 | b92e5a22 | bellard | } else {
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262 | b92e5a22 | bellard | /* the page is not in the TLB : fill it */
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263 | 61382a50 | bellard | retaddr = GETPC(); |
264 | a64d4718 | bellard | #ifdef ALIGNED_ONLY
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265 | a64d4718 | bellard | if ((addr & (DATA_SIZE - 1)) != 0) |
266 | 6ebbf390 | j_mayer | do_unaligned_access(addr, 1, mmu_idx, retaddr);
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267 | a64d4718 | bellard | #endif
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268 | 6ebbf390 | j_mayer | tlb_fill(addr, 1, mmu_idx, retaddr);
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269 | b92e5a22 | bellard | goto redo;
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270 | b92e5a22 | bellard | } |
271 | b92e5a22 | bellard | } |
272 | b92e5a22 | bellard | |
273 | b92e5a22 | bellard | /* handles all unaligned cases */
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274 | 5fafdf24 | ths | static void glue(glue(slow_st, SUFFIX), MMUSUFFIX)(target_ulong addr, |
275 | 61382a50 | bellard | DATA_TYPE val, |
276 | 6ebbf390 | j_mayer | int mmu_idx,
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277 | 61382a50 | bellard | void *retaddr)
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278 | b92e5a22 | bellard | { |
279 | c227f099 | Anthony Liguori | target_phys_addr_t addend; |
280 | c27004ec | bellard | target_ulong tlb_addr; |
281 | 61382a50 | bellard | int index, i;
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282 | b92e5a22 | bellard | |
283 | b92e5a22 | bellard | index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
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284 | b92e5a22 | bellard | redo:
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285 | 6ebbf390 | j_mayer | tlb_addr = env->tlb_table[mmu_idx][index].addr_write; |
286 | b92e5a22 | bellard | if ((addr & TARGET_PAGE_MASK) == (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
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287 | b92e5a22 | bellard | if (tlb_addr & ~TARGET_PAGE_MASK) {
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288 | b92e5a22 | bellard | /* IO access */
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289 | b92e5a22 | bellard | if ((addr & (DATA_SIZE - 1)) != 0) |
290 | b92e5a22 | bellard | goto do_unaligned_access;
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291 | 0f459d16 | pbrook | addend = env->iotlb[mmu_idx][index]; |
292 | 0f459d16 | pbrook | glue(io_write, SUFFIX)(addend, val, addr, retaddr); |
293 | 98699967 | bellard | } else if (((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1) >= TARGET_PAGE_SIZE) { |
294 | b92e5a22 | bellard | do_unaligned_access:
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295 | b92e5a22 | bellard | /* XXX: not efficient, but simple */
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296 | 6c41b272 | balrog | /* Note: relies on the fact that tlb_fill() does not remove the
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297 | 6c41b272 | balrog | * previous page from the TLB cache. */
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298 | 7221fa98 | balrog | for(i = DATA_SIZE - 1; i >= 0; i--) { |
299 | b92e5a22 | bellard | #ifdef TARGET_WORDS_BIGENDIAN
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300 | 5fafdf24 | ths | glue(slow_stb, MMUSUFFIX)(addr + i, val >> (((DATA_SIZE - 1) * 8) - (i * 8)), |
301 | 6ebbf390 | j_mayer | mmu_idx, retaddr); |
302 | b92e5a22 | bellard | #else
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303 | 5fafdf24 | ths | glue(slow_stb, MMUSUFFIX)(addr + i, val >> (i * 8),
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304 | 6ebbf390 | j_mayer | mmu_idx, retaddr); |
305 | b92e5a22 | bellard | #endif
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306 | b92e5a22 | bellard | } |
307 | b92e5a22 | bellard | } else {
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308 | b92e5a22 | bellard | /* aligned/unaligned access in the same page */
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309 | 0f459d16 | pbrook | addend = env->tlb_table[mmu_idx][index].addend; |
310 | 0f459d16 | pbrook | glue(glue(st, SUFFIX), _raw)((uint8_t *)(long)(addr+addend), val);
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311 | b92e5a22 | bellard | } |
312 | b92e5a22 | bellard | } else {
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313 | b92e5a22 | bellard | /* the page is not in the TLB : fill it */
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314 | 6ebbf390 | j_mayer | tlb_fill(addr, 1, mmu_idx, retaddr);
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315 | b92e5a22 | bellard | goto redo;
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316 | b92e5a22 | bellard | } |
317 | b92e5a22 | bellard | } |
318 | b92e5a22 | bellard | |
319 | b769d8fe | bellard | #endif /* !defined(SOFTMMU_CODE_ACCESS) */ |
320 | b769d8fe | bellard | |
321 | b769d8fe | bellard | #undef READ_ACCESS_TYPE
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322 | b92e5a22 | bellard | #undef SHIFT
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323 | b92e5a22 | bellard | #undef DATA_TYPE
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324 | b92e5a22 | bellard | #undef SUFFIX
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325 | 61382a50 | bellard | #undef USUFFIX
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326 | b92e5a22 | bellard | #undef DATA_SIZE
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327 | 84b7b8e7 | bellard | #undef ADDR_READ |