root / target-cris / helper.c @ 9d29cdea
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/*
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* CRIS helper routines.
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*
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* Copyright (c) 2007 AXIS Communications AB
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* Written by Edgar E. Iglesias.
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include <stdio.h> |
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#include <string.h> |
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#include "config.h" |
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#include "cpu.h" |
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#include "mmu.h" |
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#include "exec-all.h" |
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#include "host-utils.h" |
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//#define CRIS_HELPER_DEBUG
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#ifdef CRIS_HELPER_DEBUG
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#define D(x) x
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#define D_LOG(...) qemu_log(__VA__ARGS__)
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#else
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#define D(x)
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#define D_LOG(...) do { } while (0) |
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#endif
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#if defined(CONFIG_USER_ONLY)
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void do_interrupt (CPUState *env)
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{ |
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env->exception_index = -1;
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env->pregs[PR_ERP] = env->pc; |
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} |
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int cpu_cris_handle_mmu_fault(CPUState * env, target_ulong address, int rw, |
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int mmu_idx, int is_softmmu) |
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{ |
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env->exception_index = 0xaa;
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env->pregs[PR_EDA] = address; |
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cpu_dump_state(env, stderr, fprintf, 0);
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return 1; |
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} |
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target_phys_addr_t cpu_get_phys_page_debug(CPUState * env, target_ulong addr) |
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{ |
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return addr;
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} |
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#else /* !CONFIG_USER_ONLY */ |
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static void cris_shift_ccs(CPUState *env) |
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{ |
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uint32_t ccs; |
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/* Apply the ccs shift. */
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ccs = env->pregs[PR_CCS]; |
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ccs = ((ccs & 0xc0000000) | ((ccs << 12) >> 2)) & ~0x3ff; |
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env->pregs[PR_CCS] = ccs; |
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} |
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int cpu_cris_handle_mmu_fault (CPUState *env, target_ulong address, int rw, |
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int mmu_idx, int is_softmmu) |
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{ |
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struct cris_mmu_result res;
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int prot, miss;
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int r = -1; |
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target_ulong phy; |
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D(printf ("%s addr=%x pc=%x rw=%x\n", __func__, address, env->pc, rw));
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miss = cris_mmu_translate(&res, env, address & TARGET_PAGE_MASK, |
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rw, mmu_idx); |
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if (miss)
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{ |
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if (env->exception_index == EXCP_BUSFAULT)
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cpu_abort(env, |
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"CRIS: Illegal recursive bus fault."
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"addr=%x rw=%d\n",
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address, rw); |
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env->pregs[PR_EDA] = address; |
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env->exception_index = EXCP_BUSFAULT; |
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env->fault_vector = res.bf_vec; |
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r = 1;
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} |
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else
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{ |
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/*
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* Mask off the cache selection bit. The ETRAX busses do not
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* see the top bit.
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*/
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phy = res.phy & ~0x80000000;
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prot = res.prot; |
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r = tlb_set_page(env, address & TARGET_PAGE_MASK, |
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phy, prot, mmu_idx, is_softmmu); |
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} |
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if (r > 0) |
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D_LOG("%s returns %d irqreq=%x addr=%x"
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" phy=%x ismmu=%d vec=%x pc=%x\n",
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__func__, r, env->interrupt_request, |
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address, res.phy, is_softmmu, res.bf_vec, env->pc); |
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return r;
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} |
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void do_interrupt(CPUState *env)
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{ |
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int ex_vec = -1; |
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D_LOG( "exception index=%d interrupt_req=%d\n",
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env->exception_index, |
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env->interrupt_request); |
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switch (env->exception_index)
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{ |
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case EXCP_BREAK:
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/* These exceptions are genereated by the core itself.
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ERP should point to the insn following the brk. */
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ex_vec = env->trap_vector; |
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env->pregs[PR_ERP] = env->pc; |
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break;
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case EXCP_NMI:
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/* NMI is hardwired to vector zero. */
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ex_vec = 0;
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env->pregs[PR_CCS] &= ~M_FLAG; |
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env->pregs[PR_NRP] = env->pc; |
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break;
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case EXCP_BUSFAULT:
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ex_vec = env->fault_vector; |
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env->pregs[PR_ERP] = env->pc; |
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break;
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default:
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/* The interrupt controller gives us the vector. */
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ex_vec = env->interrupt_vector; |
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/* Normal interrupts are taken between
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TB's. env->pc is valid here. */
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env->pregs[PR_ERP] = env->pc; |
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break;
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} |
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/* Fill in the IDX field. */
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env->pregs[PR_EXS] = (ex_vec & 0xff) << 8; |
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if (env->dslot) {
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D_LOG("excp isr=%x PC=%x ds=%d SP=%x"
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" ERP=%x pid=%x ccs=%x cc=%d %x\n",
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ex_vec, env->pc, env->dslot, |
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env->regs[R_SP], |
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env->pregs[PR_ERP], env->pregs[PR_PID], |
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env->pregs[PR_CCS], |
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env->cc_op, env->cc_mask); |
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/* We loose the btarget, btaken state here so rexec the
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branch. */
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env->pregs[PR_ERP] -= env->dslot; |
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/* Exception starts with dslot cleared. */
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env->dslot = 0;
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} |
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if (env->pregs[PR_CCS] & U_FLAG) {
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/* Swap stack pointers. */
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env->pregs[PR_USP] = env->regs[R_SP]; |
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env->regs[R_SP] = env->ksp; |
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} |
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/* Apply the CRIS CCS shift. Clears U if set. */
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cris_shift_ccs(env); |
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/* Now that we are in kernel mode, load the handlers address. */
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env->pc = ldl_code(env->pregs[PR_EBP] + ex_vec * 4);
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D_LOG("%s isr=%x vec=%x ccs=%x pid=%d erp=%x\n",
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__func__, env->pc, ex_vec, |
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env->pregs[PR_CCS], |
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env->pregs[PR_PID], |
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env->pregs[PR_ERP]); |
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} |
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target_phys_addr_t cpu_get_phys_page_debug(CPUState * env, target_ulong addr) |
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{ |
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uint32_t phy = addr; |
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struct cris_mmu_result res;
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int miss;
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miss = cris_mmu_translate(&res, env, addr, 0, 0); |
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if (!miss)
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phy = res.phy; |
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D(fprintf(stderr, "%s %x -> %x\n", __func__, addr, phy));
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return phy;
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} |
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#endif
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