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1 | 420557e8 | bellard | /*
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2 | 6f7e9aec | bellard | * QEMU TCX Frame buffer
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3 | 5fafdf24 | ths | *
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4 | 6f7e9aec | bellard | * Copyright (c) 2003-2005 Fabrice Bellard
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5 | 5fafdf24 | ths | *
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6 | 420557e8 | bellard | * Permission is hereby granted, free of charge, to any person obtaining a copy
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7 | 420557e8 | bellard | * of this software and associated documentation files (the "Software"), to deal
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8 | 420557e8 | bellard | * in the Software without restriction, including without limitation the rights
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9 | 420557e8 | bellard | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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10 | 420557e8 | bellard | * copies of the Software, and to permit persons to whom the Software is
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11 | 420557e8 | bellard | * furnished to do so, subject to the following conditions:
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12 | 420557e8 | bellard | *
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13 | 420557e8 | bellard | * The above copyright notice and this permission notice shall be included in
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14 | 420557e8 | bellard | * all copies or substantial portions of the Software.
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15 | 420557e8 | bellard | *
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16 | 420557e8 | bellard | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 | 420557e8 | bellard | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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18 | 420557e8 | bellard | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 | 420557e8 | bellard | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 | 420557e8 | bellard | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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21 | 420557e8 | bellard | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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22 | 420557e8 | bellard | * THE SOFTWARE.
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23 | 420557e8 | bellard | */
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24 | 87ecb68b | pbrook | #include "hw.h" |
25 | 87ecb68b | pbrook | #include "sun4m.h" |
26 | 87ecb68b | pbrook | #include "console.h" |
27 | 94470844 | blueswir1 | #include "pixel_ops.h" |
28 | 420557e8 | bellard | |
29 | 420557e8 | bellard | #define MAXX 1024 |
30 | 420557e8 | bellard | #define MAXY 768 |
31 | 6f7e9aec | bellard | #define TCX_DAC_NREGS 16 |
32 | 8508b89e | blueswir1 | #define TCX_THC_NREGS_8 0x081c |
33 | 8508b89e | blueswir1 | #define TCX_THC_NREGS_24 0x1000 |
34 | 8508b89e | blueswir1 | #define TCX_TEC_NREGS 0x1000 |
35 | 420557e8 | bellard | |
36 | 420557e8 | bellard | typedef struct TCXState { |
37 | 5dcb6b91 | blueswir1 | target_phys_addr_t addr; |
38 | 420557e8 | bellard | DisplayState *ds; |
39 | c60e08d9 | pbrook | QEMUConsole *console; |
40 | 8d5f07fa | bellard | uint8_t *vram; |
41 | eee0b836 | blueswir1 | uint32_t *vram24, *cplane; |
42 | eee0b836 | blueswir1 | ram_addr_t vram_offset, vram24_offset, cplane_offset; |
43 | eee0b836 | blueswir1 | uint16_t width, height, depth; |
44 | e80cfcfc | bellard | uint8_t r[256], g[256], b[256]; |
45 | 21206a10 | bellard | uint32_t palette[256];
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46 | 6f7e9aec | bellard | uint8_t dac_index, dac_state; |
47 | 420557e8 | bellard | } TCXState; |
48 | 420557e8 | bellard | |
49 | 95219897 | pbrook | static void tcx_screen_dump(void *opaque, const char *filename); |
50 | eee0b836 | blueswir1 | static void tcx24_screen_dump(void *opaque, const char *filename); |
51 | 97e7df27 | blueswir1 | static void tcx_invalidate_display(void *opaque); |
52 | 97e7df27 | blueswir1 | static void tcx24_invalidate_display(void *opaque); |
53 | 95219897 | pbrook | |
54 | 21206a10 | bellard | static void update_palette_entries(TCXState *s, int start, int end) |
55 | 21206a10 | bellard | { |
56 | 21206a10 | bellard | int i;
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57 | 21206a10 | bellard | for(i = start; i < end; i++) {
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58 | 21206a10 | bellard | switch(s->ds->depth) {
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59 | 21206a10 | bellard | default:
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60 | 21206a10 | bellard | case 8: |
61 | 21206a10 | bellard | s->palette[i] = rgb_to_pixel8(s->r[i], s->g[i], s->b[i]); |
62 | 21206a10 | bellard | break;
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63 | 21206a10 | bellard | case 15: |
64 | b29169d2 | blueswir1 | if (s->ds->bgr)
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65 | b29169d2 | blueswir1 | s->palette[i] = rgb_to_pixel15bgr(s->r[i], s->g[i], s->b[i]); |
66 | b29169d2 | blueswir1 | else
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67 | b29169d2 | blueswir1 | s->palette[i] = rgb_to_pixel15(s->r[i], s->g[i], s->b[i]); |
68 | 21206a10 | bellard | break;
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69 | 21206a10 | bellard | case 16: |
70 | b29169d2 | blueswir1 | if (s->ds->bgr)
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71 | b29169d2 | blueswir1 | s->palette[i] = rgb_to_pixel16bgr(s->r[i], s->g[i], s->b[i]); |
72 | b29169d2 | blueswir1 | else
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73 | b29169d2 | blueswir1 | s->palette[i] = rgb_to_pixel16(s->r[i], s->g[i], s->b[i]); |
74 | 21206a10 | bellard | break;
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75 | 21206a10 | bellard | case 32: |
76 | b29169d2 | blueswir1 | if (s->ds->bgr)
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77 | b29169d2 | blueswir1 | s->palette[i] = rgb_to_pixel32bgr(s->r[i], s->g[i], s->b[i]); |
78 | b29169d2 | blueswir1 | else
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79 | b29169d2 | blueswir1 | s->palette[i] = rgb_to_pixel32(s->r[i], s->g[i], s->b[i]); |
80 | 21206a10 | bellard | break;
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81 | 21206a10 | bellard | } |
82 | 21206a10 | bellard | } |
83 | 97e7df27 | blueswir1 | if (s->depth == 24) |
84 | 97e7df27 | blueswir1 | tcx24_invalidate_display(s); |
85 | 97e7df27 | blueswir1 | else
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86 | 97e7df27 | blueswir1 | tcx_invalidate_display(s); |
87 | 21206a10 | bellard | } |
88 | 21206a10 | bellard | |
89 | 5fafdf24 | ths | static void tcx_draw_line32(TCXState *s1, uint8_t *d, |
90 | f930d07e | blueswir1 | const uint8_t *s, int width) |
91 | 420557e8 | bellard | { |
92 | e80cfcfc | bellard | int x;
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93 | e80cfcfc | bellard | uint8_t val; |
94 | 8bdc2159 | ths | uint32_t *p = (uint32_t *)d; |
95 | e80cfcfc | bellard | |
96 | e80cfcfc | bellard | for(x = 0; x < width; x++) { |
97 | f930d07e | blueswir1 | val = *s++; |
98 | 8bdc2159 | ths | *p++ = s1->palette[val]; |
99 | e80cfcfc | bellard | } |
100 | 420557e8 | bellard | } |
101 | 420557e8 | bellard | |
102 | 5fafdf24 | ths | static void tcx_draw_line16(TCXState *s1, uint8_t *d, |
103 | f930d07e | blueswir1 | const uint8_t *s, int width) |
104 | e80cfcfc | bellard | { |
105 | e80cfcfc | bellard | int x;
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106 | e80cfcfc | bellard | uint8_t val; |
107 | 8bdc2159 | ths | uint16_t *p = (uint16_t *)d; |
108 | 8d5f07fa | bellard | |
109 | e80cfcfc | bellard | for(x = 0; x < width; x++) { |
110 | f930d07e | blueswir1 | val = *s++; |
111 | 8bdc2159 | ths | *p++ = s1->palette[val]; |
112 | e80cfcfc | bellard | } |
113 | e80cfcfc | bellard | } |
114 | e80cfcfc | bellard | |
115 | 5fafdf24 | ths | static void tcx_draw_line8(TCXState *s1, uint8_t *d, |
116 | f930d07e | blueswir1 | const uint8_t *s, int width) |
117 | 420557e8 | bellard | { |
118 | e80cfcfc | bellard | int x;
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119 | e80cfcfc | bellard | uint8_t val; |
120 | e80cfcfc | bellard | |
121 | e80cfcfc | bellard | for(x = 0; x < width; x++) { |
122 | f930d07e | blueswir1 | val = *s++; |
123 | 21206a10 | bellard | *d++ = s1->palette[val]; |
124 | 420557e8 | bellard | } |
125 | 420557e8 | bellard | } |
126 | 420557e8 | bellard | |
127 | 688ea2eb | blueswir1 | /*
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128 | 688ea2eb | blueswir1 | XXX Could be much more optimal:
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129 | 688ea2eb | blueswir1 | * detect if line/page/whole screen is in 24 bit mode
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130 | 688ea2eb | blueswir1 | * if destination is also BGR, use memcpy
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131 | 688ea2eb | blueswir1 | */
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132 | eee0b836 | blueswir1 | static inline void tcx24_draw_line32(TCXState *s1, uint8_t *d, |
133 | eee0b836 | blueswir1 | const uint8_t *s, int width, |
134 | eee0b836 | blueswir1 | const uint32_t *cplane,
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135 | eee0b836 | blueswir1 | const uint32_t *s24)
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136 | eee0b836 | blueswir1 | { |
137 | 688ea2eb | blueswir1 | int x, bgr, r, g, b;
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138 | 688ea2eb | blueswir1 | uint8_t val, *p8; |
139 | eee0b836 | blueswir1 | uint32_t *p = (uint32_t *)d; |
140 | eee0b836 | blueswir1 | uint32_t dval; |
141 | eee0b836 | blueswir1 | |
142 | 688ea2eb | blueswir1 | bgr = s1->ds->bgr; |
143 | eee0b836 | blueswir1 | for(x = 0; x < width; x++, s++, s24++) { |
144 | 688ea2eb | blueswir1 | if ((be32_to_cpu(*cplane++) & 0xff000000) == 0x03000000) { |
145 | 688ea2eb | blueswir1 | // 24-bit direct, BGR order
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146 | 688ea2eb | blueswir1 | p8 = (uint8_t *)s24; |
147 | 688ea2eb | blueswir1 | p8++; |
148 | 688ea2eb | blueswir1 | b = *p8++; |
149 | 688ea2eb | blueswir1 | g = *p8++; |
150 | 688ea2eb | blueswir1 | r = *p8++; |
151 | 688ea2eb | blueswir1 | if (bgr)
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152 | 688ea2eb | blueswir1 | dval = rgb_to_pixel32bgr(r, g, b); |
153 | 688ea2eb | blueswir1 | else
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154 | 688ea2eb | blueswir1 | dval = rgb_to_pixel32(r, g, b); |
155 | eee0b836 | blueswir1 | } else {
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156 | eee0b836 | blueswir1 | val = *s; |
157 | eee0b836 | blueswir1 | dval = s1->palette[val]; |
158 | eee0b836 | blueswir1 | } |
159 | eee0b836 | blueswir1 | *p++ = dval; |
160 | eee0b836 | blueswir1 | } |
161 | eee0b836 | blueswir1 | } |
162 | eee0b836 | blueswir1 | |
163 | 22548760 | blueswir1 | static inline int check_dirty(ram_addr_t page, ram_addr_t page24, |
164 | eee0b836 | blueswir1 | ram_addr_t cpage) |
165 | eee0b836 | blueswir1 | { |
166 | eee0b836 | blueswir1 | int ret;
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167 | eee0b836 | blueswir1 | unsigned int off; |
168 | eee0b836 | blueswir1 | |
169 | eee0b836 | blueswir1 | ret = cpu_physical_memory_get_dirty(page, VGA_DIRTY_FLAG); |
170 | eee0b836 | blueswir1 | for (off = 0; off < TARGET_PAGE_SIZE * 4; off += TARGET_PAGE_SIZE) { |
171 | eee0b836 | blueswir1 | ret |= cpu_physical_memory_get_dirty(page24 + off, VGA_DIRTY_FLAG); |
172 | eee0b836 | blueswir1 | ret |= cpu_physical_memory_get_dirty(cpage + off, VGA_DIRTY_FLAG); |
173 | eee0b836 | blueswir1 | } |
174 | eee0b836 | blueswir1 | return ret;
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175 | eee0b836 | blueswir1 | } |
176 | eee0b836 | blueswir1 | |
177 | eee0b836 | blueswir1 | static inline void reset_dirty(TCXState *ts, ram_addr_t page_min, |
178 | eee0b836 | blueswir1 | ram_addr_t page_max, ram_addr_t page24, |
179 | eee0b836 | blueswir1 | ram_addr_t cpage) |
180 | eee0b836 | blueswir1 | { |
181 | eee0b836 | blueswir1 | cpu_physical_memory_reset_dirty(page_min, page_max + TARGET_PAGE_SIZE, |
182 | eee0b836 | blueswir1 | VGA_DIRTY_FLAG); |
183 | eee0b836 | blueswir1 | page_min -= ts->vram_offset; |
184 | eee0b836 | blueswir1 | page_max -= ts->vram_offset; |
185 | eee0b836 | blueswir1 | cpu_physical_memory_reset_dirty(page24 + page_min * 4,
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186 | eee0b836 | blueswir1 | page24 + page_max * 4 + TARGET_PAGE_SIZE,
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187 | eee0b836 | blueswir1 | VGA_DIRTY_FLAG); |
188 | eee0b836 | blueswir1 | cpu_physical_memory_reset_dirty(cpage + page_min * 4,
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189 | eee0b836 | blueswir1 | cpage + page_max * 4 + TARGET_PAGE_SIZE,
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190 | eee0b836 | blueswir1 | VGA_DIRTY_FLAG); |
191 | eee0b836 | blueswir1 | } |
192 | eee0b836 | blueswir1 | |
193 | e80cfcfc | bellard | /* Fixed line length 1024 allows us to do nice tricks not possible on
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194 | e80cfcfc | bellard | VGA... */
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195 | 95219897 | pbrook | static void tcx_update_display(void *opaque) |
196 | 420557e8 | bellard | { |
197 | e80cfcfc | bellard | TCXState *ts = opaque; |
198 | 550be127 | bellard | ram_addr_t page, page_min, page_max; |
199 | 550be127 | bellard | int y, y_start, dd, ds;
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200 | e80cfcfc | bellard | uint8_t *d, *s; |
201 | b3ceef24 | blueswir1 | void (*f)(TCXState *s1, uint8_t *dst, const uint8_t *src, int width); |
202 | e80cfcfc | bellard | |
203 | e80cfcfc | bellard | if (ts->ds->depth == 0) |
204 | f930d07e | blueswir1 | return;
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205 | 6f7e9aec | bellard | page = ts->vram_offset; |
206 | e80cfcfc | bellard | y_start = -1;
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207 | 550be127 | bellard | page_min = 0xffffffff;
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208 | 550be127 | bellard | page_max = 0;
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209 | e80cfcfc | bellard | d = ts->ds->data; |
210 | 6f7e9aec | bellard | s = ts->vram; |
211 | e80cfcfc | bellard | dd = ts->ds->linesize; |
212 | e80cfcfc | bellard | ds = 1024;
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213 | e80cfcfc | bellard | |
214 | e80cfcfc | bellard | switch (ts->ds->depth) {
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215 | e80cfcfc | bellard | case 32: |
216 | f930d07e | blueswir1 | f = tcx_draw_line32; |
217 | f930d07e | blueswir1 | break;
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218 | 21206a10 | bellard | case 15: |
219 | 21206a10 | bellard | case 16: |
220 | f930d07e | blueswir1 | f = tcx_draw_line16; |
221 | f930d07e | blueswir1 | break;
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222 | e80cfcfc | bellard | default:
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223 | e80cfcfc | bellard | case 8: |
224 | f930d07e | blueswir1 | f = tcx_draw_line8; |
225 | f930d07e | blueswir1 | break;
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226 | e80cfcfc | bellard | case 0: |
227 | f930d07e | blueswir1 | return;
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228 | e80cfcfc | bellard | } |
229 | 3b46e624 | ths | |
230 | 6f7e9aec | bellard | for(y = 0; y < ts->height; y += 4, page += TARGET_PAGE_SIZE) { |
231 | f930d07e | blueswir1 | if (cpu_physical_memory_get_dirty(page, VGA_DIRTY_FLAG)) {
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232 | f930d07e | blueswir1 | if (y_start < 0) |
233 | e80cfcfc | bellard | y_start = y; |
234 | e80cfcfc | bellard | if (page < page_min)
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235 | e80cfcfc | bellard | page_min = page; |
236 | e80cfcfc | bellard | if (page > page_max)
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237 | e80cfcfc | bellard | page_max = page; |
238 | f930d07e | blueswir1 | f(ts, d, s, ts->width); |
239 | f930d07e | blueswir1 | d += dd; |
240 | f930d07e | blueswir1 | s += ds; |
241 | f930d07e | blueswir1 | f(ts, d, s, ts->width); |
242 | f930d07e | blueswir1 | d += dd; |
243 | f930d07e | blueswir1 | s += ds; |
244 | f930d07e | blueswir1 | f(ts, d, s, ts->width); |
245 | f930d07e | blueswir1 | d += dd; |
246 | f930d07e | blueswir1 | s += ds; |
247 | f930d07e | blueswir1 | f(ts, d, s, ts->width); |
248 | f930d07e | blueswir1 | d += dd; |
249 | f930d07e | blueswir1 | s += ds; |
250 | f930d07e | blueswir1 | } else {
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251 | e80cfcfc | bellard | if (y_start >= 0) { |
252 | e80cfcfc | bellard | /* flush to display */
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253 | 5fafdf24 | ths | dpy_update(ts->ds, 0, y_start,
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254 | 6f7e9aec | bellard | ts->width, y - y_start); |
255 | e80cfcfc | bellard | y_start = -1;
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256 | e80cfcfc | bellard | } |
257 | f930d07e | blueswir1 | d += dd * 4;
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258 | f930d07e | blueswir1 | s += ds * 4;
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259 | f930d07e | blueswir1 | } |
260 | e80cfcfc | bellard | } |
261 | e80cfcfc | bellard | if (y_start >= 0) { |
262 | f930d07e | blueswir1 | /* flush to display */
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263 | f930d07e | blueswir1 | dpy_update(ts->ds, 0, y_start,
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264 | f930d07e | blueswir1 | ts->width, y - y_start); |
265 | e80cfcfc | bellard | } |
266 | e80cfcfc | bellard | /* reset modified pages */
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267 | 550be127 | bellard | if (page_min <= page_max) {
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268 | 0a962c02 | bellard | cpu_physical_memory_reset_dirty(page_min, page_max + TARGET_PAGE_SIZE, |
269 | 0a962c02 | bellard | VGA_DIRTY_FLAG); |
270 | e80cfcfc | bellard | } |
271 | 420557e8 | bellard | } |
272 | 420557e8 | bellard | |
273 | eee0b836 | blueswir1 | static void tcx24_update_display(void *opaque) |
274 | eee0b836 | blueswir1 | { |
275 | eee0b836 | blueswir1 | TCXState *ts = opaque; |
276 | eee0b836 | blueswir1 | ram_addr_t page, page_min, page_max, cpage, page24; |
277 | eee0b836 | blueswir1 | int y, y_start, dd, ds;
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278 | eee0b836 | blueswir1 | uint8_t *d, *s; |
279 | eee0b836 | blueswir1 | uint32_t *cptr, *s24; |
280 | eee0b836 | blueswir1 | |
281 | eee0b836 | blueswir1 | if (ts->ds->depth != 32) |
282 | eee0b836 | blueswir1 | return;
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283 | eee0b836 | blueswir1 | page = ts->vram_offset; |
284 | eee0b836 | blueswir1 | page24 = ts->vram24_offset; |
285 | eee0b836 | blueswir1 | cpage = ts->cplane_offset; |
286 | eee0b836 | blueswir1 | y_start = -1;
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287 | eee0b836 | blueswir1 | page_min = 0xffffffff;
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288 | eee0b836 | blueswir1 | page_max = 0;
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289 | eee0b836 | blueswir1 | d = ts->ds->data; |
290 | eee0b836 | blueswir1 | s = ts->vram; |
291 | eee0b836 | blueswir1 | s24 = ts->vram24; |
292 | eee0b836 | blueswir1 | cptr = ts->cplane; |
293 | eee0b836 | blueswir1 | dd = ts->ds->linesize; |
294 | eee0b836 | blueswir1 | ds = 1024;
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295 | eee0b836 | blueswir1 | |
296 | eee0b836 | blueswir1 | for(y = 0; y < ts->height; y += 4, page += TARGET_PAGE_SIZE, |
297 | eee0b836 | blueswir1 | page24 += TARGET_PAGE_SIZE, cpage += TARGET_PAGE_SIZE) { |
298 | 22548760 | blueswir1 | if (check_dirty(page, page24, cpage)) {
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299 | eee0b836 | blueswir1 | if (y_start < 0) |
300 | eee0b836 | blueswir1 | y_start = y; |
301 | eee0b836 | blueswir1 | if (page < page_min)
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302 | eee0b836 | blueswir1 | page_min = page; |
303 | eee0b836 | blueswir1 | if (page > page_max)
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304 | eee0b836 | blueswir1 | page_max = page; |
305 | eee0b836 | blueswir1 | tcx24_draw_line32(ts, d, s, ts->width, cptr, s24); |
306 | eee0b836 | blueswir1 | d += dd; |
307 | eee0b836 | blueswir1 | s += ds; |
308 | eee0b836 | blueswir1 | cptr += ds; |
309 | eee0b836 | blueswir1 | s24 += ds; |
310 | eee0b836 | blueswir1 | tcx24_draw_line32(ts, d, s, ts->width, cptr, s24); |
311 | eee0b836 | blueswir1 | d += dd; |
312 | eee0b836 | blueswir1 | s += ds; |
313 | eee0b836 | blueswir1 | cptr += ds; |
314 | eee0b836 | blueswir1 | s24 += ds; |
315 | eee0b836 | blueswir1 | tcx24_draw_line32(ts, d, s, ts->width, cptr, s24); |
316 | eee0b836 | blueswir1 | d += dd; |
317 | eee0b836 | blueswir1 | s += ds; |
318 | eee0b836 | blueswir1 | cptr += ds; |
319 | eee0b836 | blueswir1 | s24 += ds; |
320 | eee0b836 | blueswir1 | tcx24_draw_line32(ts, d, s, ts->width, cptr, s24); |
321 | eee0b836 | blueswir1 | d += dd; |
322 | eee0b836 | blueswir1 | s += ds; |
323 | eee0b836 | blueswir1 | cptr += ds; |
324 | eee0b836 | blueswir1 | s24 += ds; |
325 | eee0b836 | blueswir1 | } else {
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326 | eee0b836 | blueswir1 | if (y_start >= 0) { |
327 | eee0b836 | blueswir1 | /* flush to display */
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328 | eee0b836 | blueswir1 | dpy_update(ts->ds, 0, y_start,
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329 | eee0b836 | blueswir1 | ts->width, y - y_start); |
330 | eee0b836 | blueswir1 | y_start = -1;
|
331 | eee0b836 | blueswir1 | } |
332 | eee0b836 | blueswir1 | d += dd * 4;
|
333 | eee0b836 | blueswir1 | s += ds * 4;
|
334 | eee0b836 | blueswir1 | cptr += ds * 4;
|
335 | eee0b836 | blueswir1 | s24 += ds * 4;
|
336 | eee0b836 | blueswir1 | } |
337 | eee0b836 | blueswir1 | } |
338 | eee0b836 | blueswir1 | if (y_start >= 0) { |
339 | eee0b836 | blueswir1 | /* flush to display */
|
340 | eee0b836 | blueswir1 | dpy_update(ts->ds, 0, y_start,
|
341 | eee0b836 | blueswir1 | ts->width, y - y_start); |
342 | eee0b836 | blueswir1 | } |
343 | eee0b836 | blueswir1 | /* reset modified pages */
|
344 | eee0b836 | blueswir1 | if (page_min <= page_max) {
|
345 | eee0b836 | blueswir1 | reset_dirty(ts, page_min, page_max, page24, cpage); |
346 | eee0b836 | blueswir1 | } |
347 | eee0b836 | blueswir1 | } |
348 | eee0b836 | blueswir1 | |
349 | 95219897 | pbrook | static void tcx_invalidate_display(void *opaque) |
350 | 420557e8 | bellard | { |
351 | e80cfcfc | bellard | TCXState *s = opaque; |
352 | e80cfcfc | bellard | int i;
|
353 | e80cfcfc | bellard | |
354 | e80cfcfc | bellard | for (i = 0; i < MAXX*MAXY; i += TARGET_PAGE_SIZE) { |
355 | f930d07e | blueswir1 | cpu_physical_memory_set_dirty(s->vram_offset + i); |
356 | e80cfcfc | bellard | } |
357 | 420557e8 | bellard | } |
358 | 420557e8 | bellard | |
359 | eee0b836 | blueswir1 | static void tcx24_invalidate_display(void *opaque) |
360 | eee0b836 | blueswir1 | { |
361 | eee0b836 | blueswir1 | TCXState *s = opaque; |
362 | eee0b836 | blueswir1 | int i;
|
363 | eee0b836 | blueswir1 | |
364 | eee0b836 | blueswir1 | tcx_invalidate_display(s); |
365 | eee0b836 | blueswir1 | for (i = 0; i < MAXX*MAXY * 4; i += TARGET_PAGE_SIZE) { |
366 | eee0b836 | blueswir1 | cpu_physical_memory_set_dirty(s->vram24_offset + i); |
367 | eee0b836 | blueswir1 | cpu_physical_memory_set_dirty(s->cplane_offset + i); |
368 | eee0b836 | blueswir1 | } |
369 | eee0b836 | blueswir1 | } |
370 | eee0b836 | blueswir1 | |
371 | e80cfcfc | bellard | static void tcx_save(QEMUFile *f, void *opaque) |
372 | 420557e8 | bellard | { |
373 | 420557e8 | bellard | TCXState *s = opaque; |
374 | 3b46e624 | ths | |
375 | 67d8cec3 | blueswir1 | qemu_put_be16s(f, &s->height); |
376 | 67d8cec3 | blueswir1 | qemu_put_be16s(f, &s->width); |
377 | 67d8cec3 | blueswir1 | qemu_put_be16s(f, &s->depth); |
378 | e80cfcfc | bellard | qemu_put_buffer(f, s->r, 256);
|
379 | e80cfcfc | bellard | qemu_put_buffer(f, s->g, 256);
|
380 | e80cfcfc | bellard | qemu_put_buffer(f, s->b, 256);
|
381 | 6f7e9aec | bellard | qemu_put_8s(f, &s->dac_index); |
382 | 6f7e9aec | bellard | qemu_put_8s(f, &s->dac_state); |
383 | 420557e8 | bellard | } |
384 | 420557e8 | bellard | |
385 | e80cfcfc | bellard | static int tcx_load(QEMUFile *f, void *opaque, int version_id) |
386 | 420557e8 | bellard | { |
387 | e80cfcfc | bellard | TCXState *s = opaque; |
388 | fda77c2d | blueswir1 | uint32_t dummy; |
389 | fda77c2d | blueswir1 | |
390 | fda77c2d | blueswir1 | if (version_id != 3 && version_id != 4) |
391 | e80cfcfc | bellard | return -EINVAL;
|
392 | e80cfcfc | bellard | |
393 | fda77c2d | blueswir1 | if (version_id == 3) { |
394 | 67d8cec3 | blueswir1 | qemu_get_be32s(f, &dummy); |
395 | 67d8cec3 | blueswir1 | qemu_get_be32s(f, &dummy); |
396 | 67d8cec3 | blueswir1 | qemu_get_be32s(f, &dummy); |
397 | fda77c2d | blueswir1 | } |
398 | 67d8cec3 | blueswir1 | qemu_get_be16s(f, &s->height); |
399 | 67d8cec3 | blueswir1 | qemu_get_be16s(f, &s->width); |
400 | 67d8cec3 | blueswir1 | qemu_get_be16s(f, &s->depth); |
401 | e80cfcfc | bellard | qemu_get_buffer(f, s->r, 256);
|
402 | e80cfcfc | bellard | qemu_get_buffer(f, s->g, 256);
|
403 | e80cfcfc | bellard | qemu_get_buffer(f, s->b, 256);
|
404 | 6f7e9aec | bellard | qemu_get_8s(f, &s->dac_index); |
405 | 6f7e9aec | bellard | qemu_get_8s(f, &s->dac_state); |
406 | 21206a10 | bellard | update_palette_entries(s, 0, 256); |
407 | 97e7df27 | blueswir1 | if (s->depth == 24) |
408 | 97e7df27 | blueswir1 | tcx24_invalidate_display(s); |
409 | 97e7df27 | blueswir1 | else
|
410 | 97e7df27 | blueswir1 | tcx_invalidate_display(s); |
411 | 5425a216 | blueswir1 | |
412 | e80cfcfc | bellard | return 0; |
413 | 420557e8 | bellard | } |
414 | 420557e8 | bellard | |
415 | e80cfcfc | bellard | static void tcx_reset(void *opaque) |
416 | 420557e8 | bellard | { |
417 | e80cfcfc | bellard | TCXState *s = opaque; |
418 | e80cfcfc | bellard | |
419 | e80cfcfc | bellard | /* Initialize palette */
|
420 | e80cfcfc | bellard | memset(s->r, 0, 256); |
421 | e80cfcfc | bellard | memset(s->g, 0, 256); |
422 | e80cfcfc | bellard | memset(s->b, 0, 256); |
423 | e80cfcfc | bellard | s->r[255] = s->g[255] = s->b[255] = 255; |
424 | 21206a10 | bellard | update_palette_entries(s, 0, 256); |
425 | e80cfcfc | bellard | memset(s->vram, 0, MAXX*MAXY);
|
426 | eee0b836 | blueswir1 | cpu_physical_memory_reset_dirty(s->vram_offset, s->vram_offset + |
427 | eee0b836 | blueswir1 | MAXX * MAXY * (1 + 4 + 4), VGA_DIRTY_FLAG); |
428 | 6f7e9aec | bellard | s->dac_index = 0;
|
429 | 6f7e9aec | bellard | s->dac_state = 0;
|
430 | 6f7e9aec | bellard | } |
431 | 6f7e9aec | bellard | |
432 | 6f7e9aec | bellard | static uint32_t tcx_dac_readl(void *opaque, target_phys_addr_t addr) |
433 | 6f7e9aec | bellard | { |
434 | 6f7e9aec | bellard | return 0; |
435 | 6f7e9aec | bellard | } |
436 | 6f7e9aec | bellard | |
437 | 6f7e9aec | bellard | static void tcx_dac_writel(void *opaque, target_phys_addr_t addr, uint32_t val) |
438 | 6f7e9aec | bellard | { |
439 | 6f7e9aec | bellard | TCXState *s = opaque; |
440 | 6f7e9aec | bellard | uint32_t saddr; |
441 | 6f7e9aec | bellard | |
442 | 6f7e9aec | bellard | saddr = (addr & (TCX_DAC_NREGS - 1)) >> 2; |
443 | 6f7e9aec | bellard | switch (saddr) {
|
444 | 6f7e9aec | bellard | case 0: |
445 | f930d07e | blueswir1 | s->dac_index = val >> 24;
|
446 | f930d07e | blueswir1 | s->dac_state = 0;
|
447 | f930d07e | blueswir1 | break;
|
448 | 6f7e9aec | bellard | case 1: |
449 | f930d07e | blueswir1 | switch (s->dac_state) {
|
450 | f930d07e | blueswir1 | case 0: |
451 | f930d07e | blueswir1 | s->r[s->dac_index] = val >> 24;
|
452 | 21206a10 | bellard | update_palette_entries(s, s->dac_index, s->dac_index + 1);
|
453 | f930d07e | blueswir1 | s->dac_state++; |
454 | f930d07e | blueswir1 | break;
|
455 | f930d07e | blueswir1 | case 1: |
456 | f930d07e | blueswir1 | s->g[s->dac_index] = val >> 24;
|
457 | 21206a10 | bellard | update_palette_entries(s, s->dac_index, s->dac_index + 1);
|
458 | f930d07e | blueswir1 | s->dac_state++; |
459 | f930d07e | blueswir1 | break;
|
460 | f930d07e | blueswir1 | case 2: |
461 | f930d07e | blueswir1 | s->b[s->dac_index] = val >> 24;
|
462 | 21206a10 | bellard | update_palette_entries(s, s->dac_index, s->dac_index + 1);
|
463 | 5c8cdbf8 | blueswir1 | s->dac_index = (s->dac_index + 1) & 255; // Index autoincrement |
464 | f930d07e | blueswir1 | default:
|
465 | f930d07e | blueswir1 | s->dac_state = 0;
|
466 | f930d07e | blueswir1 | break;
|
467 | f930d07e | blueswir1 | } |
468 | f930d07e | blueswir1 | break;
|
469 | 6f7e9aec | bellard | default:
|
470 | f930d07e | blueswir1 | break;
|
471 | 6f7e9aec | bellard | } |
472 | 6f7e9aec | bellard | return;
|
473 | 420557e8 | bellard | } |
474 | 420557e8 | bellard | |
475 | 6f7e9aec | bellard | static CPUReadMemoryFunc *tcx_dac_read[3] = { |
476 | 7c560456 | blueswir1 | NULL,
|
477 | 7c560456 | blueswir1 | NULL,
|
478 | 6f7e9aec | bellard | tcx_dac_readl, |
479 | 6f7e9aec | bellard | }; |
480 | 6f7e9aec | bellard | |
481 | 6f7e9aec | bellard | static CPUWriteMemoryFunc *tcx_dac_write[3] = { |
482 | 7c560456 | blueswir1 | NULL,
|
483 | 7c560456 | blueswir1 | NULL,
|
484 | 6f7e9aec | bellard | tcx_dac_writel, |
485 | 6f7e9aec | bellard | }; |
486 | 6f7e9aec | bellard | |
487 | 8508b89e | blueswir1 | static uint32_t tcx_dummy_readl(void *opaque, target_phys_addr_t addr) |
488 | 8508b89e | blueswir1 | { |
489 | 8508b89e | blueswir1 | return 0; |
490 | 8508b89e | blueswir1 | } |
491 | 8508b89e | blueswir1 | |
492 | 8508b89e | blueswir1 | static void tcx_dummy_writel(void *opaque, target_phys_addr_t addr, |
493 | 8508b89e | blueswir1 | uint32_t val) |
494 | 8508b89e | blueswir1 | { |
495 | 8508b89e | blueswir1 | } |
496 | 8508b89e | blueswir1 | |
497 | 8508b89e | blueswir1 | static CPUReadMemoryFunc *tcx_dummy_read[3] = { |
498 | 7c560456 | blueswir1 | NULL,
|
499 | 7c560456 | blueswir1 | NULL,
|
500 | 8508b89e | blueswir1 | tcx_dummy_readl, |
501 | 8508b89e | blueswir1 | }; |
502 | 8508b89e | blueswir1 | |
503 | 8508b89e | blueswir1 | static CPUWriteMemoryFunc *tcx_dummy_write[3] = { |
504 | 7c560456 | blueswir1 | NULL,
|
505 | 7c560456 | blueswir1 | NULL,
|
506 | 8508b89e | blueswir1 | tcx_dummy_writel, |
507 | 8508b89e | blueswir1 | }; |
508 | 8508b89e | blueswir1 | |
509 | 5dcb6b91 | blueswir1 | void tcx_init(DisplayState *ds, target_phys_addr_t addr, uint8_t *vram_base,
|
510 | eee0b836 | blueswir1 | unsigned long vram_offset, int vram_size, int width, int height, |
511 | eee0b836 | blueswir1 | int depth)
|
512 | 420557e8 | bellard | { |
513 | 420557e8 | bellard | TCXState *s; |
514 | 8508b89e | blueswir1 | int io_memory, dummy_memory;
|
515 | eee0b836 | blueswir1 | int size;
|
516 | 420557e8 | bellard | |
517 | 420557e8 | bellard | s = qemu_mallocz(sizeof(TCXState));
|
518 | 420557e8 | bellard | if (!s)
|
519 | 95219897 | pbrook | return;
|
520 | 420557e8 | bellard | s->ds = ds; |
521 | 8d5f07fa | bellard | s->addr = addr; |
522 | e80cfcfc | bellard | s->vram_offset = vram_offset; |
523 | 6f7e9aec | bellard | s->width = width; |
524 | 6f7e9aec | bellard | s->height = height; |
525 | eee0b836 | blueswir1 | s->depth = depth; |
526 | eee0b836 | blueswir1 | |
527 | eee0b836 | blueswir1 | // 8-bit plane
|
528 | eee0b836 | blueswir1 | s->vram = vram_base; |
529 | eee0b836 | blueswir1 | size = vram_size; |
530 | 5dcb6b91 | blueswir1 | cpu_register_physical_memory(addr + 0x00800000ULL, size, vram_offset);
|
531 | eee0b836 | blueswir1 | vram_offset += size; |
532 | eee0b836 | blueswir1 | vram_base += size; |
533 | e80cfcfc | bellard | |
534 | 6f7e9aec | bellard | io_memory = cpu_register_io_memory(0, tcx_dac_read, tcx_dac_write, s);
|
535 | 77f193da | blueswir1 | cpu_register_physical_memory(addr + 0x00200000ULL, TCX_DAC_NREGS,
|
536 | 77f193da | blueswir1 | io_memory); |
537 | eee0b836 | blueswir1 | |
538 | 8508b89e | blueswir1 | dummy_memory = cpu_register_io_memory(0, tcx_dummy_read, tcx_dummy_write,
|
539 | 8508b89e | blueswir1 | s); |
540 | 5dcb6b91 | blueswir1 | cpu_register_physical_memory(addr + 0x00700000ULL, TCX_TEC_NREGS,
|
541 | 8508b89e | blueswir1 | dummy_memory); |
542 | eee0b836 | blueswir1 | if (depth == 24) { |
543 | eee0b836 | blueswir1 | // 24-bit plane
|
544 | eee0b836 | blueswir1 | size = vram_size * 4;
|
545 | eee0b836 | blueswir1 | s->vram24 = (uint32_t *)vram_base; |
546 | eee0b836 | blueswir1 | s->vram24_offset = vram_offset; |
547 | 5dcb6b91 | blueswir1 | cpu_register_physical_memory(addr + 0x02000000ULL, size, vram_offset);
|
548 | eee0b836 | blueswir1 | vram_offset += size; |
549 | eee0b836 | blueswir1 | vram_base += size; |
550 | eee0b836 | blueswir1 | |
551 | eee0b836 | blueswir1 | // Control plane
|
552 | eee0b836 | blueswir1 | size = vram_size * 4;
|
553 | eee0b836 | blueswir1 | s->cplane = (uint32_t *)vram_base; |
554 | eee0b836 | blueswir1 | s->cplane_offset = vram_offset; |
555 | 5dcb6b91 | blueswir1 | cpu_register_physical_memory(addr + 0x0a000000ULL, size, vram_offset);
|
556 | c60e08d9 | pbrook | s->console = graphic_console_init(s->ds, tcx24_update_display, |
557 | c60e08d9 | pbrook | tcx24_invalidate_display, |
558 | c60e08d9 | pbrook | tcx24_screen_dump, NULL, s);
|
559 | eee0b836 | blueswir1 | } else {
|
560 | 5dcb6b91 | blueswir1 | cpu_register_physical_memory(addr + 0x00300000ULL, TCX_THC_NREGS_8,
|
561 | 8508b89e | blueswir1 | dummy_memory); |
562 | c60e08d9 | pbrook | s->console = graphic_console_init(s->ds, tcx_update_display, |
563 | c60e08d9 | pbrook | tcx_invalidate_display, |
564 | c60e08d9 | pbrook | tcx_screen_dump, NULL, s);
|
565 | eee0b836 | blueswir1 | } |
566 | f96f4c9d | blueswir1 | // NetBSD writes here even with 8-bit display
|
567 | 5dcb6b91 | blueswir1 | cpu_register_physical_memory(addr + 0x00301000ULL, TCX_THC_NREGS_24,
|
568 | f96f4c9d | blueswir1 | dummy_memory); |
569 | e80cfcfc | bellard | |
570 | fda77c2d | blueswir1 | register_savevm("tcx", addr, 4, tcx_save, tcx_load, s); |
571 | e80cfcfc | bellard | qemu_register_reset(tcx_reset, s); |
572 | e80cfcfc | bellard | tcx_reset(s); |
573 | c60e08d9 | pbrook | qemu_console_resize(s->console, width, height); |
574 | 420557e8 | bellard | } |
575 | 420557e8 | bellard | |
576 | 95219897 | pbrook | static void tcx_screen_dump(void *opaque, const char *filename) |
577 | 8d5f07fa | bellard | { |
578 | e80cfcfc | bellard | TCXState *s = opaque; |
579 | 8d5f07fa | bellard | FILE *f; |
580 | e80cfcfc | bellard | uint8_t *d, *d1, v; |
581 | 8d5f07fa | bellard | int y, x;
|
582 | 8d5f07fa | bellard | |
583 | 8d5f07fa | bellard | f = fopen(filename, "wb");
|
584 | 8d5f07fa | bellard | if (!f)
|
585 | e80cfcfc | bellard | return;
|
586 | 6f7e9aec | bellard | fprintf(f, "P6\n%d %d\n%d\n", s->width, s->height, 255); |
587 | 6f7e9aec | bellard | d1 = s->vram; |
588 | 6f7e9aec | bellard | for(y = 0; y < s->height; y++) { |
589 | 8d5f07fa | bellard | d = d1; |
590 | 6f7e9aec | bellard | for(x = 0; x < s->width; x++) { |
591 | 8d5f07fa | bellard | v = *d; |
592 | e80cfcfc | bellard | fputc(s->r[v], f); |
593 | e80cfcfc | bellard | fputc(s->g[v], f); |
594 | e80cfcfc | bellard | fputc(s->b[v], f); |
595 | 8d5f07fa | bellard | d++; |
596 | 8d5f07fa | bellard | } |
597 | e80cfcfc | bellard | d1 += MAXX; |
598 | 8d5f07fa | bellard | } |
599 | 8d5f07fa | bellard | fclose(f); |
600 | 8d5f07fa | bellard | return;
|
601 | 8d5f07fa | bellard | } |
602 | 8d5f07fa | bellard | |
603 | eee0b836 | blueswir1 | static void tcx24_screen_dump(void *opaque, const char *filename) |
604 | eee0b836 | blueswir1 | { |
605 | eee0b836 | blueswir1 | TCXState *s = opaque; |
606 | eee0b836 | blueswir1 | FILE *f; |
607 | eee0b836 | blueswir1 | uint8_t *d, *d1, v; |
608 | eee0b836 | blueswir1 | uint32_t *s24, *cptr, dval; |
609 | eee0b836 | blueswir1 | int y, x;
|
610 | 8d5f07fa | bellard | |
611 | eee0b836 | blueswir1 | f = fopen(filename, "wb");
|
612 | eee0b836 | blueswir1 | if (!f)
|
613 | eee0b836 | blueswir1 | return;
|
614 | eee0b836 | blueswir1 | fprintf(f, "P6\n%d %d\n%d\n", s->width, s->height, 255); |
615 | eee0b836 | blueswir1 | d1 = s->vram; |
616 | eee0b836 | blueswir1 | s24 = s->vram24; |
617 | eee0b836 | blueswir1 | cptr = s->cplane; |
618 | eee0b836 | blueswir1 | for(y = 0; y < s->height; y++) { |
619 | eee0b836 | blueswir1 | d = d1; |
620 | eee0b836 | blueswir1 | for(x = 0; x < s->width; x++, d++, s24++) { |
621 | eee0b836 | blueswir1 | if ((*cptr++ & 0xff000000) == 0x03000000) { // 24-bit direct |
622 | eee0b836 | blueswir1 | dval = *s24 & 0x00ffffff;
|
623 | eee0b836 | blueswir1 | fputc((dval >> 16) & 0xff, f); |
624 | eee0b836 | blueswir1 | fputc((dval >> 8) & 0xff, f); |
625 | eee0b836 | blueswir1 | fputc(dval & 0xff, f);
|
626 | eee0b836 | blueswir1 | } else {
|
627 | eee0b836 | blueswir1 | v = *d; |
628 | eee0b836 | blueswir1 | fputc(s->r[v], f); |
629 | eee0b836 | blueswir1 | fputc(s->g[v], f); |
630 | eee0b836 | blueswir1 | fputc(s->b[v], f); |
631 | eee0b836 | blueswir1 | } |
632 | eee0b836 | blueswir1 | } |
633 | eee0b836 | blueswir1 | d1 += MAXX; |
634 | eee0b836 | blueswir1 | } |
635 | eee0b836 | blueswir1 | fclose(f); |
636 | eee0b836 | blueswir1 | return;
|
637 | eee0b836 | blueswir1 | } |