Revision 9dd749aa hw/pcnet.c
b/hw/pcnet.c | ||
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1981 | 1981 |
|
1982 | 1982 |
pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_AMD); |
1983 | 1983 |
pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_AMD_LANCE); |
1984 |
/* TODO: value should be 0 at RST# */ |
|
1985 |
pci_set_word(pci_conf + PCI_COMMAND, |
|
1986 |
PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); |
|
1987 | 1984 |
pci_set_word(pci_conf + PCI_STATUS, |
1988 | 1985 |
PCI_STATUS_FAST_BACK | PCI_STATUS_DEVSEL_MEDIUM); |
1989 | 1986 |
pci_conf[PCI_REVISION_ID] = 0x10; |
1990 |
/* TODO: 0 is the default anyway, no need to set it. */ |
|
1991 |
pci_conf[PCI_CLASS_PROG] = 0x00; |
|
1992 | 1987 |
pci_config_set_class(pci_conf, PCI_CLASS_NETWORK_ETHERNET); |
1993 | 1988 |
|
1994 |
/* TODO: not necessary, is set when BAR is registered. */ |
|
1995 |
pci_set_long(pci_conf + PCI_BASE_ADDRESS_0, PCI_BASE_ADDRESS_SPACE_IO); |
|
1996 |
pci_set_long(pci_conf + PCI_BASE_ADDRESS_0 + 4, |
|
1997 |
PCI_BASE_ADDRESS_SPACE_MEMORY); |
|
1998 |
|
|
1999 | 1989 |
pci_set_word(pci_conf + PCI_SUBSYSTEM_VENDOR_ID, 0x0); |
2000 | 1990 |
pci_set_word(pci_conf + PCI_SUBSYSTEM_ID, 0x0); |
2001 | 1991 |
|
2002 |
/* TODO: value must be 0 at RST# */ |
|
2003 | 1992 |
pci_conf[PCI_INTERRUPT_PIN] = 1; // interrupt pin 0 |
2004 | 1993 |
pci_conf[PCI_MIN_GNT] = 0x06; |
2005 | 1994 |
pci_conf[PCI_MAX_LAT] = 0xff; |
... | ... | |
2008 | 1997 |
s->mmio_index = |
2009 | 1998 |
cpu_register_io_memory(pcnet_mmio_read, pcnet_mmio_write, &d->state); |
2010 | 1999 |
|
2011 |
/* TODO: use pci_dev, avoid cast below. */ |
|
2012 |
pci_register_bar((PCIDevice *)d, 0, PCNET_IOPORT_SIZE, |
|
2000 |
pci_register_bar(pci_dev, 0, PCNET_IOPORT_SIZE, |
|
2013 | 2001 |
PCI_BASE_ADDRESS_SPACE_IO, pcnet_ioport_map); |
2014 | 2002 |
|
2015 |
pci_register_bar((PCIDevice *)d, 1, PCNET_PNPMMIO_SIZE,
|
|
2003 |
pci_register_bar(pci_dev, 1, PCNET_PNPMMIO_SIZE,
|
|
2016 | 2004 |
PCI_BASE_ADDRESS_SPACE_MEMORY, pcnet_mmio_map); |
2017 | 2005 |
|
2018 | 2006 |
s->irq = pci_dev->irq[0]; |
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