Revision 9e56e756 target-mips/translate.c
| b/target-mips/translate.c | ||
|---|---|---|
| 12813 | 12813 |
/* Count register increments in debug mode, EJTAG version 1 */ |
| 12814 | 12814 |
env->CP0_Debug = (1 << CP0DB_CNT) | (0x1 << CP0DB_VER); |
| 12815 | 12815 |
env->hflags = MIPS_HFLAG_CP0; |
| 12816 |
|
|
| 12817 |
if (env->CP0_Config3 & (1 << CP0C3_MT)) {
|
|
| 12818 |
int i; |
|
| 12819 |
|
|
| 12820 |
/* Only TC0 on VPE 0 starts as active. */ |
|
| 12821 |
for (i = 0; i < ARRAY_SIZE(env->tcs); i++) {
|
|
| 12822 |
env->tcs[i].CP0_TCBind = env->cpu_index << CP0TCBd_CurVPE; |
|
| 12823 |
env->tcs[i].CP0_TCHalt = 1; |
|
| 12824 |
} |
|
| 12825 |
env->active_tc.CP0_TCHalt = 1; |
|
| 12826 |
env->halted = 1; |
|
| 12827 |
|
|
| 12828 |
if (!env->cpu_index) {
|
|
| 12829 |
/* VPE0 starts up enabled. */ |
|
| 12830 |
env->mvp->CP0_MVPControl |= (1 << CP0MVPCo_EVP); |
|
| 12831 |
env->CP0_VPEConf0 |= (1 << CP0VPEC0_MVP) | (1 << CP0VPEC0_VPA); |
|
| 12832 |
|
|
| 12833 |
/* TC0 starts up unhalted. */ |
|
| 12834 |
env->halted = 0; |
|
| 12835 |
env->active_tc.CP0_TCHalt = 0; |
|
| 12836 |
env->tcs[0].CP0_TCHalt = 0; |
|
| 12837 |
/* With thread 0 active. */ |
|
| 12838 |
env->active_tc.CP0_TCStatus = (1 << CP0TCSt_A); |
|
| 12839 |
env->tcs[0].CP0_TCStatus = (1 << CP0TCSt_A); |
|
| 12840 |
} |
|
| 12841 |
} |
|
| 12816 | 12842 |
#endif |
| 12817 | 12843 |
#if defined(TARGET_MIPS64) |
| 12818 | 12844 |
if (env->cpu_model->insn_flags & ISA_MIPS3) {
|
Also available in: Unified diff