Revision 9ee6e8bb target-arm/cpu.h
| b/target-arm/cpu.h | ||
|---|---|---|
| 37 | 37 |
#define EXCP_IRQ 5 |
| 38 | 38 |
#define EXCP_FIQ 6 |
| 39 | 39 |
#define EXCP_BKPT 7 |
| 40 |
#define EXCP_EXCEPTION_EXIT 8 /* Return from v7M exception. */ |
|
| 41 |
|
|
| 42 |
#define ARMV7M_EXCP_RESET 1 |
|
| 43 |
#define ARMV7M_EXCP_NMI 2 |
|
| 44 |
#define ARMV7M_EXCP_HARD 3 |
|
| 45 |
#define ARMV7M_EXCP_MEM 4 |
|
| 46 |
#define ARMV7M_EXCP_BUS 5 |
|
| 47 |
#define ARMV7M_EXCP_USAGE 6 |
|
| 48 |
#define ARMV7M_EXCP_SVC 11 |
|
| 49 |
#define ARMV7M_EXCP_DEBUG 12 |
|
| 50 |
#define ARMV7M_EXCP_PENDSV 14 |
|
| 51 |
#define ARMV7M_EXCP_SYSTICK 15 |
|
| 40 | 52 |
|
| 41 | 53 |
typedef void ARMWriteCPFunc(void *opaque, int cp_info, |
| 42 | 54 |
int srcreg, int operand, uint32_t value); |
| ... | ... | |
| 76 | 88 |
uint32_t VF; /* V is the bit 31. All other bits are undefined */ |
| 77 | 89 |
uint32_t NZF; /* N is bit 31. Z is computed from NZF */ |
| 78 | 90 |
uint32_t QF; /* 0 or 1 */ |
| 79 |
|
|
| 80 |
int thumb; /* 0 = arm mode, 1 = thumb mode */ |
|
| 91 |
uint32_t GE; /* cpsr[19:16] */ |
|
| 92 |
int thumb; /* cprs[5]. 0 = arm mode, 1 = thumb mode. */ |
|
| 93 |
uint32_t condexec_bits; /* IT bits. cpsr[15:10,26:25]. */ |
|
| 81 | 94 |
|
| 82 | 95 |
/* System control coprocessor (cp15) */ |
| 83 | 96 |
struct {
|
| 84 | 97 |
uint32_t c0_cpuid; |
| 85 | 98 |
uint32_t c0_cachetype; |
| 99 |
uint32_t c0_c1[8]; /* Feature registers. */ |
|
| 100 |
uint32_t c0_c2[8]; /* Instruction set registers. */ |
|
| 86 | 101 |
uint32_t c1_sys; /* System control register. */ |
| 87 | 102 |
uint32_t c1_coproc; /* Coprocessor access register. */ |
| 88 | 103 |
uint32_t c1_xscaleauxcr; /* XScale auxiliary control register. */ |
| 89 |
uint32_t c2_base; /* MMU translation table base. */ |
|
| 104 |
uint32_t c2_base0; /* MMU translation table base 0. */ |
|
| 105 |
uint32_t c2_base1; /* MMU translation table base 1. */ |
|
| 106 |
uint32_t c2_mask; /* MMU translation table base mask. */ |
|
| 90 | 107 |
uint32_t c2_data; /* MPU data cachable bits. */ |
| 91 | 108 |
uint32_t c2_insn; /* MPU instruction cachable bits. */ |
| 92 | 109 |
uint32_t c3; /* MMU domain access control register |
| ... | ... | |
| 100 | 117 |
uint32_t c9_data; |
| 101 | 118 |
uint32_t c13_fcse; /* FCSE PID. */ |
| 102 | 119 |
uint32_t c13_context; /* Context ID. */ |
| 120 |
uint32_t c13_tls1; /* User RW Thread register. */ |
|
| 121 |
uint32_t c13_tls2; /* User RO Thread register. */ |
|
| 122 |
uint32_t c13_tls3; /* Privileged Thread register. */ |
|
| 103 | 123 |
uint32_t c15_cpar; /* XScale Coprocessor Access Register */ |
| 104 | 124 |
uint32_t c15_ticonfig; /* TI925T configuration byte. */ |
| 105 | 125 |
uint32_t c15_i_max; /* Maximum D-cache dirty line index. */ |
| ... | ... | |
| 107 | 127 |
uint32_t c15_threadid; /* TI debugger thread-ID. */ |
| 108 | 128 |
} cp15; |
| 109 | 129 |
|
| 130 |
struct {
|
|
| 131 |
uint32_t other_sp; |
|
| 132 |
uint32_t vecbase; |
|
| 133 |
uint32_t basepri; |
|
| 134 |
uint32_t control; |
|
| 135 |
int current_sp; |
|
| 136 |
int exception; |
|
| 137 |
int pending_exception; |
|
| 138 |
void *nvic; |
|
| 139 |
} v7m; |
|
| 140 |
|
|
| 110 | 141 |
/* Coprocessor IO used by peripherals */ |
| 111 | 142 |
struct {
|
| 112 | 143 |
ARMReadCPFunc *cp_read; |
| ... | ... | |
| 117 | 148 |
/* Internal CPU feature flags. */ |
| 118 | 149 |
uint32_t features; |
| 119 | 150 |
|
| 151 |
/* Callback for vectored interrupt controller. */ |
|
| 152 |
int (*get_irq_vector)(struct CPUARMState *); |
|
| 153 |
void *irq_opaque; |
|
| 154 |
|
|
| 120 | 155 |
/* exception/interrupt handling */ |
| 121 | 156 |
jmp_buf jmp_env; |
| 122 | 157 |
int exception_index; |
| ... | ... | |
| 126 | 161 |
|
| 127 | 162 |
/* VFP coprocessor state. */ |
| 128 | 163 |
struct {
|
| 129 |
float64 regs[16];
|
|
| 164 |
float64 regs[32];
|
|
| 130 | 165 |
|
| 131 | 166 |
uint32_t xregs[16]; |
| 132 | 167 |
/* We store these fpcsr fields separately for convenience. */ |
| ... | ... | |
| 136 | 171 |
/* Temporary variables if we don't have spare fp regs. */ |
| 137 | 172 |
float32 tmp0s, tmp1s; |
| 138 | 173 |
float64 tmp0d, tmp1d; |
| 174 |
/* scratch space when Tn are not sufficient. */ |
|
| 175 |
uint32_t scratch[8]; |
|
| 139 | 176 |
|
| 140 | 177 |
float_status fp_status; |
| 141 | 178 |
} vfp; |
| 179 |
#if defined(CONFIG_USER_ONLY) |
|
| 180 |
struct mmon_state *mmon_entry; |
|
| 181 |
#else |
|
| 182 |
uint32_t mmon_addr; |
|
| 183 |
#endif |
|
| 142 | 184 |
|
| 143 | 185 |
/* iwMMXt coprocessor state. */ |
| 144 | 186 |
struct {
|
| ... | ... | |
| 169 | 211 |
void cpu_arm_close(CPUARMState *s); |
| 170 | 212 |
void do_interrupt(CPUARMState *); |
| 171 | 213 |
void switch_mode(CPUARMState *, int); |
| 214 |
uint32_t do_arm_semihosting(CPUARMState *env); |
|
| 172 | 215 |
|
| 173 | 216 |
/* you can call this signal handler from your SIGBUS and SIGSEGV |
| 174 | 217 |
signal handlers to inform the virtual CPU of exceptions. non zero |
| ... | ... | |
| 176 | 219 |
int cpu_arm_signal_handler(int host_signum, void *pinfo, |
| 177 | 220 |
void *puc); |
| 178 | 221 |
|
| 222 |
void cpu_lock(void); |
|
| 223 |
void cpu_unlock(void); |
|
| 224 |
|
|
| 179 | 225 |
#define CPSR_M (0x1f) |
| 180 | 226 |
#define CPSR_T (1 << 5) |
| 181 | 227 |
#define CPSR_F (1 << 6) |
| ... | ... | |
| 183 | 229 |
#define CPSR_A (1 << 8) |
| 184 | 230 |
#define CPSR_E (1 << 9) |
| 185 | 231 |
#define CPSR_IT_2_7 (0xfc00) |
| 186 |
/* Bits 20-23 reserved. */ |
|
| 232 |
#define CPSR_GE (0xf << 16) |
|
| 233 |
#define CPSR_RESERVED (0xf << 20) |
|
| 187 | 234 |
#define CPSR_J (1 << 24) |
| 188 | 235 |
#define CPSR_IT_0_1 (3 << 25) |
| 189 | 236 |
#define CPSR_Q (1 << 27) |
| 190 |
#define CPSR_NZCV (0xf << 28) |
|
| 237 |
#define CPSR_V (1 << 28) |
|
| 238 |
#define CPSR_C (1 << 29) |
|
| 239 |
#define CPSR_Z (1 << 30) |
|
| 240 |
#define CPSR_N (1 << 31) |
|
| 241 |
#define CPSR_NZCV (CPSR_N | CPSR_Z | CPSR_C | CPSR_V) |
|
| 242 |
|
|
| 243 |
#define CPSR_IT (CPSR_IT_0_1 | CPSR_IT_2_7) |
|
| 244 |
#define CACHED_CPSR_BITS (CPSR_T | CPSR_GE | CPSR_IT | CPSR_Q | CPSR_NZCV) |
|
| 245 |
/* Bits writable in user mode. */ |
|
| 246 |
#define CPSR_USER (CPSR_NZCV | CPSR_Q | CPSR_GE) |
|
| 247 |
/* Execution state bits. MRS read as zero, MSR writes ignored. */ |
|
| 248 |
#define CPSR_EXEC (CPSR_T | CPSR_IT | CPSR_J) |
|
| 191 | 249 |
|
| 192 |
#define CACHED_CPSR_BITS (CPSR_T | CPSR_Q | CPSR_NZCV) |
|
| 193 | 250 |
/* Return the current CPSR value. */ |
| 194 | 251 |
static inline uint32_t cpsr_read(CPUARMState *env) |
| 195 | 252 |
{
|
| ... | ... | |
| 197 | 254 |
ZF = (env->NZF == 0); |
| 198 | 255 |
return env->uncached_cpsr | (env->NZF & 0x80000000) | (ZF << 30) | |
| 199 | 256 |
(env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27) |
| 200 |
| (env->thumb << 5); |
|
| 257 |
| (env->thumb << 5) | ((env->condexec_bits & 3) << 25) |
|
| 258 |
| ((env->condexec_bits & 0xfc) << 8) |
|
| 259 |
| (env->GE << 16); |
|
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} |
|
| 261 |
|
|
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/* Return the current xPSR value. */ |
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static inline uint32_t xpsr_read(CPUARMState *env) |
|
| 264 |
{
|
|
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int ZF; |
|
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ZF = (env->NZF == 0); |
|
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return (env->NZF & 0x80000000) | (ZF << 30) |
|
| 268 |
| (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27) |
|
| 269 |
| (env->thumb << 24) | ((env->condexec_bits & 3) << 25) |
|
| 270 |
| ((env->condexec_bits & 0xfc) << 8) |
|
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| env->v7m.exception; |
|
| 201 | 272 |
} |
| 202 | 273 |
|
| 203 | 274 |
/* Set the CPSR. Note that some bits of mask must be all-set or all-clear. */ |
| ... | ... | |
| 213 | 284 |
env->QF = ((val & CPSR_Q) != 0); |
| 214 | 285 |
if (mask & CPSR_T) |
| 215 | 286 |
env->thumb = ((val & CPSR_T) != 0); |
| 287 |
if (mask & CPSR_IT_0_1) {
|
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env->condexec_bits &= ~3; |
|
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env->condexec_bits |= (val >> 25) & 3; |
|
| 290 |
} |
|
| 291 |
if (mask & CPSR_IT_2_7) {
|
|
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env->condexec_bits &= 3; |
|
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env->condexec_bits |= (val >> 8) & 0xfc; |
|
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} |
|
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if (mask & CPSR_GE) {
|
|
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env->GE = (val >> 16) & 0xf; |
|
| 297 |
} |
|
| 216 | 298 |
|
| 217 | 299 |
if ((env->uncached_cpsr ^ val) & mask & CPSR_M) {
|
| 218 | 300 |
switch_mode(env, val & CPSR_M); |
| ... | ... | |
| 221 | 303 |
env->uncached_cpsr = (env->uncached_cpsr & ~mask) | (val & mask); |
| 222 | 304 |
} |
| 223 | 305 |
|
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/* Set the xPSR. Note that some bits of mask must be all-set or all-clear. */ |
|
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static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask) |
|
| 308 |
{
|
|
| 309 |
/* NOTE: N = 1 and Z = 1 cannot be stored currently */ |
|
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if (mask & CPSR_NZCV) {
|
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env->NZF = (val & 0xc0000000) ^ 0x40000000; |
|
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env->CF = (val >> 29) & 1; |
|
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env->VF = (val << 3) & 0x80000000; |
|
| 314 |
} |
|
| 315 |
if (mask & CPSR_Q) |
|
| 316 |
env->QF = ((val & CPSR_Q) != 0); |
|
| 317 |
if (mask & (1 << 24)) |
|
| 318 |
env->thumb = ((val & (1 << 24)) != 0); |
|
| 319 |
if (mask & CPSR_IT_0_1) {
|
|
| 320 |
env->condexec_bits &= ~3; |
|
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env->condexec_bits |= (val >> 25) & 3; |
|
| 322 |
} |
|
| 323 |
if (mask & CPSR_IT_2_7) {
|
|
| 324 |
env->condexec_bits &= 3; |
|
| 325 |
env->condexec_bits |= (val >> 8) & 0xfc; |
|
| 326 |
} |
|
| 327 |
if (mask & 0x1ff) {
|
|
| 328 |
env->v7m.exception = val & 0x1ff; |
|
| 329 |
} |
|
| 330 |
} |
|
| 331 |
|
|
| 224 | 332 |
enum arm_cpu_mode {
|
| 225 | 333 |
ARM_CPU_MODE_USR = 0x10, |
| 226 | 334 |
ARM_CPU_MODE_FIQ = 0x11, |
| ... | ... | |
| 234 | 342 |
/* VFP system registers. */ |
| 235 | 343 |
#define ARM_VFP_FPSID 0 |
| 236 | 344 |
#define ARM_VFP_FPSCR 1 |
| 345 |
#define ARM_VFP_MVFR1 6 |
|
| 346 |
#define ARM_VFP_MVFR0 7 |
|
| 237 | 347 |
#define ARM_VFP_FPEXC 8 |
| 238 | 348 |
#define ARM_VFP_FPINST 9 |
| 239 | 349 |
#define ARM_VFP_FPINST2 10 |
| ... | ... | |
| 253 | 363 |
ARM_FEATURE_AUXCR, /* ARM1026 Auxiliary control register. */ |
| 254 | 364 |
ARM_FEATURE_XSCALE, /* Intel XScale extensions. */ |
| 255 | 365 |
ARM_FEATURE_IWMMXT, /* Intel iwMMXt extension. */ |
| 366 |
ARM_FEATURE_V6, |
|
| 367 |
ARM_FEATURE_V6K, |
|
| 368 |
ARM_FEATURE_V7, |
|
| 369 |
ARM_FEATURE_THUMB2, |
|
| 256 | 370 |
ARM_FEATURE_MPU, /* Only has Memory Protection Unit, not full MMU. */ |
| 371 |
ARM_FEATURE_VFP3, |
|
| 372 |
ARM_FEATURE_NEON, |
|
| 373 |
ARM_FEATURE_DIV, |
|
| 374 |
ARM_FEATURE_M, /* Microcontroller profile. */ |
|
| 257 | 375 |
ARM_FEATURE_OMAPCP /* OMAP specific CP15 ops handling. */ |
| 258 | 376 |
}; |
| 259 | 377 |
|
| ... | ... | |
| 264 | 382 |
|
| 265 | 383 |
void arm_cpu_list(FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...)); |
| 266 | 384 |
|
| 385 |
/* Interface between CPU and Interrupt controller. */ |
|
| 386 |
void armv7m_nvic_set_pending(void *opaque, int irq); |
|
| 387 |
int armv7m_nvic_acknowledge_irq(void *opaque); |
|
| 388 |
void armv7m_nvic_complete_irq(void *opaque, int irq); |
|
| 389 |
|
|
| 267 | 390 |
void cpu_arm_set_cp_io(CPUARMState *env, int cpnum, |
| 268 | 391 |
ARMReadCPFunc *cp_read, ARMWriteCPFunc *cp_write, |
| 269 | 392 |
void *opaque); |
| 270 | 393 |
|
| 271 |
#define ARM_CPUID_ARM1026 0x4106a262 |
|
| 272 |
#define ARM_CPUID_ARM926 0x41069265 |
|
| 273 |
#define ARM_CPUID_ARM946 0x41059461 |
|
| 274 |
#define ARM_CPUID_TI915T 0x54029152 |
|
| 275 |
#define ARM_CPUID_TI925T 0x54029252 |
|
| 276 |
#define ARM_CPUID_PXA250 0x69052100 |
|
| 277 |
#define ARM_CPUID_PXA255 0x69052d00 |
|
| 278 |
#define ARM_CPUID_PXA260 0x69052903 |
|
| 279 |
#define ARM_CPUID_PXA261 0x69052d05 |
|
| 280 |
#define ARM_CPUID_PXA262 0x69052d06 |
|
| 281 |
#define ARM_CPUID_PXA270 0x69054110 |
|
| 282 |
#define ARM_CPUID_PXA270_A0 0x69054110 |
|
| 283 |
#define ARM_CPUID_PXA270_A1 0x69054111 |
|
| 284 |
#define ARM_CPUID_PXA270_B0 0x69054112 |
|
| 285 |
#define ARM_CPUID_PXA270_B1 0x69054113 |
|
| 286 |
#define ARM_CPUID_PXA270_C0 0x69054114 |
|
| 287 |
#define ARM_CPUID_PXA270_C5 0x69054117 |
|
| 394 |
/* Does the core conform to the the "MicroController" profile. e.g. Cortex-M3. |
|
| 395 |
Note the M in older cores (eg. ARM7TDMI) stands for Multiply. These are |
|
| 396 |
conventional cores (ie. Application or Realtime profile). */ |
|
| 397 |
|
|
| 398 |
#define IS_M(env) arm_feature(env, ARM_FEATURE_M) |
|
| 399 |
#define ARM_CPUID(env) (env->cp15.c0_cpuid) |
|
| 400 |
|
|
| 401 |
#define ARM_CPUID_ARM1026 0x4106a262 |
|
| 402 |
#define ARM_CPUID_ARM926 0x41069265 |
|
| 403 |
#define ARM_CPUID_ARM946 0x41059461 |
|
| 404 |
#define ARM_CPUID_TI915T 0x54029152 |
|
| 405 |
#define ARM_CPUID_TI925T 0x54029252 |
|
| 406 |
#define ARM_CPUID_PXA250 0x69052100 |
|
| 407 |
#define ARM_CPUID_PXA255 0x69052d00 |
|
| 408 |
#define ARM_CPUID_PXA260 0x69052903 |
|
| 409 |
#define ARM_CPUID_PXA261 0x69052d05 |
|
| 410 |
#define ARM_CPUID_PXA262 0x69052d06 |
|
| 411 |
#define ARM_CPUID_PXA270 0x69054110 |
|
| 412 |
#define ARM_CPUID_PXA270_A0 0x69054110 |
|
| 413 |
#define ARM_CPUID_PXA270_A1 0x69054111 |
|
| 414 |
#define ARM_CPUID_PXA270_B0 0x69054112 |
|
| 415 |
#define ARM_CPUID_PXA270_B1 0x69054113 |
|
| 416 |
#define ARM_CPUID_PXA270_C0 0x69054114 |
|
| 417 |
#define ARM_CPUID_PXA270_C5 0x69054117 |
|
| 418 |
#define ARM_CPUID_ARM1136 0x4117b363 |
|
| 419 |
#define ARM_CPUID_ARM11MPCORE 0x410fb022 |
|
| 420 |
#define ARM_CPUID_CORTEXA8 0x410fc080 |
|
| 421 |
#define ARM_CPUID_CORTEXM3 0x410fc231 |
|
| 422 |
#define ARM_CPUID_ANY 0xffffffff |
|
| 288 | 423 |
|
| 289 | 424 |
#if defined(CONFIG_USER_ONLY) |
| 290 | 425 |
#define TARGET_PAGE_BITS 12 |
| ... | ... | |
| 302 | 437 |
#define cpu_signal_handler cpu_arm_signal_handler |
| 303 | 438 |
#define cpu_list arm_cpu_list |
| 304 | 439 |
|
| 440 |
#define ARM_CPU_SAVE_VERSION 1 |
|
| 441 |
|
|
| 305 | 442 |
/* MMU modes definitions */ |
| 306 | 443 |
#define MMU_MODE0_SUFFIX _kernel |
| 307 | 444 |
#define MMU_MODE1_SUFFIX _user |
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