Revision 9ef39277
| b/target-arm/helper.h | ||
|---|---|---|
| 4 | 4 |
DEF_HELPER_1(sxtb16, i32, i32) |
| 5 | 5 |
DEF_HELPER_1(uxtb16, i32, i32) |
| 6 | 6 |
|
| 7 |
DEF_HELPER_2(add_setq, i32, i32, i32)
|
|
| 8 |
DEF_HELPER_2(add_saturate, i32, i32, i32)
|
|
| 9 |
DEF_HELPER_2(sub_saturate, i32, i32, i32)
|
|
| 10 |
DEF_HELPER_2(add_usaturate, i32, i32, i32)
|
|
| 11 |
DEF_HELPER_2(sub_usaturate, i32, i32, i32)
|
|
| 12 |
DEF_HELPER_1(double_saturate, i32, s32)
|
|
| 7 |
DEF_HELPER_3(add_setq, i32, env, i32, i32)
|
|
| 8 |
DEF_HELPER_3(add_saturate, i32, env, i32, i32)
|
|
| 9 |
DEF_HELPER_3(sub_saturate, i32, env, i32, i32)
|
|
| 10 |
DEF_HELPER_3(add_usaturate, i32, env, i32, i32)
|
|
| 11 |
DEF_HELPER_3(sub_usaturate, i32, env, i32, i32)
|
|
| 12 |
DEF_HELPER_2(double_saturate, i32, env, s32)
|
|
| 13 | 13 |
DEF_HELPER_2(sdiv, s32, s32, s32) |
| 14 | 14 |
DEF_HELPER_2(udiv, i32, i32, i32) |
| 15 | 15 |
DEF_HELPER_1(rbit, i32, i32) |
| ... | ... | |
| 40 | 40 |
PAS_OP(uh) |
| 41 | 41 |
#undef PAS_OP |
| 42 | 42 |
|
| 43 |
DEF_HELPER_2(ssat, i32, i32, i32)
|
|
| 44 |
DEF_HELPER_2(usat, i32, i32, i32)
|
|
| 45 |
DEF_HELPER_2(ssat16, i32, i32, i32)
|
|
| 46 |
DEF_HELPER_2(usat16, i32, i32, i32)
|
|
| 43 |
DEF_HELPER_3(ssat, i32, env, i32, i32)
|
|
| 44 |
DEF_HELPER_3(usat, i32, env, i32, i32)
|
|
| 45 |
DEF_HELPER_3(ssat16, i32, env, i32, i32)
|
|
| 46 |
DEF_HELPER_3(usat16, i32, env, i32, i32)
|
|
| 47 | 47 |
|
| 48 | 48 |
DEF_HELPER_2(usad8, i32, i32, i32) |
| 49 | 49 |
|
| ... | ... | |
| 54 | 54 |
DEF_HELPER_1(wfi, void, env) |
| 55 | 55 |
|
| 56 | 56 |
DEF_HELPER_3(cpsr_write, void, env, i32, i32) |
| 57 |
DEF_HELPER_0(cpsr_read, i32)
|
|
| 57 |
DEF_HELPER_1(cpsr_read, i32, env)
|
|
| 58 | 58 |
|
| 59 | 59 |
DEF_HELPER_3(v7m_msr, void, env, i32, i32) |
| 60 | 60 |
DEF_HELPER_2(v7m_mrs, i32, env, i32) |
| ... | ... | |
| 67 | 67 |
DEF_HELPER_2(get_r13_banked, i32, env, i32) |
| 68 | 68 |
DEF_HELPER_3(set_r13_banked, void, env, i32, i32) |
| 69 | 69 |
|
| 70 |
DEF_HELPER_1(get_user_reg, i32, i32)
|
|
| 70 |
DEF_HELPER_2(get_user_reg, i32, env, i32)
|
|
| 71 | 71 |
DEF_HELPER_3(set_user_reg, void, env, i32, i32) |
| 72 | 72 |
|
| 73 | 73 |
DEF_HELPER_1(vfp_get_fpscr, i32, env) |
| ... | ... | |
| 140 | 140 |
DEF_HELPER_2(rsqrte_f32, f32, f32, env) |
| 141 | 141 |
DEF_HELPER_2(recpe_u32, i32, i32, env) |
| 142 | 142 |
DEF_HELPER_2(rsqrte_u32, i32, i32, env) |
| 143 |
DEF_HELPER_4(neon_tbl, i32, i32, i32, i32, i32)
|
|
| 144 |
|
|
| 145 |
DEF_HELPER_2(add_cc, i32, i32, i32)
|
|
| 146 |
DEF_HELPER_2(adc_cc, i32, i32, i32)
|
|
| 147 |
DEF_HELPER_2(sub_cc, i32, i32, i32)
|
|
| 148 |
DEF_HELPER_2(sbc_cc, i32, i32, i32)
|
|
| 149 |
|
|
| 150 |
DEF_HELPER_2(shl, i32, i32, i32)
|
|
| 151 |
DEF_HELPER_2(shr, i32, i32, i32)
|
|
| 152 |
DEF_HELPER_2(sar, i32, i32, i32)
|
|
| 153 |
DEF_HELPER_2(shl_cc, i32, i32, i32)
|
|
| 154 |
DEF_HELPER_2(shr_cc, i32, i32, i32)
|
|
| 155 |
DEF_HELPER_2(sar_cc, i32, i32, i32)
|
|
| 156 |
DEF_HELPER_2(ror_cc, i32, i32, i32)
|
|
| 143 |
DEF_HELPER_5(neon_tbl, i32, env, i32, i32, i32, i32)
|
|
| 144 |
|
|
| 145 |
DEF_HELPER_3(add_cc, i32, env, i32, i32)
|
|
| 146 |
DEF_HELPER_3(adc_cc, i32, env, i32, i32)
|
|
| 147 |
DEF_HELPER_3(sub_cc, i32, env, i32, i32)
|
|
| 148 |
DEF_HELPER_3(sbc_cc, i32, env, i32, i32)
|
|
| 149 |
|
|
| 150 |
DEF_HELPER_3(shl, i32, env, i32, i32)
|
|
| 151 |
DEF_HELPER_3(shr, i32, env, i32, i32)
|
|
| 152 |
DEF_HELPER_3(sar, i32, env, i32, i32)
|
|
| 153 |
DEF_HELPER_3(shl_cc, i32, env, i32, i32)
|
|
| 154 |
DEF_HELPER_3(shr_cc, i32, env, i32, i32)
|
|
| 155 |
DEF_HELPER_3(sar_cc, i32, env, i32, i32)
|
|
| 156 |
DEF_HELPER_3(ror_cc, i32, env, i32, i32)
|
|
| 157 | 157 |
|
| 158 | 158 |
/* neon_helper.c */ |
| 159 | 159 |
DEF_HELPER_3(neon_qadd_u8, i32, env, i32, i32) |
| b/target-arm/op_helper.c | ||
|---|---|---|
| 29 | 29 |
cpu_loop_exit(env); |
| 30 | 30 |
} |
| 31 | 31 |
|
| 32 |
uint32_t HELPER(neon_tbl)(uint32_t ireg, uint32_t def, |
|
| 32 |
uint32_t HELPER(neon_tbl)(CPUARMState *env, uint32_t ireg, uint32_t def,
|
|
| 33 | 33 |
uint32_t rn, uint32_t maxindex) |
| 34 | 34 |
{
|
| 35 | 35 |
uint32_t val; |
| ... | ... | |
| 101 | 101 |
|
| 102 | 102 |
/* FIXME: Pass an explicit pointer to QF to CPUARMState, and move saturating |
| 103 | 103 |
instructions into helper.c */ |
| 104 |
uint32_t HELPER(add_setq)(uint32_t a, uint32_t b) |
|
| 104 |
uint32_t HELPER(add_setq)(CPUARMState *env, uint32_t a, uint32_t b)
|
|
| 105 | 105 |
{
|
| 106 | 106 |
uint32_t res = a + b; |
| 107 | 107 |
if (((res ^ a) & SIGNBIT) && !((a ^ b) & SIGNBIT)) |
| ... | ... | |
| 109 | 109 |
return res; |
| 110 | 110 |
} |
| 111 | 111 |
|
| 112 |
uint32_t HELPER(add_saturate)(uint32_t a, uint32_t b) |
|
| 112 |
uint32_t HELPER(add_saturate)(CPUARMState *env, uint32_t a, uint32_t b)
|
|
| 113 | 113 |
{
|
| 114 | 114 |
uint32_t res = a + b; |
| 115 | 115 |
if (((res ^ a) & SIGNBIT) && !((a ^ b) & SIGNBIT)) {
|
| ... | ... | |
| 119 | 119 |
return res; |
| 120 | 120 |
} |
| 121 | 121 |
|
| 122 |
uint32_t HELPER(sub_saturate)(uint32_t a, uint32_t b) |
|
| 122 |
uint32_t HELPER(sub_saturate)(CPUARMState *env, uint32_t a, uint32_t b)
|
|
| 123 | 123 |
{
|
| 124 | 124 |
uint32_t res = a - b; |
| 125 | 125 |
if (((res ^ a) & SIGNBIT) && ((a ^ b) & SIGNBIT)) {
|
| ... | ... | |
| 129 | 129 |
return res; |
| 130 | 130 |
} |
| 131 | 131 |
|
| 132 |
uint32_t HELPER(double_saturate)(int32_t val) |
|
| 132 |
uint32_t HELPER(double_saturate)(CPUARMState *env, int32_t val)
|
|
| 133 | 133 |
{
|
| 134 | 134 |
uint32_t res; |
| 135 | 135 |
if (val >= 0x40000000) {
|
| ... | ... | |
| 144 | 144 |
return res; |
| 145 | 145 |
} |
| 146 | 146 |
|
| 147 |
uint32_t HELPER(add_usaturate)(uint32_t a, uint32_t b) |
|
| 147 |
uint32_t HELPER(add_usaturate)(CPUARMState *env, uint32_t a, uint32_t b)
|
|
| 148 | 148 |
{
|
| 149 | 149 |
uint32_t res = a + b; |
| 150 | 150 |
if (res < a) {
|
| ... | ... | |
| 154 | 154 |
return res; |
| 155 | 155 |
} |
| 156 | 156 |
|
| 157 |
uint32_t HELPER(sub_usaturate)(uint32_t a, uint32_t b) |
|
| 157 |
uint32_t HELPER(sub_usaturate)(CPUARMState *env, uint32_t a, uint32_t b)
|
|
| 158 | 158 |
{
|
| 159 | 159 |
uint32_t res = a - b; |
| 160 | 160 |
if (res > a) {
|
| ... | ... | |
| 165 | 165 |
} |
| 166 | 166 |
|
| 167 | 167 |
/* Signed saturation. */ |
| 168 |
static inline uint32_t do_ssat(int32_t val, int shift) |
|
| 168 |
static inline uint32_t do_ssat(CPUARMState *env, int32_t val, int shift)
|
|
| 169 | 169 |
{
|
| 170 | 170 |
int32_t top; |
| 171 | 171 |
uint32_t mask; |
| ... | ... | |
| 183 | 183 |
} |
| 184 | 184 |
|
| 185 | 185 |
/* Unsigned saturation. */ |
| 186 |
static inline uint32_t do_usat(int32_t val, int shift) |
|
| 186 |
static inline uint32_t do_usat(CPUARMState *env, int32_t val, int shift)
|
|
| 187 | 187 |
{
|
| 188 | 188 |
uint32_t max; |
| 189 | 189 |
|
| ... | ... | |
| 199 | 199 |
} |
| 200 | 200 |
|
| 201 | 201 |
/* Signed saturate. */ |
| 202 |
uint32_t HELPER(ssat)(uint32_t x, uint32_t shift) |
|
| 202 |
uint32_t HELPER(ssat)(CPUARMState *env, uint32_t x, uint32_t shift)
|
|
| 203 | 203 |
{
|
| 204 |
return do_ssat(x, shift); |
|
| 204 |
return do_ssat(env, x, shift);
|
|
| 205 | 205 |
} |
| 206 | 206 |
|
| 207 | 207 |
/* Dual halfword signed saturate. */ |
| 208 |
uint32_t HELPER(ssat16)(uint32_t x, uint32_t shift) |
|
| 208 |
uint32_t HELPER(ssat16)(CPUARMState *env, uint32_t x, uint32_t shift)
|
|
| 209 | 209 |
{
|
| 210 | 210 |
uint32_t res; |
| 211 | 211 |
|
| 212 |
res = (uint16_t)do_ssat((int16_t)x, shift); |
|
| 213 |
res |= do_ssat(((int32_t)x) >> 16, shift) << 16; |
|
| 212 |
res = (uint16_t)do_ssat(env, (int16_t)x, shift);
|
|
| 213 |
res |= do_ssat(env, ((int32_t)x) >> 16, shift) << 16;
|
|
| 214 | 214 |
return res; |
| 215 | 215 |
} |
| 216 | 216 |
|
| 217 | 217 |
/* Unsigned saturate. */ |
| 218 |
uint32_t HELPER(usat)(uint32_t x, uint32_t shift) |
|
| 218 |
uint32_t HELPER(usat)(CPUARMState *env, uint32_t x, uint32_t shift)
|
|
| 219 | 219 |
{
|
| 220 |
return do_usat(x, shift); |
|
| 220 |
return do_usat(env, x, shift);
|
|
| 221 | 221 |
} |
| 222 | 222 |
|
| 223 | 223 |
/* Dual halfword unsigned saturate. */ |
| 224 |
uint32_t HELPER(usat16)(uint32_t x, uint32_t shift) |
|
| 224 |
uint32_t HELPER(usat16)(CPUARMState *env, uint32_t x, uint32_t shift)
|
|
| 225 | 225 |
{
|
| 226 | 226 |
uint32_t res; |
| 227 | 227 |
|
| 228 |
res = (uint16_t)do_usat((int16_t)x, shift); |
|
| 229 |
res |= do_usat(((int32_t)x) >> 16, shift) << 16; |
|
| 228 |
res = (uint16_t)do_usat(env, (int16_t)x, shift);
|
|
| 229 |
res |= do_usat(env, ((int32_t)x) >> 16, shift) << 16;
|
|
| 230 | 230 |
return res; |
| 231 | 231 |
} |
| 232 | 232 |
|
| ... | ... | |
| 243 | 243 |
cpu_loop_exit(env); |
| 244 | 244 |
} |
| 245 | 245 |
|
| 246 |
uint32_t HELPER(cpsr_read)(void)
|
|
| 246 |
uint32_t HELPER(cpsr_read)(CPUARMState *env)
|
|
| 247 | 247 |
{
|
| 248 | 248 |
return cpsr_read(env) & ~CPSR_EXEC; |
| 249 | 249 |
} |
| ... | ... | |
| 254 | 254 |
} |
| 255 | 255 |
|
| 256 | 256 |
/* Access to user mode registers from privileged modes. */ |
| 257 |
uint32_t HELPER(get_user_reg)(uint32_t regno) |
|
| 257 |
uint32_t HELPER(get_user_reg)(CPUARMState *env, uint32_t regno)
|
|
| 258 | 258 |
{
|
| 259 | 259 |
uint32_t val; |
| 260 | 260 |
|
| ... | ... | |
| 329 | 329 |
The only way to do that in TCG is a conditional branch, which clobbers |
| 330 | 330 |
all our temporaries. For now implement these as helper functions. */ |
| 331 | 331 |
|
| 332 |
uint32_t HELPER (add_cc)(uint32_t a, uint32_t b) |
|
| 332 |
uint32_t HELPER (add_cc)(CPUARMState *env, uint32_t a, uint32_t b)
|
|
| 333 | 333 |
{
|
| 334 | 334 |
uint32_t result; |
| 335 | 335 |
result = a + b; |
| ... | ... | |
| 339 | 339 |
return result; |
| 340 | 340 |
} |
| 341 | 341 |
|
| 342 |
uint32_t HELPER(adc_cc)(uint32_t a, uint32_t b) |
|
| 342 |
uint32_t HELPER(adc_cc)(CPUARMState *env, uint32_t a, uint32_t b)
|
|
| 343 | 343 |
{
|
| 344 | 344 |
uint32_t result; |
| 345 | 345 |
if (!env->CF) {
|
| ... | ... | |
| 354 | 354 |
return result; |
| 355 | 355 |
} |
| 356 | 356 |
|
| 357 |
uint32_t HELPER(sub_cc)(uint32_t a, uint32_t b) |
|
| 357 |
uint32_t HELPER(sub_cc)(CPUARMState *env, uint32_t a, uint32_t b)
|
|
| 358 | 358 |
{
|
| 359 | 359 |
uint32_t result; |
| 360 | 360 |
result = a - b; |
| ... | ... | |
| 364 | 364 |
return result; |
| 365 | 365 |
} |
| 366 | 366 |
|
| 367 |
uint32_t HELPER(sbc_cc)(uint32_t a, uint32_t b) |
|
| 367 |
uint32_t HELPER(sbc_cc)(CPUARMState *env, uint32_t a, uint32_t b)
|
|
| 368 | 368 |
{
|
| 369 | 369 |
uint32_t result; |
| 370 | 370 |
if (!env->CF) {
|
| ... | ... | |
| 381 | 381 |
|
| 382 | 382 |
/* Similarly for variable shift instructions. */ |
| 383 | 383 |
|
| 384 |
uint32_t HELPER(shl)(uint32_t x, uint32_t i) |
|
| 384 |
uint32_t HELPER(shl)(CPUARMState *env, uint32_t x, uint32_t i)
|
|
| 385 | 385 |
{
|
| 386 | 386 |
int shift = i & 0xff; |
| 387 | 387 |
if (shift >= 32) |
| ... | ... | |
| 389 | 389 |
return x << shift; |
| 390 | 390 |
} |
| 391 | 391 |
|
| 392 |
uint32_t HELPER(shr)(uint32_t x, uint32_t i) |
|
| 392 |
uint32_t HELPER(shr)(CPUARMState *env, uint32_t x, uint32_t i)
|
|
| 393 | 393 |
{
|
| 394 | 394 |
int shift = i & 0xff; |
| 395 | 395 |
if (shift >= 32) |
| ... | ... | |
| 397 | 397 |
return (uint32_t)x >> shift; |
| 398 | 398 |
} |
| 399 | 399 |
|
| 400 |
uint32_t HELPER(sar)(uint32_t x, uint32_t i) |
|
| 400 |
uint32_t HELPER(sar)(CPUARMState *env, uint32_t x, uint32_t i)
|
|
| 401 | 401 |
{
|
| 402 | 402 |
int shift = i & 0xff; |
| 403 | 403 |
if (shift >= 32) |
| ... | ... | |
| 405 | 405 |
return (int32_t)x >> shift; |
| 406 | 406 |
} |
| 407 | 407 |
|
| 408 |
uint32_t HELPER(shl_cc)(uint32_t x, uint32_t i) |
|
| 408 |
uint32_t HELPER(shl_cc)(CPUARMState *env, uint32_t x, uint32_t i)
|
|
| 409 | 409 |
{
|
| 410 | 410 |
int shift = i & 0xff; |
| 411 | 411 |
if (shift >= 32) {
|
| ... | ... | |
| 421 | 421 |
return x; |
| 422 | 422 |
} |
| 423 | 423 |
|
| 424 |
uint32_t HELPER(shr_cc)(uint32_t x, uint32_t i) |
|
| 424 |
uint32_t HELPER(shr_cc)(CPUARMState *env, uint32_t x, uint32_t i)
|
|
| 425 | 425 |
{
|
| 426 | 426 |
int shift = i & 0xff; |
| 427 | 427 |
if (shift >= 32) {
|
| ... | ... | |
| 437 | 437 |
return x; |
| 438 | 438 |
} |
| 439 | 439 |
|
| 440 |
uint32_t HELPER(sar_cc)(uint32_t x, uint32_t i) |
|
| 440 |
uint32_t HELPER(sar_cc)(CPUARMState *env, uint32_t x, uint32_t i)
|
|
| 441 | 441 |
{
|
| 442 | 442 |
int shift = i & 0xff; |
| 443 | 443 |
if (shift >= 32) {
|
| ... | ... | |
| 450 | 450 |
return x; |
| 451 | 451 |
} |
| 452 | 452 |
|
| 453 |
uint32_t HELPER(ror_cc)(uint32_t x, uint32_t i) |
|
| 453 |
uint32_t HELPER(ror_cc)(CPUARMState *env, uint32_t x, uint32_t i)
|
|
| 454 | 454 |
{
|
| 455 | 455 |
int shift1, shift; |
| 456 | 456 |
shift1 = i & 0xff; |
| b/target-arm/translate.c | ||
|---|---|---|
| 490 | 490 |
{
|
| 491 | 491 |
if (flags) {
|
| 492 | 492 |
switch (shiftop) {
|
| 493 |
case 0: gen_helper_shl_cc(var, var, shift); break; |
|
| 494 |
case 1: gen_helper_shr_cc(var, var, shift); break; |
|
| 495 |
case 2: gen_helper_sar_cc(var, var, shift); break; |
|
| 496 |
case 3: gen_helper_ror_cc(var, var, shift); break; |
|
| 493 |
case 0: gen_helper_shl_cc(var, cpu_env, var, shift); break;
|
|
| 494 |
case 1: gen_helper_shr_cc(var, cpu_env, var, shift); break;
|
|
| 495 |
case 2: gen_helper_sar_cc(var, cpu_env, var, shift); break;
|
|
| 496 |
case 3: gen_helper_ror_cc(var, cpu_env, var, shift); break;
|
|
| 497 | 497 |
} |
| 498 | 498 |
} else {
|
| 499 | 499 |
switch (shiftop) {
|
| 500 |
case 0: gen_helper_shl(var, var, shift); break; |
|
| 501 |
case 1: gen_helper_shr(var, var, shift); break; |
|
| 502 |
case 2: gen_helper_sar(var, var, shift); break; |
|
| 500 |
case 0: gen_helper_shl(var, cpu_env, var, shift); break;
|
|
| 501 |
case 1: gen_helper_shr(var, cpu_env, var, shift); break;
|
|
| 502 |
case 2: gen_helper_sar(var, cpu_env, var, shift); break;
|
|
| 503 | 503 |
case 3: tcg_gen_andi_i32(shift, shift, 0x1f); |
| 504 | 504 |
tcg_gen_rotr_i32(var, var, shift); break; |
| 505 | 505 |
} |
| ... | ... | |
| 6121 | 6121 |
tmp2 = neon_load_reg(rm, 0); |
| 6122 | 6122 |
tmp4 = tcg_const_i32(rn); |
| 6123 | 6123 |
tmp5 = tcg_const_i32(n); |
| 6124 |
gen_helper_neon_tbl(tmp2, tmp2, tmp, tmp4, tmp5); |
|
| 6124 |
gen_helper_neon_tbl(tmp2, cpu_env, tmp2, tmp, tmp4, tmp5);
|
|
| 6125 | 6125 |
tcg_temp_free_i32(tmp); |
| 6126 | 6126 |
if (insn & (1 << 6)) {
|
| 6127 | 6127 |
tmp = neon_load_reg(rd, 1); |
| ... | ... | |
| 6130 | 6130 |
tcg_gen_movi_i32(tmp, 0); |
| 6131 | 6131 |
} |
| 6132 | 6132 |
tmp3 = neon_load_reg(rm, 1); |
| 6133 |
gen_helper_neon_tbl(tmp3, tmp3, tmp, tmp4, tmp5); |
|
| 6133 |
gen_helper_neon_tbl(tmp3, cpu_env, tmp3, tmp, tmp4, tmp5);
|
|
| 6134 | 6134 |
tcg_temp_free_i32(tmp5); |
| 6135 | 6135 |
tcg_temp_free_i32(tmp4); |
| 6136 | 6136 |
neon_store_reg(rd, 0, tmp2); |
| ... | ... | |
| 6818 | 6818 |
tmp = load_cpu_field(spsr); |
| 6819 | 6819 |
} else {
|
| 6820 | 6820 |
tmp = tcg_temp_new_i32(); |
| 6821 |
gen_helper_cpsr_read(tmp); |
|
| 6821 |
gen_helper_cpsr_read(tmp, cpu_env);
|
|
| 6822 | 6822 |
} |
| 6823 | 6823 |
store_reg(s, rd, tmp); |
| 6824 | 6824 |
} |
| ... | ... | |
| 6869 | 6869 |
tmp = load_reg(s, rm); |
| 6870 | 6870 |
tmp2 = load_reg(s, rn); |
| 6871 | 6871 |
if (op1 & 2) |
| 6872 |
gen_helper_double_saturate(tmp2, tmp2); |
|
| 6872 |
gen_helper_double_saturate(tmp2, cpu_env, tmp2);
|
|
| 6873 | 6873 |
if (op1 & 1) |
| 6874 |
gen_helper_sub_saturate(tmp, tmp, tmp2); |
|
| 6874 |
gen_helper_sub_saturate(tmp, cpu_env, tmp, tmp2);
|
|
| 6875 | 6875 |
else |
| 6876 |
gen_helper_add_saturate(tmp, tmp, tmp2); |
|
| 6876 |
gen_helper_add_saturate(tmp, cpu_env, tmp, tmp2);
|
|
| 6877 | 6877 |
tcg_temp_free_i32(tmp2); |
| 6878 | 6878 |
store_reg(s, rd, tmp); |
| 6879 | 6879 |
break; |
| ... | ... | |
| 6911 | 6911 |
tcg_temp_free_i64(tmp64); |
| 6912 | 6912 |
if ((sh & 2) == 0) {
|
| 6913 | 6913 |
tmp2 = load_reg(s, rn); |
| 6914 |
gen_helper_add_setq(tmp, tmp, tmp2); |
|
| 6914 |
gen_helper_add_setq(tmp, cpu_env, tmp, tmp2);
|
|
| 6915 | 6915 |
tcg_temp_free_i32(tmp2); |
| 6916 | 6916 |
} |
| 6917 | 6917 |
store_reg(s, rd, tmp); |
| ... | ... | |
| 6931 | 6931 |
} else {
|
| 6932 | 6932 |
if (op1 == 0) {
|
| 6933 | 6933 |
tmp2 = load_reg(s, rn); |
| 6934 |
gen_helper_add_setq(tmp, tmp, tmp2); |
|
| 6934 |
gen_helper_add_setq(tmp, cpu_env, tmp, tmp2);
|
|
| 6935 | 6935 |
tcg_temp_free_i32(tmp2); |
| 6936 | 6936 |
} |
| 6937 | 6937 |
store_reg(s, rd, tmp); |
| ... | ... | |
| 7005 | 7005 |
if (IS_USER(s)) {
|
| 7006 | 7006 |
goto illegal_op; |
| 7007 | 7007 |
} |
| 7008 |
gen_helper_sub_cc(tmp, tmp, tmp2); |
|
| 7008 |
gen_helper_sub_cc(tmp, cpu_env, tmp, tmp2);
|
|
| 7009 | 7009 |
gen_exception_return(s, tmp); |
| 7010 | 7010 |
} else {
|
| 7011 | 7011 |
if (set_cc) {
|
| 7012 |
gen_helper_sub_cc(tmp, tmp, tmp2); |
|
| 7012 |
gen_helper_sub_cc(tmp, cpu_env, tmp, tmp2);
|
|
| 7013 | 7013 |
} else {
|
| 7014 | 7014 |
tcg_gen_sub_i32(tmp, tmp, tmp2); |
| 7015 | 7015 |
} |
| ... | ... | |
| 7018 | 7018 |
break; |
| 7019 | 7019 |
case 0x03: |
| 7020 | 7020 |
if (set_cc) {
|
| 7021 |
gen_helper_sub_cc(tmp, tmp2, tmp); |
|
| 7021 |
gen_helper_sub_cc(tmp, cpu_env, tmp2, tmp);
|
|
| 7022 | 7022 |
} else {
|
| 7023 | 7023 |
tcg_gen_sub_i32(tmp, tmp2, tmp); |
| 7024 | 7024 |
} |
| ... | ... | |
| 7026 | 7026 |
break; |
| 7027 | 7027 |
case 0x04: |
| 7028 | 7028 |
if (set_cc) {
|
| 7029 |
gen_helper_add_cc(tmp, tmp, tmp2); |
|
| 7029 |
gen_helper_add_cc(tmp, cpu_env, tmp, tmp2);
|
|
| 7030 | 7030 |
} else {
|
| 7031 | 7031 |
tcg_gen_add_i32(tmp, tmp, tmp2); |
| 7032 | 7032 |
} |
| ... | ... | |
| 7034 | 7034 |
break; |
| 7035 | 7035 |
case 0x05: |
| 7036 | 7036 |
if (set_cc) {
|
| 7037 |
gen_helper_adc_cc(tmp, tmp, tmp2); |
|
| 7037 |
gen_helper_adc_cc(tmp, cpu_env, tmp, tmp2);
|
|
| 7038 | 7038 |
} else {
|
| 7039 | 7039 |
gen_add_carry(tmp, tmp, tmp2); |
| 7040 | 7040 |
} |
| ... | ... | |
| 7042 | 7042 |
break; |
| 7043 | 7043 |
case 0x06: |
| 7044 | 7044 |
if (set_cc) {
|
| 7045 |
gen_helper_sbc_cc(tmp, tmp, tmp2); |
|
| 7045 |
gen_helper_sbc_cc(tmp, cpu_env, tmp, tmp2);
|
|
| 7046 | 7046 |
} else {
|
| 7047 | 7047 |
gen_sub_carry(tmp, tmp, tmp2); |
| 7048 | 7048 |
} |
| ... | ... | |
| 7050 | 7050 |
break; |
| 7051 | 7051 |
case 0x07: |
| 7052 | 7052 |
if (set_cc) {
|
| 7053 |
gen_helper_sbc_cc(tmp, tmp2, tmp); |
|
| 7053 |
gen_helper_sbc_cc(tmp, cpu_env, tmp2, tmp);
|
|
| 7054 | 7054 |
} else {
|
| 7055 | 7055 |
gen_sub_carry(tmp, tmp2, tmp); |
| 7056 | 7056 |
} |
| ... | ... | |
| 7072 | 7072 |
break; |
| 7073 | 7073 |
case 0x0a: |
| 7074 | 7074 |
if (set_cc) {
|
| 7075 |
gen_helper_sub_cc(tmp, tmp, tmp2); |
|
| 7075 |
gen_helper_sub_cc(tmp, cpu_env, tmp, tmp2);
|
|
| 7076 | 7076 |
} |
| 7077 | 7077 |
tcg_temp_free_i32(tmp); |
| 7078 | 7078 |
break; |
| 7079 | 7079 |
case 0x0b: |
| 7080 | 7080 |
if (set_cc) {
|
| 7081 |
gen_helper_add_cc(tmp, tmp, tmp2); |
|
| 7081 |
gen_helper_add_cc(tmp, cpu_env, tmp, tmp2);
|
|
| 7082 | 7082 |
} |
| 7083 | 7083 |
tcg_temp_free_i32(tmp); |
| 7084 | 7084 |
break; |
| ... | ... | |
| 7395 | 7395 |
sh = (insn >> 16) & 0x1f; |
| 7396 | 7396 |
tmp2 = tcg_const_i32(sh); |
| 7397 | 7397 |
if (insn & (1 << 22)) |
| 7398 |
gen_helper_usat(tmp, tmp, tmp2); |
|
| 7398 |
gen_helper_usat(tmp, cpu_env, tmp, tmp2);
|
|
| 7399 | 7399 |
else |
| 7400 |
gen_helper_ssat(tmp, tmp, tmp2); |
|
| 7400 |
gen_helper_ssat(tmp, cpu_env, tmp, tmp2);
|
|
| 7401 | 7401 |
tcg_temp_free_i32(tmp2); |
| 7402 | 7402 |
store_reg(s, rd, tmp); |
| 7403 | 7403 |
} else if ((insn & 0x00300fe0) == 0x00200f20) {
|
| ... | ... | |
| 7406 | 7406 |
sh = (insn >> 16) & 0x1f; |
| 7407 | 7407 |
tmp2 = tcg_const_i32(sh); |
| 7408 | 7408 |
if (insn & (1 << 22)) |
| 7409 |
gen_helper_usat16(tmp, tmp, tmp2); |
|
| 7409 |
gen_helper_usat16(tmp, cpu_env, tmp, tmp2);
|
|
| 7410 | 7410 |
else |
| 7411 |
gen_helper_ssat16(tmp, tmp, tmp2); |
|
| 7411 |
gen_helper_ssat16(tmp, cpu_env, tmp, tmp2);
|
|
| 7412 | 7412 |
tcg_temp_free_i32(tmp2); |
| 7413 | 7413 |
store_reg(s, rd, tmp); |
| 7414 | 7414 |
} else if ((insn & 0x00700fe0) == 0x00000fa0) {
|
| ... | ... | |
| 7518 | 7518 |
* however it may overflow considered as a signed |
| 7519 | 7519 |
* operation, in which case we must set the Q flag. |
| 7520 | 7520 |
*/ |
| 7521 |
gen_helper_add_setq(tmp, tmp, tmp2); |
|
| 7521 |
gen_helper_add_setq(tmp, cpu_env, tmp, tmp2);
|
|
| 7522 | 7522 |
} |
| 7523 | 7523 |
tcg_temp_free_i32(tmp2); |
| 7524 | 7524 |
if (insn & (1 << 22)) {
|
| ... | ... | |
| 7534 | 7534 |
if (rd != 15) |
| 7535 | 7535 |
{
|
| 7536 | 7536 |
tmp2 = load_reg(s, rd); |
| 7537 |
gen_helper_add_setq(tmp, tmp, tmp2); |
|
| 7537 |
gen_helper_add_setq(tmp, cpu_env, tmp, tmp2);
|
|
| 7538 | 7538 |
tcg_temp_free_i32(tmp2); |
| 7539 | 7539 |
} |
| 7540 | 7540 |
store_reg(s, rn, tmp); |
| ... | ... | |
| 7738 | 7738 |
} else if (user) {
|
| 7739 | 7739 |
tmp = tcg_temp_new_i32(); |
| 7740 | 7740 |
tmp2 = tcg_const_i32(i); |
| 7741 |
gen_helper_get_user_reg(tmp, tmp2); |
|
| 7741 |
gen_helper_get_user_reg(tmp, cpu_env, tmp2);
|
|
| 7742 | 7742 |
tcg_temp_free_i32(tmp2); |
| 7743 | 7743 |
} else {
|
| 7744 | 7744 |
tmp = load_reg(s, i); |
| ... | ... | |
| 7865 | 7865 |
break; |
| 7866 | 7866 |
case 8: /* add */ |
| 7867 | 7867 |
if (conds) |
| 7868 |
gen_helper_add_cc(t0, t0, t1); |
|
| 7868 |
gen_helper_add_cc(t0, cpu_env, t0, t1);
|
|
| 7869 | 7869 |
else |
| 7870 | 7870 |
tcg_gen_add_i32(t0, t0, t1); |
| 7871 | 7871 |
break; |
| 7872 | 7872 |
case 10: /* adc */ |
| 7873 | 7873 |
if (conds) |
| 7874 |
gen_helper_adc_cc(t0, t0, t1); |
|
| 7874 |
gen_helper_adc_cc(t0, cpu_env, t0, t1);
|
|
| 7875 | 7875 |
else |
| 7876 | 7876 |
gen_adc(t0, t1); |
| 7877 | 7877 |
break; |
| 7878 | 7878 |
case 11: /* sbc */ |
| 7879 | 7879 |
if (conds) |
| 7880 |
gen_helper_sbc_cc(t0, t0, t1); |
|
| 7880 |
gen_helper_sbc_cc(t0, cpu_env, t0, t1);
|
|
| 7881 | 7881 |
else |
| 7882 | 7882 |
gen_sub_carry(t0, t0, t1); |
| 7883 | 7883 |
break; |
| 7884 | 7884 |
case 13: /* sub */ |
| 7885 | 7885 |
if (conds) |
| 7886 |
gen_helper_sub_cc(t0, t0, t1); |
|
| 7886 |
gen_helper_sub_cc(t0, cpu_env, t0, t1);
|
|
| 7887 | 7887 |
else |
| 7888 | 7888 |
tcg_gen_sub_i32(t0, t0, t1); |
| 7889 | 7889 |
break; |
| 7890 | 7890 |
case 14: /* rsb */ |
| 7891 | 7891 |
if (conds) |
| 7892 |
gen_helper_sub_cc(t0, t1, t0); |
|
| 7892 |
gen_helper_sub_cc(t0, cpu_env, t1, t0);
|
|
| 7893 | 7893 |
else |
| 7894 | 7894 |
tcg_gen_sub_i32(t0, t1, t0); |
| 7895 | 7895 |
break; |
| ... | ... | |
| 8111 | 8111 |
gen_st32(tmp, addr, 0); |
| 8112 | 8112 |
tcg_gen_addi_i32(addr, addr, 4); |
| 8113 | 8113 |
tmp = tcg_temp_new_i32(); |
| 8114 |
gen_helper_cpsr_read(tmp); |
|
| 8114 |
gen_helper_cpsr_read(tmp, cpu_env);
|
|
| 8115 | 8115 |
gen_st32(tmp, addr, 0); |
| 8116 | 8116 |
if (insn & (1 << 21)) {
|
| 8117 | 8117 |
if ((insn & (1 << 24)) == 0) {
|
| ... | ... | |
| 8293 | 8293 |
tmp = load_reg(s, rn); |
| 8294 | 8294 |
tmp2 = load_reg(s, rm); |
| 8295 | 8295 |
if (op & 1) |
| 8296 |
gen_helper_double_saturate(tmp, tmp); |
|
| 8296 |
gen_helper_double_saturate(tmp, cpu_env, tmp);
|
|
| 8297 | 8297 |
if (op & 2) |
| 8298 |
gen_helper_sub_saturate(tmp, tmp2, tmp); |
|
| 8298 |
gen_helper_sub_saturate(tmp, cpu_env, tmp2, tmp);
|
|
| 8299 | 8299 |
else |
| 8300 |
gen_helper_add_saturate(tmp, tmp, tmp2); |
|
| 8300 |
gen_helper_add_saturate(tmp, cpu_env, tmp, tmp2);
|
|
| 8301 | 8301 |
tcg_temp_free_i32(tmp2); |
| 8302 | 8302 |
} else {
|
| 8303 | 8303 |
tmp = load_reg(s, rn); |
| ... | ... | |
| 8353 | 8353 |
tcg_temp_free_i32(tmp2); |
| 8354 | 8354 |
if (rs != 15) {
|
| 8355 | 8355 |
tmp2 = load_reg(s, rs); |
| 8356 |
gen_helper_add_setq(tmp, tmp, tmp2); |
|
| 8356 |
gen_helper_add_setq(tmp, cpu_env, tmp, tmp2);
|
|
| 8357 | 8357 |
tcg_temp_free_i32(tmp2); |
| 8358 | 8358 |
} |
| 8359 | 8359 |
break; |
| ... | ... | |
| 8370 | 8370 |
* however it may overflow considered as a signed |
| 8371 | 8371 |
* operation, in which case we must set the Q flag. |
| 8372 | 8372 |
*/ |
| 8373 |
gen_helper_add_setq(tmp, tmp, tmp2); |
|
| 8373 |
gen_helper_add_setq(tmp, cpu_env, tmp, tmp2);
|
|
| 8374 | 8374 |
} |
| 8375 | 8375 |
tcg_temp_free_i32(tmp2); |
| 8376 | 8376 |
if (rs != 15) |
| 8377 | 8377 |
{
|
| 8378 | 8378 |
tmp2 = load_reg(s, rs); |
| 8379 |
gen_helper_add_setq(tmp, tmp, tmp2); |
|
| 8379 |
gen_helper_add_setq(tmp, cpu_env, tmp, tmp2);
|
|
| 8380 | 8380 |
tcg_temp_free_i32(tmp2); |
| 8381 | 8381 |
} |
| 8382 | 8382 |
break; |
| ... | ... | |
| 8393 | 8393 |
if (rs != 15) |
| 8394 | 8394 |
{
|
| 8395 | 8395 |
tmp2 = load_reg(s, rs); |
| 8396 |
gen_helper_add_setq(tmp, tmp, tmp2); |
|
| 8396 |
gen_helper_add_setq(tmp, cpu_env, tmp, tmp2);
|
|
| 8397 | 8397 |
tcg_temp_free_i32(tmp2); |
| 8398 | 8398 |
} |
| 8399 | 8399 |
break; |
| ... | ... | |
| 8632 | 8632 |
gen_helper_v7m_mrs(tmp, cpu_env, addr); |
| 8633 | 8633 |
tcg_temp_free_i32(addr); |
| 8634 | 8634 |
} else {
|
| 8635 |
gen_helper_cpsr_read(tmp); |
|
| 8635 |
gen_helper_cpsr_read(tmp, cpu_env);
|
|
| 8636 | 8636 |
} |
| 8637 | 8637 |
store_reg(s, rd, tmp); |
| 8638 | 8638 |
break; |
| ... | ... | |
| 8721 | 8721 |
if (op & 4) {
|
| 8722 | 8722 |
/* Unsigned. */ |
| 8723 | 8723 |
if ((op & 1) && shift == 0) |
| 8724 |
gen_helper_usat16(tmp, tmp, tmp2); |
|
| 8724 |
gen_helper_usat16(tmp, cpu_env, tmp, tmp2);
|
|
| 8725 | 8725 |
else |
| 8726 |
gen_helper_usat(tmp, tmp, tmp2); |
|
| 8726 |
gen_helper_usat(tmp, cpu_env, tmp, tmp2);
|
|
| 8727 | 8727 |
} else {
|
| 8728 | 8728 |
/* Signed. */ |
| 8729 | 8729 |
if ((op & 1) && shift == 0) |
| 8730 |
gen_helper_ssat16(tmp, tmp, tmp2); |
|
| 8730 |
gen_helper_ssat16(tmp, cpu_env, tmp, tmp2);
|
|
| 8731 | 8731 |
else |
| 8732 |
gen_helper_ssat(tmp, tmp, tmp2); |
|
| 8732 |
gen_helper_ssat(tmp, cpu_env, tmp, tmp2);
|
|
| 8733 | 8733 |
} |
| 8734 | 8734 |
tcg_temp_free_i32(tmp2); |
| 8735 | 8735 |
break; |
| ... | ... | |
| 9017 | 9017 |
if (s->condexec_mask) |
| 9018 | 9018 |
tcg_gen_sub_i32(tmp, tmp, tmp2); |
| 9019 | 9019 |
else |
| 9020 |
gen_helper_sub_cc(tmp, tmp, tmp2); |
|
| 9020 |
gen_helper_sub_cc(tmp, cpu_env, tmp, tmp2);
|
|
| 9021 | 9021 |
} else {
|
| 9022 | 9022 |
if (s->condexec_mask) |
| 9023 | 9023 |
tcg_gen_add_i32(tmp, tmp, tmp2); |
| 9024 | 9024 |
else |
| 9025 |
gen_helper_add_cc(tmp, tmp, tmp2); |
|
| 9025 |
gen_helper_add_cc(tmp, cpu_env, tmp, tmp2);
|
|
| 9026 | 9026 |
} |
| 9027 | 9027 |
tcg_temp_free_i32(tmp2); |
| 9028 | 9028 |
store_reg(s, rd, tmp); |
| ... | ... | |
| 9053 | 9053 |
tcg_gen_movi_i32(tmp2, insn & 0xff); |
| 9054 | 9054 |
switch (op) {
|
| 9055 | 9055 |
case 1: /* cmp */ |
| 9056 |
gen_helper_sub_cc(tmp, tmp, tmp2); |
|
| 9056 |
gen_helper_sub_cc(tmp, cpu_env, tmp, tmp2);
|
|
| 9057 | 9057 |
tcg_temp_free_i32(tmp); |
| 9058 | 9058 |
tcg_temp_free_i32(tmp2); |
| 9059 | 9059 |
break; |
| ... | ... | |
| 9061 | 9061 |
if (s->condexec_mask) |
| 9062 | 9062 |
tcg_gen_add_i32(tmp, tmp, tmp2); |
| 9063 | 9063 |
else |
| 9064 |
gen_helper_add_cc(tmp, tmp, tmp2); |
|
| 9064 |
gen_helper_add_cc(tmp, cpu_env, tmp, tmp2);
|
|
| 9065 | 9065 |
tcg_temp_free_i32(tmp2); |
| 9066 | 9066 |
store_reg(s, rd, tmp); |
| 9067 | 9067 |
break; |
| ... | ... | |
| 9069 | 9069 |
if (s->condexec_mask) |
| 9070 | 9070 |
tcg_gen_sub_i32(tmp, tmp, tmp2); |
| 9071 | 9071 |
else |
| 9072 |
gen_helper_sub_cc(tmp, tmp, tmp2); |
|
| 9072 |
gen_helper_sub_cc(tmp, cpu_env, tmp, tmp2);
|
|
| 9073 | 9073 |
tcg_temp_free_i32(tmp2); |
| 9074 | 9074 |
store_reg(s, rd, tmp); |
| 9075 | 9075 |
break; |
| ... | ... | |
| 9105 | 9105 |
case 1: /* cmp */ |
| 9106 | 9106 |
tmp = load_reg(s, rd); |
| 9107 | 9107 |
tmp2 = load_reg(s, rm); |
| 9108 |
gen_helper_sub_cc(tmp, tmp, tmp2); |
|
| 9108 |
gen_helper_sub_cc(tmp, cpu_env, tmp, tmp2);
|
|
| 9109 | 9109 |
tcg_temp_free_i32(tmp2); |
| 9110 | 9110 |
tcg_temp_free_i32(tmp); |
| 9111 | 9111 |
break; |
| ... | ... | |
| 9166 | 9166 |
break; |
| 9167 | 9167 |
case 0x2: /* lsl */ |
| 9168 | 9168 |
if (s->condexec_mask) {
|
| 9169 |
gen_helper_shl(tmp2, tmp2, tmp); |
|
| 9169 |
gen_helper_shl(tmp2, cpu_env, tmp2, tmp);
|
|
| 9170 | 9170 |
} else {
|
| 9171 |
gen_helper_shl_cc(tmp2, tmp2, tmp); |
|
| 9171 |
gen_helper_shl_cc(tmp2, cpu_env, tmp2, tmp);
|
|
| 9172 | 9172 |
gen_logic_CC(tmp2); |
| 9173 | 9173 |
} |
| 9174 | 9174 |
break; |
| 9175 | 9175 |
case 0x3: /* lsr */ |
| 9176 | 9176 |
if (s->condexec_mask) {
|
| 9177 |
gen_helper_shr(tmp2, tmp2, tmp); |
|
| 9177 |
gen_helper_shr(tmp2, cpu_env, tmp2, tmp);
|
|
| 9178 | 9178 |
} else {
|
| 9179 |
gen_helper_shr_cc(tmp2, tmp2, tmp); |
|
| 9179 |
gen_helper_shr_cc(tmp2, cpu_env, tmp2, tmp);
|
|
| 9180 | 9180 |
gen_logic_CC(tmp2); |
| 9181 | 9181 |
} |
| 9182 | 9182 |
break; |
| 9183 | 9183 |
case 0x4: /* asr */ |
| 9184 | 9184 |
if (s->condexec_mask) {
|
| 9185 |
gen_helper_sar(tmp2, tmp2, tmp); |
|
| 9185 |
gen_helper_sar(tmp2, cpu_env, tmp2, tmp);
|
|
| 9186 | 9186 |
} else {
|
| 9187 |
gen_helper_sar_cc(tmp2, tmp2, tmp); |
|
| 9187 |
gen_helper_sar_cc(tmp2, cpu_env, tmp2, tmp);
|
|
| 9188 | 9188 |
gen_logic_CC(tmp2); |
| 9189 | 9189 |
} |
| 9190 | 9190 |
break; |
| ... | ... | |
| 9192 | 9192 |
if (s->condexec_mask) |
| 9193 | 9193 |
gen_adc(tmp, tmp2); |
| 9194 | 9194 |
else |
| 9195 |
gen_helper_adc_cc(tmp, tmp, tmp2); |
|
| 9195 |
gen_helper_adc_cc(tmp, cpu_env, tmp, tmp2);
|
|
| 9196 | 9196 |
break; |
| 9197 | 9197 |
case 0x6: /* sbc */ |
| 9198 | 9198 |
if (s->condexec_mask) |
| 9199 | 9199 |
gen_sub_carry(tmp, tmp, tmp2); |
| 9200 | 9200 |
else |
| 9201 |
gen_helper_sbc_cc(tmp, tmp, tmp2); |
|
| 9201 |
gen_helper_sbc_cc(tmp, cpu_env, tmp, tmp2);
|
|
| 9202 | 9202 |
break; |
| 9203 | 9203 |
case 0x7: /* ror */ |
| 9204 | 9204 |
if (s->condexec_mask) {
|
| 9205 | 9205 |
tcg_gen_andi_i32(tmp, tmp, 0x1f); |
| 9206 | 9206 |
tcg_gen_rotr_i32(tmp2, tmp2, tmp); |
| 9207 | 9207 |
} else {
|
| 9208 |
gen_helper_ror_cc(tmp2, tmp2, tmp); |
|
| 9208 |
gen_helper_ror_cc(tmp2, cpu_env, tmp2, tmp);
|
|
| 9209 | 9209 |
gen_logic_CC(tmp2); |
| 9210 | 9210 |
} |
| 9211 | 9211 |
break; |
| ... | ... | |
| 9218 | 9218 |
if (s->condexec_mask) |
| 9219 | 9219 |
tcg_gen_neg_i32(tmp, tmp2); |
| 9220 | 9220 |
else |
| 9221 |
gen_helper_sub_cc(tmp, tmp, tmp2); |
|
| 9221 |
gen_helper_sub_cc(tmp, cpu_env, tmp, tmp2);
|
|
| 9222 | 9222 |
break; |
| 9223 | 9223 |
case 0xa: /* cmp */ |
| 9224 |
gen_helper_sub_cc(tmp, tmp, tmp2); |
|
| 9224 |
gen_helper_sub_cc(tmp, cpu_env, tmp, tmp2);
|
|
| 9225 | 9225 |
rd = 16; |
| 9226 | 9226 |
break; |
| 9227 | 9227 |
case 0xb: /* cmn */ |
| 9228 |
gen_helper_add_cc(tmp, tmp, tmp2); |
|
| 9228 |
gen_helper_add_cc(tmp, cpu_env, tmp, tmp2);
|
|
| 9229 | 9229 |
rd = 16; |
| 9230 | 9230 |
break; |
| 9231 | 9231 |
case 0xc: /* orr */ |
Also available in: Unified diff