root / hw / sh_pci.c @ 9fdf0c29
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1 | 1e5459a3 | balrog | /*
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2 | 1e5459a3 | balrog | * SuperH on-chip PCIC emulation.
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3 | 1e5459a3 | balrog | *
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4 | 1e5459a3 | balrog | * Copyright (c) 2008 Takashi YOSHII
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5 | 1e5459a3 | balrog | *
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6 | 1e5459a3 | balrog | * Permission is hereby granted, free of charge, to any person obtaining a copy
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7 | 1e5459a3 | balrog | * of this software and associated documentation files (the "Software"), to deal
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8 | 1e5459a3 | balrog | * in the Software without restriction, including without limitation the rights
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9 | 1e5459a3 | balrog | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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10 | 1e5459a3 | balrog | * copies of the Software, and to permit persons to whom the Software is
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11 | 1e5459a3 | balrog | * furnished to do so, subject to the following conditions:
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12 | 1e5459a3 | balrog | *
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13 | 1e5459a3 | balrog | * The above copyright notice and this permission notice shall be included in
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14 | 1e5459a3 | balrog | * all copies or substantial portions of the Software.
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15 | 1e5459a3 | balrog | *
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16 | 1e5459a3 | balrog | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 | 1e5459a3 | balrog | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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18 | 1e5459a3 | balrog | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 | 1e5459a3 | balrog | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 | 1e5459a3 | balrog | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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21 | 1e5459a3 | balrog | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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22 | 1e5459a3 | balrog | * THE SOFTWARE.
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23 | 1e5459a3 | balrog | */
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24 | cf154394 | Aurelien Jarno | #include "sysbus.h" |
25 | 1e5459a3 | balrog | #include "sh.h" |
26 | 1e5459a3 | balrog | #include "pci.h" |
27 | b6243d99 | Isaku Yamahata | #include "pci_host.h" |
28 | 1e5459a3 | balrog | #include "bswap.h" |
29 | 1e5459a3 | balrog | |
30 | cf154394 | Aurelien Jarno | typedef struct SHPCIState { |
31 | cf154394 | Aurelien Jarno | SysBusDevice busdev; |
32 | 1e5459a3 | balrog | PCIBus *bus; |
33 | 1e5459a3 | balrog | PCIDevice *dev; |
34 | cf154394 | Aurelien Jarno | qemu_irq irq[4];
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35 | cf154394 | Aurelien Jarno | int memconfig;
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36 | 1e5459a3 | balrog | uint32_t par; |
37 | 1e5459a3 | balrog | uint32_t mbr; |
38 | 1e5459a3 | balrog | uint32_t iobr; |
39 | cf154394 | Aurelien Jarno | } SHPCIState; |
40 | 1e5459a3 | balrog | |
41 | c227f099 | Anthony Liguori | static void sh_pci_reg_write (void *p, target_phys_addr_t addr, uint32_t val) |
42 | 1e5459a3 | balrog | { |
43 | cf154394 | Aurelien Jarno | SHPCIState *pcic = p; |
44 | 1e5459a3 | balrog | switch(addr) {
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45 | 1e5459a3 | balrog | case 0 ... 0xfc: |
46 | 1e5459a3 | balrog | cpu_to_le32w((uint32_t*)(pcic->dev->config + addr), val); |
47 | 1e5459a3 | balrog | break;
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48 | 1e5459a3 | balrog | case 0x1c0: |
49 | 1e5459a3 | balrog | pcic->par = val; |
50 | 1e5459a3 | balrog | break;
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51 | 1e5459a3 | balrog | case 0x1c4: |
52 | 5ba9e952 | Aurelien Jarno | pcic->mbr = val & 0xff000001;
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53 | 1e5459a3 | balrog | break;
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54 | 1e5459a3 | balrog | case 0x1c8: |
55 | 5ba9e952 | Aurelien Jarno | if ((val & 0xfffc0000) != (pcic->iobr & 0xfffc0000)) { |
56 | 5ba9e952 | Aurelien Jarno | cpu_register_physical_memory(pcic->iobr & 0xfffc0000, 0x40000, |
57 | 5ba9e952 | Aurelien Jarno | IO_MEM_UNASSIGNED); |
58 | 5ba9e952 | Aurelien Jarno | pcic->iobr = val & 0xfffc0001;
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59 | 968d683c | Alexander Graf | isa_mmio_init(pcic->iobr & 0xfffc0000, 0x40000); |
60 | 5ba9e952 | Aurelien Jarno | } |
61 | 1e5459a3 | balrog | break;
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62 | 1e5459a3 | balrog | case 0x220: |
63 | 1e5459a3 | balrog | pci_data_write(pcic->bus, pcic->par, val, 4);
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64 | 1e5459a3 | balrog | break;
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65 | 1e5459a3 | balrog | } |
66 | 1e5459a3 | balrog | } |
67 | 1e5459a3 | balrog | |
68 | c227f099 | Anthony Liguori | static uint32_t sh_pci_reg_read (void *p, target_phys_addr_t addr) |
69 | 1e5459a3 | balrog | { |
70 | cf154394 | Aurelien Jarno | SHPCIState *pcic = p; |
71 | 1e5459a3 | balrog | switch(addr) {
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72 | 1e5459a3 | balrog | case 0 ... 0xfc: |
73 | 1e5459a3 | balrog | return le32_to_cpup((uint32_t*)(pcic->dev->config + addr));
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74 | 1e5459a3 | balrog | case 0x1c0: |
75 | 1e5459a3 | balrog | return pcic->par;
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76 | 5ba9e952 | Aurelien Jarno | case 0x1c4: |
77 | 5ba9e952 | Aurelien Jarno | return pcic->mbr;
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78 | 5ba9e952 | Aurelien Jarno | case 0x1c8: |
79 | 5ba9e952 | Aurelien Jarno | return pcic->iobr;
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80 | 1e5459a3 | balrog | case 0x220: |
81 | 1e5459a3 | balrog | return pci_data_read(pcic->bus, pcic->par, 4); |
82 | 1e5459a3 | balrog | } |
83 | 1e5459a3 | balrog | return 0; |
84 | 1e5459a3 | balrog | } |
85 | 1e5459a3 | balrog | |
86 | 1e5459a3 | balrog | typedef struct { |
87 | d60efc6b | Blue Swirl | CPUReadMemoryFunc * const r[3]; |
88 | d60efc6b | Blue Swirl | CPUWriteMemoryFunc * const w[3]; |
89 | 1e5459a3 | balrog | } MemOp; |
90 | 1e5459a3 | balrog | |
91 | 1e5459a3 | balrog | static MemOp sh_pci_reg = {
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92 | 1e5459a3 | balrog | { NULL, NULL, sh_pci_reg_read }, |
93 | 1e5459a3 | balrog | { NULL, NULL, sh_pci_reg_write }, |
94 | 1e5459a3 | balrog | }; |
95 | 1e5459a3 | balrog | |
96 | cf154394 | Aurelien Jarno | static int sh_pci_map_irq(PCIDevice *d, int irq_num) |
97 | cf154394 | Aurelien Jarno | { |
98 | cf154394 | Aurelien Jarno | return (d->devfn >> 3); |
99 | cf154394 | Aurelien Jarno | } |
100 | cf154394 | Aurelien Jarno | |
101 | cf154394 | Aurelien Jarno | static void sh_pci_set_irq(void *opaque, int irq_num, int level) |
102 | cf154394 | Aurelien Jarno | { |
103 | cf154394 | Aurelien Jarno | qemu_irq *pic = opaque; |
104 | cf154394 | Aurelien Jarno | |
105 | cf154394 | Aurelien Jarno | qemu_set_irq(pic[irq_num], level); |
106 | cf154394 | Aurelien Jarno | } |
107 | cf154394 | Aurelien Jarno | |
108 | cf154394 | Aurelien Jarno | static void sh_pci_map(SysBusDevice *dev, target_phys_addr_t base) |
109 | cf154394 | Aurelien Jarno | { |
110 | cf154394 | Aurelien Jarno | SHPCIState *s = FROM_SYSBUS(SHPCIState, dev); |
111 | cf154394 | Aurelien Jarno | |
112 | cf154394 | Aurelien Jarno | cpu_register_physical_memory(P4ADDR(base), 0x224, s->memconfig);
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113 | cf154394 | Aurelien Jarno | cpu_register_physical_memory(A7ADDR(base), 0x224, s->memconfig);
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114 | cf154394 | Aurelien Jarno | |
115 | cf154394 | Aurelien Jarno | s->iobr = 0xfe240000;
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116 | cf154394 | Aurelien Jarno | isa_mmio_init(s->iobr, 0x40000);
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117 | cf154394 | Aurelien Jarno | } |
118 | cf154394 | Aurelien Jarno | |
119 | cf154394 | Aurelien Jarno | static int sh_pci_init_device(SysBusDevice *dev) |
120 | cf154394 | Aurelien Jarno | { |
121 | cf154394 | Aurelien Jarno | SHPCIState *s; |
122 | cf154394 | Aurelien Jarno | int i;
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123 | cf154394 | Aurelien Jarno | |
124 | cf154394 | Aurelien Jarno | s = FROM_SYSBUS(SHPCIState, dev); |
125 | cf154394 | Aurelien Jarno | for (i = 0; i < 4; i++) { |
126 | cf154394 | Aurelien Jarno | sysbus_init_irq(dev, &s->irq[i]); |
127 | cf154394 | Aurelien Jarno | } |
128 | cf154394 | Aurelien Jarno | s->bus = pci_register_bus(&s->busdev.qdev, "pci",
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129 | cf154394 | Aurelien Jarno | sh_pci_set_irq, sh_pci_map_irq, |
130 | cf154394 | Aurelien Jarno | s->irq, PCI_DEVFN(0, 0), 4); |
131 | cf154394 | Aurelien Jarno | s->memconfig = cpu_register_io_memory(sh_pci_reg.r, sh_pci_reg.w, |
132 | cf154394 | Aurelien Jarno | s, DEVICE_NATIVE_ENDIAN); |
133 | cf154394 | Aurelien Jarno | sysbus_init_mmio_cb(dev, 0x224, sh_pci_map);
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134 | cf154394 | Aurelien Jarno | s->dev = pci_create_simple(s->bus, PCI_DEVFN(0, 0), "sh_pci_host"); |
135 | cf154394 | Aurelien Jarno | return 0; |
136 | cf154394 | Aurelien Jarno | } |
137 | cf154394 | Aurelien Jarno | |
138 | cf154394 | Aurelien Jarno | static int sh_pci_host_init(PCIDevice *d) |
139 | cf154394 | Aurelien Jarno | { |
140 | cf154394 | Aurelien Jarno | pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_HITACHI); |
141 | cf154394 | Aurelien Jarno | pci_config_set_device_id(d->config, PCI_DEVICE_ID_HITACHI_SH7751R); |
142 | cf154394 | Aurelien Jarno | pci_set_word(d->config + PCI_COMMAND, PCI_COMMAND_WAIT); |
143 | cf154394 | Aurelien Jarno | pci_set_word(d->config + PCI_STATUS, PCI_STATUS_CAP_LIST | |
144 | cf154394 | Aurelien Jarno | PCI_STATUS_FAST_BACK | PCI_STATUS_DEVSEL_MEDIUM); |
145 | cf154394 | Aurelien Jarno | return 0; |
146 | cf154394 | Aurelien Jarno | } |
147 | cf154394 | Aurelien Jarno | |
148 | cf154394 | Aurelien Jarno | static PCIDeviceInfo sh_pci_host_info = {
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149 | cf154394 | Aurelien Jarno | .qdev.name = "sh_pci_host",
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150 | cf154394 | Aurelien Jarno | .qdev.size = sizeof(PCIDevice),
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151 | cf154394 | Aurelien Jarno | .init = sh_pci_host_init, |
152 | cf154394 | Aurelien Jarno | }; |
153 | cf154394 | Aurelien Jarno | |
154 | cf154394 | Aurelien Jarno | static void sh_pci_register_devices(void) |
155 | 1e5459a3 | balrog | { |
156 | cf154394 | Aurelien Jarno | sysbus_register_dev("sh_pci", sizeof(SHPCIState), |
157 | cf154394 | Aurelien Jarno | sh_pci_init_device); |
158 | cf154394 | Aurelien Jarno | pci_qdev_register(&sh_pci_host_info); |
159 | 1e5459a3 | balrog | } |
160 | cf154394 | Aurelien Jarno | |
161 | cf154394 | Aurelien Jarno | device_init(sh_pci_register_devices) |