root / hw / etraxfs_ser.c @ a01d8cad
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1 | 83fa1010 | ths | /*
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2 | 83fa1010 | ths | * QEMU ETRAX System Emulator
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3 | 83fa1010 | ths | *
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4 | 83fa1010 | ths | * Copyright (c) 2007 Edgar E. Iglesias, Axis Communications AB.
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5 | 83fa1010 | ths | *
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6 | 83fa1010 | ths | * Permission is hereby granted, free of charge, to any person obtaining a copy
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7 | 83fa1010 | ths | * of this software and associated documentation files (the "Software"), to deal
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8 | 83fa1010 | ths | * in the Software without restriction, including without limitation the rights
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9 | 83fa1010 | ths | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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10 | 83fa1010 | ths | * copies of the Software, and to permit persons to whom the Software is
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11 | 83fa1010 | ths | * furnished to do so, subject to the following conditions:
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12 | 83fa1010 | ths | *
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13 | 83fa1010 | ths | * The above copyright notice and this permission notice shall be included in
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14 | 83fa1010 | ths | * all copies or substantial portions of the Software.
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15 | 83fa1010 | ths | *
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16 | 83fa1010 | ths | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 | 83fa1010 | ths | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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18 | 83fa1010 | ths | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 | 83fa1010 | ths | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 | 83fa1010 | ths | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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21 | 83fa1010 | ths | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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22 | 83fa1010 | ths | * THE SOFTWARE.
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23 | 83fa1010 | ths | */
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24 | 83fa1010 | ths | |
25 | 83fa1010 | ths | #include <stdio.h> |
26 | 83fa1010 | ths | #include <ctype.h> |
27 | 83fa1010 | ths | #include "vl.h" |
28 | 83fa1010 | ths | |
29 | 83fa1010 | ths | #define RW_TR_DMA_EN 0xb0026004 |
30 | 83fa1010 | ths | #define RW_DOUT 0xb002601c |
31 | 83fa1010 | ths | #define RW_STAT_DIN 0xb0026020 |
32 | 83fa1010 | ths | #define R_STAT_DIN 0xb0026024 |
33 | 83fa1010 | ths | |
34 | 83fa1010 | ths | static uint32_t ser_readb (void *opaque, target_phys_addr_t addr) |
35 | 83fa1010 | ths | { |
36 | 83fa1010 | ths | CPUState *env = opaque; |
37 | 83fa1010 | ths | uint32_t r = 0;
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38 | 83fa1010 | ths | printf ("%s %x pc=%x\n", __func__, addr, env->pc);
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39 | 83fa1010 | ths | return r;
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40 | 83fa1010 | ths | } |
41 | 83fa1010 | ths | static uint32_t ser_readw (void *opaque, target_phys_addr_t addr) |
42 | 83fa1010 | ths | { |
43 | 83fa1010 | ths | CPUState *env = opaque; |
44 | 83fa1010 | ths | uint32_t r = 0;
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45 | 83fa1010 | ths | printf ("%s %x pc=%x\n", __func__, addr, env->pc);
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46 | 83fa1010 | ths | return r;
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47 | 83fa1010 | ths | } |
48 | 83fa1010 | ths | |
49 | 83fa1010 | ths | static uint32_t ser_readl (void *opaque, target_phys_addr_t addr) |
50 | 83fa1010 | ths | { |
51 | 83fa1010 | ths | CPUState *env = opaque; |
52 | 83fa1010 | ths | uint32_t r = 0;
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53 | 83fa1010 | ths | |
54 | 83fa1010 | ths | switch (addr)
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55 | 83fa1010 | ths | { |
56 | 83fa1010 | ths | case RW_TR_DMA_EN:
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57 | 83fa1010 | ths | break;
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58 | 83fa1010 | ths | case R_STAT_DIN:
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59 | 83fa1010 | ths | r |= 1 << 24; /* set tr_rdy. */ |
60 | 83fa1010 | ths | r |= 1 << 22; /* set tr_idle. */ |
61 | 83fa1010 | ths | break;
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62 | 83fa1010 | ths | |
63 | 83fa1010 | ths | default:
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64 | 83fa1010 | ths | printf ("%s %x p=%x\n", __func__, addr, env->pc);
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65 | 83fa1010 | ths | break;
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66 | 83fa1010 | ths | } |
67 | 83fa1010 | ths | return r;
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68 | 83fa1010 | ths | } |
69 | 83fa1010 | ths | |
70 | 83fa1010 | ths | static void |
71 | 83fa1010 | ths | ser_writeb (void *opaque, target_phys_addr_t addr, uint32_t value)
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72 | 83fa1010 | ths | { |
73 | 83fa1010 | ths | CPUState *env = opaque; |
74 | 83fa1010 | ths | printf ("%s %x %x pc=%x\n", __func__, addr, value, env->pc);
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75 | 83fa1010 | ths | } |
76 | 83fa1010 | ths | static void |
77 | 83fa1010 | ths | ser_writew (void *opaque, target_phys_addr_t addr, uint32_t value)
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78 | 83fa1010 | ths | { |
79 | 83fa1010 | ths | CPUState *env = opaque; |
80 | 83fa1010 | ths | printf ("%s %x %x pc=%x\n", __func__, addr, value, env->pc);
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81 | 83fa1010 | ths | } |
82 | 83fa1010 | ths | static void |
83 | 83fa1010 | ths | ser_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
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84 | 83fa1010 | ths | { |
85 | 83fa1010 | ths | CPUState *env = opaque; |
86 | 83fa1010 | ths | |
87 | 83fa1010 | ths | switch (addr)
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88 | 83fa1010 | ths | { |
89 | 83fa1010 | ths | case RW_TR_DMA_EN:
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90 | 83fa1010 | ths | break;
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91 | 83fa1010 | ths | case RW_DOUT:
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92 | 83fa1010 | ths | if (isprint(value) || isspace(value))
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93 | 83fa1010 | ths | putchar(value); |
94 | 83fa1010 | ths | else
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95 | 83fa1010 | ths | putchar('.');
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96 | 83fa1010 | ths | break;
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97 | 83fa1010 | ths | default:
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98 | 83fa1010 | ths | printf ("%s %x %x pc=%x\n",
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99 | 83fa1010 | ths | __func__, addr, value, env->pc); |
100 | 83fa1010 | ths | break;
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101 | 83fa1010 | ths | } |
102 | 83fa1010 | ths | } |
103 | 83fa1010 | ths | |
104 | 83fa1010 | ths | static CPUReadMemoryFunc *ser_read[] = {
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105 | 83fa1010 | ths | &ser_readb, |
106 | 83fa1010 | ths | &ser_readw, |
107 | 83fa1010 | ths | &ser_readl, |
108 | 83fa1010 | ths | }; |
109 | 83fa1010 | ths | |
110 | 83fa1010 | ths | static CPUWriteMemoryFunc *ser_write[] = {
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111 | 83fa1010 | ths | &ser_writeb, |
112 | 83fa1010 | ths | &ser_writew, |
113 | 83fa1010 | ths | &ser_writel, |
114 | 83fa1010 | ths | }; |
115 | 83fa1010 | ths | |
116 | 83fa1010 | ths | void etraxfs_ser_init(CPUState *env, qemu_irq *irqs)
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117 | 83fa1010 | ths | { |
118 | 83fa1010 | ths | int ser_regs;
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119 | 83fa1010 | ths | |
120 | 83fa1010 | ths | ser_regs = cpu_register_io_memory(0, ser_read, ser_write, env);
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121 | 83fa1010 | ths | cpu_register_physical_memory (0xb0026000, 0x3c, ser_regs); |
122 | 83fa1010 | ths | } |