root / hw / mips_timer.c @ a01d8cad
History | View | Annotate | Download (2.8 kB)
| 1 |
#include "vl.h" |
|---|---|
| 2 |
|
| 3 |
void cpu_mips_irqctrl_init (void) |
| 4 |
{
|
| 5 |
} |
| 6 |
|
| 7 |
/* XXX: do not use a global */
|
| 8 |
uint32_t cpu_mips_get_random (CPUState *env) |
| 9 |
{
|
| 10 |
static uint32_t seed = 0; |
| 11 |
uint32_t idx; |
| 12 |
seed = seed * 314159 + 1; |
| 13 |
idx = (seed >> 16) % (env->tlb->nb_tlb - env->CP0_Wired) + env->CP0_Wired;
|
| 14 |
return idx;
|
| 15 |
} |
| 16 |
|
| 17 |
/* MIPS R4K timer */
|
| 18 |
uint32_t cpu_mips_get_count (CPUState *env) |
| 19 |
{
|
| 20 |
if (env->CP0_Cause & (1 << CP0Ca_DC)) |
| 21 |
return env->CP0_Count;
|
| 22 |
else
|
| 23 |
return env->CP0_Count +
|
| 24 |
(uint32_t)muldiv64(qemu_get_clock(vm_clock), |
| 25 |
100 * 1000 * 1000, ticks_per_sec); |
| 26 |
} |
| 27 |
|
| 28 |
void cpu_mips_store_count (CPUState *env, uint32_t count)
|
| 29 |
{
|
| 30 |
uint64_t now, next; |
| 31 |
uint32_t tmp; |
| 32 |
uint32_t compare = env->CP0_Compare; |
| 33 |
|
| 34 |
tmp = count; |
| 35 |
if (count == compare)
|
| 36 |
tmp++; |
| 37 |
now = qemu_get_clock(vm_clock); |
| 38 |
next = now + muldiv64(compare - tmp, ticks_per_sec, 100 * 1000 * 1000); |
| 39 |
if (next == now)
|
| 40 |
next++; |
| 41 |
#if 0
|
| 42 |
if (logfile) {
|
| 43 |
fprintf(logfile, "%s: 0x%08" PRIx64 " %08x %08x => 0x%08" PRIx64 "\n",
|
| 44 |
__func__, now, count, compare, next - now);
|
| 45 |
}
|
| 46 |
#endif
|
| 47 |
/* Store new count and compare registers */
|
| 48 |
env->CP0_Compare = compare; |
| 49 |
env->CP0_Count = |
| 50 |
count - (uint32_t)muldiv64(now, 100 * 1000 * 1000, ticks_per_sec); |
| 51 |
/* Adjust timer */
|
| 52 |
qemu_mod_timer(env->timer, next); |
| 53 |
} |
| 54 |
|
| 55 |
static void cpu_mips_update_count (CPUState *env, uint32_t count) |
| 56 |
{
|
| 57 |
if (env->CP0_Cause & (1 << CP0Ca_DC)) |
| 58 |
return;
|
| 59 |
|
| 60 |
cpu_mips_store_count(env, count); |
| 61 |
} |
| 62 |
|
| 63 |
void cpu_mips_store_compare (CPUState *env, uint32_t value)
|
| 64 |
{
|
| 65 |
env->CP0_Compare = value; |
| 66 |
cpu_mips_update_count(env, cpu_mips_get_count(env)); |
| 67 |
if ((env->CP0_Config0 & (0x7 << CP0C0_AR)) == (1 << CP0C0_AR)) |
| 68 |
env->CP0_Cause &= ~(1 << CP0Ca_TI);
|
| 69 |
qemu_irq_lower(env->irq[(env->CP0_IntCtl >> CP0IntCtl_IPTI) & 0x7]);
|
| 70 |
} |
| 71 |
|
| 72 |
void cpu_mips_start_count(CPUState *env)
|
| 73 |
{
|
| 74 |
cpu_mips_store_count(env, env->CP0_Count); |
| 75 |
} |
| 76 |
|
| 77 |
void cpu_mips_stop_count(CPUState *env)
|
| 78 |
{
|
| 79 |
/* Store the current value */
|
| 80 |
env->CP0_Count += (uint32_t)muldiv64(qemu_get_clock(vm_clock), |
| 81 |
100 * 1000 * 1000, ticks_per_sec); |
| 82 |
} |
| 83 |
|
| 84 |
static void mips_timer_cb (void *opaque) |
| 85 |
{
|
| 86 |
CPUState *env; |
| 87 |
|
| 88 |
env = opaque; |
| 89 |
#if 0
|
| 90 |
if (logfile) {
|
| 91 |
fprintf(logfile, "%s\n", __func__);
|
| 92 |
}
|
| 93 |
#endif
|
| 94 |
|
| 95 |
if (env->CP0_Cause & (1 << CP0Ca_DC)) |
| 96 |
return;
|
| 97 |
|
| 98 |
cpu_mips_update_count(env, cpu_mips_get_count(env)); |
| 99 |
if ((env->CP0_Config0 & (0x7 << CP0C0_AR)) == (1 << CP0C0_AR)) |
| 100 |
env->CP0_Cause |= 1 << CP0Ca_TI;
|
| 101 |
qemu_irq_raise(env->irq[(env->CP0_IntCtl >> CP0IntCtl_IPTI) & 0x7]);
|
| 102 |
} |
| 103 |
|
| 104 |
void cpu_mips_clock_init (CPUState *env)
|
| 105 |
{
|
| 106 |
env->timer = qemu_new_timer(vm_clock, &mips_timer_cb, env); |
| 107 |
env->CP0_Compare = 0;
|
| 108 |
cpu_mips_update_count(env, 1);
|
| 109 |
} |