root / hw / strongarm.h @ a0a3167a
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#ifndef _STRONGARM_H
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#define _STRONGARM_H
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#define SA_CS0 0x00000000 |
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#define SA_CS1 0x08000000 |
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#define SA_CS2 0x10000000 |
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#define SA_CS3 0x18000000 |
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#define SA_PCMCIA_CS0 0x20000000 |
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#define SA_PCMCIA_CS1 0x30000000 |
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#define SA_CS4 0x40000000 |
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#define SA_CS5 0x48000000 |
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/* system registers here */
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#define SA_SDCS0 0xc0000000 |
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#define SA_SDCS1 0xc8000000 |
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#define SA_SDCS2 0xd0000000 |
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#define SA_SDCS3 0xd8000000 |
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enum {
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SA_PIC_GPIO0_EDGE = 0,
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SA_PIC_GPIO1_EDGE, |
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SA_PIC_GPIO2_EDGE, |
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SA_PIC_GPIO3_EDGE, |
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SA_PIC_GPIO4_EDGE, |
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SA_PIC_GPIO5_EDGE, |
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SA_PIC_GPIO6_EDGE, |
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SA_PIC_GPIO7_EDGE, |
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SA_PIC_GPIO8_EDGE, |
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SA_PIC_GPIO9_EDGE, |
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SA_PIC_GPIO10_EDGE, |
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SA_PIC_GPIOX_EDGE, |
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SA_PIC_LCD, |
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SA_PIC_UDC, |
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SA_PIC_RSVD1, |
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SA_PIC_UART1, |
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SA_PIC_UART2, |
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SA_PIC_UART3, |
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SA_PIC_MCP, |
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SA_PIC_SSP, |
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SA_PIC_DMA_CH0, |
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SA_PIC_DMA_CH1, |
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SA_PIC_DMA_CH2, |
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SA_PIC_DMA_CH3, |
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SA_PIC_DMA_CH4, |
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SA_PIC_DMA_CH5, |
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SA_PIC_OSTC0, |
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SA_PIC_OSTC1, |
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SA_PIC_OSTC2, |
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SA_PIC_OSTC3, |
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SA_PIC_RTC_HZ, |
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SA_PIC_RTC_ALARM, |
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}; |
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typedef struct { |
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CPUState *env; |
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DeviceState *pic; |
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DeviceState *gpio; |
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DeviceState *ppc; |
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DeviceState *ssp; |
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SSIBus *ssp_bus; |
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} StrongARMState; |
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StrongARMState *sa1110_init(unsigned int sdram_size, const char *rev); |
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#endif
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