Revision a0a8793e hw/gt64xxx.c
| b/hw/gt64xxx.c | ||
|---|---|---|
| 225 | 225 |
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| 226 | 226 |
typedef PCIHostState GT64120PCIState; |
| 227 | 227 |
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#define PCI_MAPPING_ENTRY(regname) \ |
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target_phys_addr_t regname ##_start; \ |
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target_phys_addr_t regname ##_length; \ |
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int regname ##_handle |
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typedef struct GT64120State {
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GT64120PCIState *pci; |
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uint32_t regs[GT_REGS]; |
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target_phys_addr_t PCI0IO_start;
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target_phys_addr_t PCI0IO_length;
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PCI_MAPPING_ENTRY(PCI0IO);
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PCI_MAPPING_ENTRY(ISD);
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} GT64120State; |
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/* Adjust range to avoid touching space which isn't mappable via PCI */ |
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/* XXX: Hardcoded values for Malta: 0x1e000000 - 0x1f100000 |
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0x1fc00000 - 0x1fd00000 */ |
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static void check_reserved_space (target_phys_addr_t *start, |
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target_phys_addr_t *length) |
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{
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target_phys_addr_t begin = *start; |
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target_phys_addr_t end = *start + *length; |
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if (end >= 0x1e000000LL && end < 0x1f100000LL) |
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end = 0x1e000000LL; |
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if (begin >= 0x1e000000LL && begin < 0x1f100000LL) |
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begin = 0x1f100000LL; |
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if (end >= 0x1fc00000LL && end < 0x1fd00000LL) |
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end = 0x1fc00000LL; |
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if (begin >= 0x1fc00000LL && begin < 0x1fd00000LL) |
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begin = 0x1fd00000LL; |
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/* XXX: This is broken when a reserved range splits the requested range */ |
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if (end >= 0x1f100000LL && begin < 0x1e000000LL) |
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end = 0x1e000000LL; |
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if (end >= 0x1fd00000LL && begin < 0x1fc00000LL) |
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end = 0x1fc00000LL; |
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*start = begin; |
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*length = end - begin; |
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} |
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static void gt64120_isd_mapping(GT64120State *s) |
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{
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target_phys_addr_t start = s->regs[GT_ISD] << 21; |
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target_phys_addr_t length = 0x1000; |
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if (s->ISD_length) |
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cpu_register_physical_memory(s->ISD_start, s->ISD_length, |
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IO_MEM_UNASSIGNED); |
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check_reserved_space(&start, &length); |
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length = 0x1000; |
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/* Map new address */ |
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dprintf("ISD: %x@%x -> %x@%x, %x\n", s->ISD_length, s->ISD_start,
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length, start, s->ISD_handle); |
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s->ISD_start = start; |
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s->ISD_length = length; |
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cpu_register_physical_memory(s->ISD_start, s->ISD_length, s->ISD_handle); |
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} |
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static void gt64120_pci_mapping(GT64120State *s) |
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{
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/* Update IO mapping */ |
| ... | ... | |
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s->regs[saddr] = val & 0x0000007f; |
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gt64120_pci_mapping(s); |
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break; |
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case GT_ISD: |
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s->regs[saddr] = val & 0x00007fff; |
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gt64120_isd_mapping(s); |
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break; |
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|
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case GT_PCI0IOREMAP: |
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case GT_PCI0M0REMAP: |
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case GT_PCI0M1REMAP: |
| ... | ... | |
| 1026 | 1081 |
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/* Interrupt registers are all zeroed at reset */ |
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gt64120_isd_mapping(s); |
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gt64120_pci_mapping(s); |
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} |
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|
| ... | ... | |
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{
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GT64120State *s; |
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PCIDevice *d; |
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int gt64120; |
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s = qemu_mallocz(sizeof(GT64120State)); |
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s->pci = qemu_mallocz(sizeof(GT64120PCIState)); |
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gt64120_reset(s); |
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s->pci->bus = pci_register_bus(pci_gt64120_set_irq, pci_gt64120_map_irq, |
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pic, 144, 4); |
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gt64120 = cpu_register_io_memory(0, gt64120_read, |
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gt64120_write, s); |
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cpu_register_physical_memory(0x1be00000LL, 0x1000, gt64120); |
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s->ISD_handle = cpu_register_io_memory(0, gt64120_read, gt64120_write, s); |
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d = pci_register_device(s->pci->bus, "GT64120 PCI Bus", sizeof(PCIDevice), |
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0, gt64120_read_config, gt64120_write_config); |
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/* FIXME: Malta specific hw assumptions ahead */ |
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d->config[0x00] = 0xab; // vendor_id
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d->config[0x00] = 0xab; /* vendor_id */
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d->config[0x01] = 0x11; |
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d->config[0x02] = 0x20; // device_id
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d->config[0x02] = 0x20; /* device_id */
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d->config[0x03] = 0x46; |
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d->config[0x04] = 0x00; |
| ... | ... | |
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d->config[0x27] = 0x14; |
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d->config[0x3D] = 0x01; |
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gt64120_reset(s); |
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register_savevm("GT64120 PCI Bus", 0, 1, gt64120_save, gt64120_load, d);
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return s->pci->bus; |
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