root / hw / milkymist-memcard.c @ a0f42610
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1 | b4e37d98 | Michael Walle | /*
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2 | b4e37d98 | Michael Walle | * QEMU model of the Milkymist SD Card Controller.
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3 | b4e37d98 | Michael Walle | *
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4 | b4e37d98 | Michael Walle | * Copyright (c) 2010 Michael Walle <michael@walle.cc>
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5 | b4e37d98 | Michael Walle | *
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6 | b4e37d98 | Michael Walle | * This library is free software; you can redistribute it and/or
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7 | b4e37d98 | Michael Walle | * modify it under the terms of the GNU Lesser General Public
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8 | b4e37d98 | Michael Walle | * License as published by the Free Software Foundation; either
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9 | b4e37d98 | Michael Walle | * version 2 of the License, or (at your option) any later version.
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10 | b4e37d98 | Michael Walle | *
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11 | b4e37d98 | Michael Walle | * This library is distributed in the hope that it will be useful,
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12 | b4e37d98 | Michael Walle | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 | b4e37d98 | Michael Walle | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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14 | b4e37d98 | Michael Walle | * Lesser General Public License for more details.
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15 | b4e37d98 | Michael Walle | *
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16 | b4e37d98 | Michael Walle | * You should have received a copy of the GNU Lesser General Public
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17 | b4e37d98 | Michael Walle | * License along with this library; if not, see <http://www.gnu.org/licenses/>.
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18 | b4e37d98 | Michael Walle | *
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19 | b4e37d98 | Michael Walle | *
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20 | b4e37d98 | Michael Walle | * Specification available at:
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21 | b4e37d98 | Michael Walle | * http://www.milkymist.org/socdoc/memcard.pdf
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22 | b4e37d98 | Michael Walle | */
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23 | b4e37d98 | Michael Walle | |
24 | b4e37d98 | Michael Walle | #include "hw.h" |
25 | b4e37d98 | Michael Walle | #include "sysbus.h" |
26 | b4e37d98 | Michael Walle | #include "sysemu.h" |
27 | b4e37d98 | Michael Walle | #include "trace.h" |
28 | b4e37d98 | Michael Walle | #include "qemu-error.h" |
29 | b4e37d98 | Michael Walle | #include "blockdev.h" |
30 | b4e37d98 | Michael Walle | #include "sd.h" |
31 | b4e37d98 | Michael Walle | |
32 | b4e37d98 | Michael Walle | enum {
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33 | b4e37d98 | Michael Walle | ENABLE_CMD_TX = (1<<0), |
34 | b4e37d98 | Michael Walle | ENABLE_CMD_RX = (1<<1), |
35 | b4e37d98 | Michael Walle | ENABLE_DAT_TX = (1<<2), |
36 | b4e37d98 | Michael Walle | ENABLE_DAT_RX = (1<<3), |
37 | b4e37d98 | Michael Walle | }; |
38 | b4e37d98 | Michael Walle | |
39 | b4e37d98 | Michael Walle | enum {
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40 | b4e37d98 | Michael Walle | PENDING_CMD_TX = (1<<0), |
41 | b4e37d98 | Michael Walle | PENDING_CMD_RX = (1<<1), |
42 | b4e37d98 | Michael Walle | PENDING_DAT_TX = (1<<2), |
43 | b4e37d98 | Michael Walle | PENDING_DAT_RX = (1<<3), |
44 | b4e37d98 | Michael Walle | }; |
45 | b4e37d98 | Michael Walle | |
46 | b4e37d98 | Michael Walle | enum {
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47 | b4e37d98 | Michael Walle | START_CMD_TX = (1<<0), |
48 | b4e37d98 | Michael Walle | START_DAT_RX = (1<<1), |
49 | b4e37d98 | Michael Walle | }; |
50 | b4e37d98 | Michael Walle | |
51 | b4e37d98 | Michael Walle | enum {
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52 | b4e37d98 | Michael Walle | R_CLK2XDIV = 0,
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53 | b4e37d98 | Michael Walle | R_ENABLE, |
54 | b4e37d98 | Michael Walle | R_PENDING, |
55 | b4e37d98 | Michael Walle | R_START, |
56 | b4e37d98 | Michael Walle | R_CMD, |
57 | b4e37d98 | Michael Walle | R_DAT, |
58 | b4e37d98 | Michael Walle | R_MAX |
59 | b4e37d98 | Michael Walle | }; |
60 | b4e37d98 | Michael Walle | |
61 | b4e37d98 | Michael Walle | struct MilkymistMemcardState {
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62 | b4e37d98 | Michael Walle | SysBusDevice busdev; |
63 | 8c85d15b | Michael Walle | MemoryRegion regs_region; |
64 | b4e37d98 | Michael Walle | SDState *card; |
65 | b4e37d98 | Michael Walle | |
66 | b4e37d98 | Michael Walle | int command_write_ptr;
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67 | b4e37d98 | Michael Walle | int response_read_ptr;
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68 | b4e37d98 | Michael Walle | int response_len;
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69 | b4e37d98 | Michael Walle | int ignore_next_cmd;
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70 | b4e37d98 | Michael Walle | int enabled;
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71 | b4e37d98 | Michael Walle | uint8_t command[6];
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72 | b4e37d98 | Michael Walle | uint8_t response[17];
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73 | b4e37d98 | Michael Walle | uint32_t regs[R_MAX]; |
74 | b4e37d98 | Michael Walle | }; |
75 | b4e37d98 | Michael Walle | typedef struct MilkymistMemcardState MilkymistMemcardState; |
76 | b4e37d98 | Michael Walle | |
77 | b4e37d98 | Michael Walle | static void update_pending_bits(MilkymistMemcardState *s) |
78 | b4e37d98 | Michael Walle | { |
79 | b4e37d98 | Michael Walle | /* transmits are instantaneous, thus tx pending bits are never set */
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80 | b4e37d98 | Michael Walle | s->regs[R_PENDING] = 0;
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81 | b4e37d98 | Michael Walle | /* if rx is enabled the corresponding pending bits are always set */
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82 | b4e37d98 | Michael Walle | if (s->regs[R_ENABLE] & ENABLE_CMD_RX) {
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83 | b4e37d98 | Michael Walle | s->regs[R_PENDING] |= PENDING_CMD_RX; |
84 | b4e37d98 | Michael Walle | } |
85 | b4e37d98 | Michael Walle | if (s->regs[R_ENABLE] & ENABLE_DAT_RX) {
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86 | b4e37d98 | Michael Walle | s->regs[R_PENDING] |= PENDING_DAT_RX; |
87 | b4e37d98 | Michael Walle | } |
88 | b4e37d98 | Michael Walle | } |
89 | b4e37d98 | Michael Walle | |
90 | b4e37d98 | Michael Walle | static void memcard_sd_command(MilkymistMemcardState *s) |
91 | b4e37d98 | Michael Walle | { |
92 | b4e37d98 | Michael Walle | SDRequest req; |
93 | b4e37d98 | Michael Walle | |
94 | b4e37d98 | Michael Walle | req.cmd = s->command[0] & 0x3f; |
95 | b4e37d98 | Michael Walle | req.arg = (s->command[1] << 24) | (s->command[2] << 16) |
96 | b4e37d98 | Michael Walle | | (s->command[3] << 8) | s->command[4]; |
97 | b4e37d98 | Michael Walle | req.crc = s->command[5];
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98 | b4e37d98 | Michael Walle | |
99 | b4e37d98 | Michael Walle | s->response[0] = req.cmd;
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100 | b4e37d98 | Michael Walle | s->response_len = sd_do_command(s->card, &req, s->response+1);
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101 | b4e37d98 | Michael Walle | s->response_read_ptr = 0;
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102 | b4e37d98 | Michael Walle | |
103 | b4e37d98 | Michael Walle | if (s->response_len == 16) { |
104 | b4e37d98 | Michael Walle | /* R2 response */
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105 | b4e37d98 | Michael Walle | s->response[0] = 0x3f; |
106 | b4e37d98 | Michael Walle | s->response_len += 1;
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107 | b4e37d98 | Michael Walle | } else if (s->response_len == 4) { |
108 | b4e37d98 | Michael Walle | /* no crc calculation, insert dummy byte */
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109 | b4e37d98 | Michael Walle | s->response[5] = 0; |
110 | b4e37d98 | Michael Walle | s->response_len += 2;
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111 | b4e37d98 | Michael Walle | } |
112 | b4e37d98 | Michael Walle | |
113 | b4e37d98 | Michael Walle | if (req.cmd == 0) { |
114 | b4e37d98 | Michael Walle | /* next write is a dummy byte to clock the initialization of the sd
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115 | b4e37d98 | Michael Walle | * card */
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116 | b4e37d98 | Michael Walle | s->ignore_next_cmd = 1;
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117 | b4e37d98 | Michael Walle | } |
118 | b4e37d98 | Michael Walle | } |
119 | b4e37d98 | Michael Walle | |
120 | 8c85d15b | Michael Walle | static uint64_t memcard_read(void *opaque, target_phys_addr_t addr, |
121 | 8c85d15b | Michael Walle | unsigned size)
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122 | b4e37d98 | Michael Walle | { |
123 | b4e37d98 | Michael Walle | MilkymistMemcardState *s = opaque; |
124 | b4e37d98 | Michael Walle | uint32_t r = 0;
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125 | b4e37d98 | Michael Walle | |
126 | b4e37d98 | Michael Walle | addr >>= 2;
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127 | b4e37d98 | Michael Walle | switch (addr) {
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128 | b4e37d98 | Michael Walle | case R_CMD:
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129 | b4e37d98 | Michael Walle | if (!s->enabled) {
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130 | b4e37d98 | Michael Walle | r = 0xff;
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131 | b4e37d98 | Michael Walle | } else {
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132 | b4e37d98 | Michael Walle | r = s->response[s->response_read_ptr++]; |
133 | b4e37d98 | Michael Walle | if (s->response_read_ptr > s->response_len) {
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134 | b4e37d98 | Michael Walle | error_report("milkymist_memcard: "
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135 | b4e37d98 | Michael Walle | "read more cmd bytes than available. Clipping.");
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136 | b4e37d98 | Michael Walle | s->response_read_ptr = 0;
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137 | b4e37d98 | Michael Walle | } |
138 | b4e37d98 | Michael Walle | } |
139 | b4e37d98 | Michael Walle | break;
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140 | b4e37d98 | Michael Walle | case R_DAT:
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141 | b4e37d98 | Michael Walle | if (!s->enabled) {
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142 | b4e37d98 | Michael Walle | r = 0xffffffff;
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143 | b4e37d98 | Michael Walle | } else {
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144 | b4e37d98 | Michael Walle | r = 0;
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145 | b4e37d98 | Michael Walle | r |= sd_read_data(s->card) << 24;
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146 | b4e37d98 | Michael Walle | r |= sd_read_data(s->card) << 16;
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147 | b4e37d98 | Michael Walle | r |= sd_read_data(s->card) << 8;
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148 | b4e37d98 | Michael Walle | r |= sd_read_data(s->card); |
149 | b4e37d98 | Michael Walle | } |
150 | b4e37d98 | Michael Walle | break;
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151 | b4e37d98 | Michael Walle | case R_CLK2XDIV:
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152 | b4e37d98 | Michael Walle | case R_ENABLE:
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153 | b4e37d98 | Michael Walle | case R_PENDING:
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154 | b4e37d98 | Michael Walle | case R_START:
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155 | b4e37d98 | Michael Walle | r = s->regs[addr]; |
156 | b4e37d98 | Michael Walle | break;
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157 | b4e37d98 | Michael Walle | |
158 | b4e37d98 | Michael Walle | default:
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159 | dd3d6775 | Markus Armbruster | error_report("milkymist_memcard: read access to unknown register 0x"
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160 | b4e37d98 | Michael Walle | TARGET_FMT_plx, addr << 2);
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161 | b4e37d98 | Michael Walle | break;
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162 | b4e37d98 | Michael Walle | } |
163 | b4e37d98 | Michael Walle | |
164 | b4e37d98 | Michael Walle | trace_milkymist_memcard_memory_read(addr << 2, r);
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165 | b4e37d98 | Michael Walle | |
166 | b4e37d98 | Michael Walle | return r;
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167 | b4e37d98 | Michael Walle | } |
168 | b4e37d98 | Michael Walle | |
169 | 8c85d15b | Michael Walle | static void memcard_write(void *opaque, target_phys_addr_t addr, uint64_t value, |
170 | 8c85d15b | Michael Walle | unsigned size)
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171 | b4e37d98 | Michael Walle | { |
172 | b4e37d98 | Michael Walle | MilkymistMemcardState *s = opaque; |
173 | b4e37d98 | Michael Walle | |
174 | b4e37d98 | Michael Walle | trace_milkymist_memcard_memory_write(addr, value); |
175 | b4e37d98 | Michael Walle | |
176 | b4e37d98 | Michael Walle | addr >>= 2;
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177 | b4e37d98 | Michael Walle | switch (addr) {
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178 | b4e37d98 | Michael Walle | case R_PENDING:
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179 | b4e37d98 | Michael Walle | /* clear rx pending bits */
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180 | b4e37d98 | Michael Walle | s->regs[R_PENDING] &= ~(value & (PENDING_CMD_RX | PENDING_DAT_RX)); |
181 | b4e37d98 | Michael Walle | update_pending_bits(s); |
182 | b4e37d98 | Michael Walle | break;
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183 | b4e37d98 | Michael Walle | case R_CMD:
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184 | b4e37d98 | Michael Walle | if (!s->enabled) {
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185 | b4e37d98 | Michael Walle | break;
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186 | b4e37d98 | Michael Walle | } |
187 | b4e37d98 | Michael Walle | if (s->ignore_next_cmd) {
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188 | b4e37d98 | Michael Walle | s->ignore_next_cmd = 0;
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189 | b4e37d98 | Michael Walle | break;
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190 | b4e37d98 | Michael Walle | } |
191 | b4e37d98 | Michael Walle | s->command[s->command_write_ptr] = value & 0xff;
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192 | b4e37d98 | Michael Walle | s->command_write_ptr = (s->command_write_ptr + 1) % 6; |
193 | b4e37d98 | Michael Walle | if (s->command_write_ptr == 0) { |
194 | b4e37d98 | Michael Walle | memcard_sd_command(s); |
195 | b4e37d98 | Michael Walle | } |
196 | b4e37d98 | Michael Walle | break;
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197 | b4e37d98 | Michael Walle | case R_DAT:
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198 | b4e37d98 | Michael Walle | if (!s->enabled) {
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199 | b4e37d98 | Michael Walle | break;
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200 | b4e37d98 | Michael Walle | } |
201 | b4e37d98 | Michael Walle | sd_write_data(s->card, (value >> 24) & 0xff); |
202 | b4e37d98 | Michael Walle | sd_write_data(s->card, (value >> 16) & 0xff); |
203 | b4e37d98 | Michael Walle | sd_write_data(s->card, (value >> 8) & 0xff); |
204 | b4e37d98 | Michael Walle | sd_write_data(s->card, value & 0xff);
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205 | b4e37d98 | Michael Walle | break;
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206 | b4e37d98 | Michael Walle | case R_ENABLE:
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207 | b4e37d98 | Michael Walle | s->regs[addr] = value; |
208 | b4e37d98 | Michael Walle | update_pending_bits(s); |
209 | b4e37d98 | Michael Walle | break;
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210 | b4e37d98 | Michael Walle | case R_CLK2XDIV:
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211 | b4e37d98 | Michael Walle | case R_START:
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212 | b4e37d98 | Michael Walle | s->regs[addr] = value; |
213 | b4e37d98 | Michael Walle | break;
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214 | b4e37d98 | Michael Walle | |
215 | b4e37d98 | Michael Walle | default:
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216 | dd3d6775 | Markus Armbruster | error_report("milkymist_memcard: write access to unknown register 0x"
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217 | b4e37d98 | Michael Walle | TARGET_FMT_plx, addr << 2);
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218 | b4e37d98 | Michael Walle | break;
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219 | b4e37d98 | Michael Walle | } |
220 | b4e37d98 | Michael Walle | } |
221 | b4e37d98 | Michael Walle | |
222 | 8c85d15b | Michael Walle | static const MemoryRegionOps memcard_mmio_ops = { |
223 | 8c85d15b | Michael Walle | .read = memcard_read, |
224 | 8c85d15b | Michael Walle | .write = memcard_write, |
225 | 8c85d15b | Michael Walle | .valid = { |
226 | 8c85d15b | Michael Walle | .min_access_size = 4,
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227 | 8c85d15b | Michael Walle | .max_access_size = 4,
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228 | 8c85d15b | Michael Walle | }, |
229 | 8c85d15b | Michael Walle | .endianness = DEVICE_NATIVE_ENDIAN, |
230 | b4e37d98 | Michael Walle | }; |
231 | b4e37d98 | Michael Walle | |
232 | b4e37d98 | Michael Walle | static void milkymist_memcard_reset(DeviceState *d) |
233 | b4e37d98 | Michael Walle | { |
234 | b4e37d98 | Michael Walle | MilkymistMemcardState *s = |
235 | b4e37d98 | Michael Walle | container_of(d, MilkymistMemcardState, busdev.qdev); |
236 | b4e37d98 | Michael Walle | int i;
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237 | b4e37d98 | Michael Walle | |
238 | b4e37d98 | Michael Walle | s->command_write_ptr = 0;
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239 | b4e37d98 | Michael Walle | s->response_read_ptr = 0;
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240 | b4e37d98 | Michael Walle | s->response_len = 0;
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241 | b4e37d98 | Michael Walle | |
242 | b4e37d98 | Michael Walle | for (i = 0; i < R_MAX; i++) { |
243 | b4e37d98 | Michael Walle | s->regs[i] = 0;
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244 | b4e37d98 | Michael Walle | } |
245 | b4e37d98 | Michael Walle | } |
246 | b4e37d98 | Michael Walle | |
247 | b4e37d98 | Michael Walle | static int milkymist_memcard_init(SysBusDevice *dev) |
248 | b4e37d98 | Michael Walle | { |
249 | b4e37d98 | Michael Walle | MilkymistMemcardState *s = FROM_SYSBUS(typeof(*s), dev); |
250 | b4e37d98 | Michael Walle | DriveInfo *dinfo; |
251 | b4e37d98 | Michael Walle | |
252 | b4e37d98 | Michael Walle | dinfo = drive_get_next(IF_SD); |
253 | b4e37d98 | Michael Walle | s->card = sd_init(dinfo ? dinfo->bdrv : NULL, 0); |
254 | b4e37d98 | Michael Walle | s->enabled = dinfo ? bdrv_is_inserted(dinfo->bdrv) : 0;
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255 | b4e37d98 | Michael Walle | |
256 | 8c85d15b | Michael Walle | memory_region_init_io(&s->regs_region, &memcard_mmio_ops, s, |
257 | 8c85d15b | Michael Walle | "milkymist-memcard", R_MAX * 4); |
258 | 750ecd44 | Avi Kivity | sysbus_init_mmio(dev, &s->regs_region); |
259 | b4e37d98 | Michael Walle | |
260 | b4e37d98 | Michael Walle | return 0; |
261 | b4e37d98 | Michael Walle | } |
262 | b4e37d98 | Michael Walle | |
263 | b4e37d98 | Michael Walle | static const VMStateDescription vmstate_milkymist_memcard = { |
264 | b4e37d98 | Michael Walle | .name = "milkymist-memcard",
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265 | b4e37d98 | Michael Walle | .version_id = 1,
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266 | b4e37d98 | Michael Walle | .minimum_version_id = 1,
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267 | b4e37d98 | Michael Walle | .minimum_version_id_old = 1,
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268 | b4e37d98 | Michael Walle | .fields = (VMStateField[]) { |
269 | b4e37d98 | Michael Walle | VMSTATE_INT32(command_write_ptr, MilkymistMemcardState), |
270 | b4e37d98 | Michael Walle | VMSTATE_INT32(response_read_ptr, MilkymistMemcardState), |
271 | b4e37d98 | Michael Walle | VMSTATE_INT32(response_len, MilkymistMemcardState), |
272 | b4e37d98 | Michael Walle | VMSTATE_INT32(ignore_next_cmd, MilkymistMemcardState), |
273 | b4e37d98 | Michael Walle | VMSTATE_INT32(enabled, MilkymistMemcardState), |
274 | b4e37d98 | Michael Walle | VMSTATE_UINT8_ARRAY(command, MilkymistMemcardState, 6),
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275 | b4e37d98 | Michael Walle | VMSTATE_UINT8_ARRAY(response, MilkymistMemcardState, 17),
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276 | b4e37d98 | Michael Walle | VMSTATE_UINT32_ARRAY(regs, MilkymistMemcardState, R_MAX), |
277 | b4e37d98 | Michael Walle | VMSTATE_END_OF_LIST() |
278 | b4e37d98 | Michael Walle | } |
279 | b4e37d98 | Michael Walle | }; |
280 | b4e37d98 | Michael Walle | |
281 | b4e37d98 | Michael Walle | static SysBusDeviceInfo milkymist_memcard_info = {
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282 | b4e37d98 | Michael Walle | .init = milkymist_memcard_init, |
283 | b4e37d98 | Michael Walle | .qdev.name = "milkymist-memcard",
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284 | b4e37d98 | Michael Walle | .qdev.size = sizeof(MilkymistMemcardState),
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285 | b4e37d98 | Michael Walle | .qdev.vmsd = &vmstate_milkymist_memcard, |
286 | b4e37d98 | Michael Walle | .qdev.reset = milkymist_memcard_reset, |
287 | b4e37d98 | Michael Walle | }; |
288 | b4e37d98 | Michael Walle | |
289 | b4e37d98 | Michael Walle | static void milkymist_memcard_register(void) |
290 | b4e37d98 | Michael Walle | { |
291 | b4e37d98 | Michael Walle | sysbus_register_withprop(&milkymist_memcard_info); |
292 | b4e37d98 | Michael Walle | } |
293 | b4e37d98 | Michael Walle | |
294 | b4e37d98 | Michael Walle | device_init(milkymist_memcard_register) |