root / hw / piix_pci.c @ a15fdf86
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1 | 502a5395 | pbrook | /*
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2 | 502a5395 | pbrook | * QEMU i440FX/PIIX3 PCI Bridge Emulation
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3 | 502a5395 | pbrook | *
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4 | 502a5395 | pbrook | * Copyright (c) 2006 Fabrice Bellard
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5 | 5fafdf24 | ths | *
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6 | 502a5395 | pbrook | * Permission is hereby granted, free of charge, to any person obtaining a copy
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7 | 502a5395 | pbrook | * of this software and associated documentation files (the "Software"), to deal
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8 | 502a5395 | pbrook | * in the Software without restriction, including without limitation the rights
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9 | 502a5395 | pbrook | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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10 | 502a5395 | pbrook | * copies of the Software, and to permit persons to whom the Software is
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11 | 502a5395 | pbrook | * furnished to do so, subject to the following conditions:
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12 | 502a5395 | pbrook | *
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13 | 502a5395 | pbrook | * The above copyright notice and this permission notice shall be included in
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14 | 502a5395 | pbrook | * all copies or substantial portions of the Software.
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15 | 502a5395 | pbrook | *
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16 | 502a5395 | pbrook | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 | 502a5395 | pbrook | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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18 | 502a5395 | pbrook | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 | 502a5395 | pbrook | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 | 502a5395 | pbrook | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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21 | 502a5395 | pbrook | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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22 | 502a5395 | pbrook | * THE SOFTWARE.
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23 | 502a5395 | pbrook | */
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24 | 502a5395 | pbrook | |
25 | 87ecb68b | pbrook | #include "hw.h" |
26 | 87ecb68b | pbrook | #include "pc.h" |
27 | 87ecb68b | pbrook | #include "pci.h" |
28 | 4f5e19e6 | Isaku Yamahata | #include "pci_host.h" |
29 | f75247f1 | Gerd Hoffmann | #include "isa.h" |
30 | 8a14daa5 | Gerd Hoffmann | #include "sysbus.h" |
31 | 87ecb68b | pbrook | |
32 | 502a5395 | pbrook | typedef PCIHostState I440FXState;
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33 | 502a5395 | pbrook | |
34 | fd37d881 | Juan Quintela | typedef struct PIIX3State { |
35 | fd37d881 | Juan Quintela | PCIDevice dev; |
36 | 8372615d | Juan Quintela | int pci_irq_levels[4]; |
37 | bd7dce87 | Juan Quintela | qemu_irq *pic; |
38 | 7cd9eee0 | Gerd Hoffmann | } PIIX3State; |
39 | bd7dce87 | Juan Quintela | |
40 | 0a3bacf3 | Juan Quintela | struct PCII440FXState {
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41 | 0a3bacf3 | Juan Quintela | PCIDevice dev; |
42 | c227f099 | Anthony Liguori | target_phys_addr_t isa_page_descs[384 / 4]; |
43 | 6c009fa4 | Juan Quintela | uint8_t smm_enabled; |
44 | 7cd9eee0 | Gerd Hoffmann | PIIX3State *piix3; |
45 | 0a3bacf3 | Juan Quintela | }; |
46 | 0a3bacf3 | Juan Quintela | |
47 | 5d4e84c8 | Juan Quintela | static void piix3_set_irq(void *opaque, int irq_num, int level); |
48 | d2b59317 | pbrook | |
49 | d2b59317 | pbrook | /* return the global irq number corresponding to a given device irq
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50 | d2b59317 | pbrook | pin. We could also use the bus number to have a more precise
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51 | d2b59317 | pbrook | mapping. */
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52 | d2b59317 | pbrook | static int pci_slot_get_pirq(PCIDevice *pci_dev, int irq_num) |
53 | d2b59317 | pbrook | { |
54 | d2b59317 | pbrook | int slot_addend;
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55 | d2b59317 | pbrook | slot_addend = (pci_dev->devfn >> 3) - 1; |
56 | d2b59317 | pbrook | return (irq_num + slot_addend) & 3; |
57 | d2b59317 | pbrook | } |
58 | 502a5395 | pbrook | |
59 | 0a3bacf3 | Juan Quintela | static void update_pam(PCII440FXState *d, uint32_t start, uint32_t end, int r) |
60 | 84631fd7 | bellard | { |
61 | 84631fd7 | bellard | uint32_t addr; |
62 | 84631fd7 | bellard | |
63 | 84631fd7 | bellard | // printf("ISA mapping %08x-0x%08x: %d\n", start, end, r);
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64 | 84631fd7 | bellard | switch(r) {
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65 | 84631fd7 | bellard | case 3: |
66 | 84631fd7 | bellard | /* RAM */
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67 | 5fafdf24 | ths | cpu_register_physical_memory(start, end - start, |
68 | 84631fd7 | bellard | start); |
69 | 84631fd7 | bellard | break;
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70 | 84631fd7 | bellard | case 1: |
71 | 84631fd7 | bellard | /* ROM (XXX: not quite correct) */
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72 | 5fafdf24 | ths | cpu_register_physical_memory(start, end - start, |
73 | 84631fd7 | bellard | start | IO_MEM_ROM); |
74 | 84631fd7 | bellard | break;
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75 | 84631fd7 | bellard | case 2: |
76 | 84631fd7 | bellard | case 0: |
77 | 84631fd7 | bellard | /* XXX: should distinguish read/write cases */
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78 | 84631fd7 | bellard | for(addr = start; addr < end; addr += 4096) { |
79 | 5fafdf24 | ths | cpu_register_physical_memory(addr, 4096,
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80 | 6c009fa4 | Juan Quintela | d->isa_page_descs[(addr - 0xa0000) >> 12]); |
81 | 84631fd7 | bellard | } |
82 | 84631fd7 | bellard | break;
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83 | 84631fd7 | bellard | } |
84 | 84631fd7 | bellard | } |
85 | ee0ea1d0 | bellard | |
86 | 0a3bacf3 | Juan Quintela | static void i440fx_update_memory_mappings(PCII440FXState *d) |
87 | ee0ea1d0 | bellard | { |
88 | ee0ea1d0 | bellard | int i, r;
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89 | 84631fd7 | bellard | uint32_t smram, addr; |
90 | 84631fd7 | bellard | |
91 | 0a3bacf3 | Juan Quintela | update_pam(d, 0xf0000, 0x100000, (d->dev.config[0x59] >> 4) & 3); |
92 | 84631fd7 | bellard | for(i = 0; i < 12; i++) { |
93 | 0a3bacf3 | Juan Quintela | r = (d->dev.config[(i >> 1) + 0x5a] >> ((i & 1) * 4)) & 3; |
94 | 84631fd7 | bellard | update_pam(d, 0xc0000 + 0x4000 * i, 0xc0000 + 0x4000 * (i + 1), r); |
95 | ee0ea1d0 | bellard | } |
96 | 0a3bacf3 | Juan Quintela | smram = d->dev.config[0x72];
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97 | 6c009fa4 | Juan Quintela | if ((d->smm_enabled && (smram & 0x08)) || (smram & 0x40)) { |
98 | 84631fd7 | bellard | cpu_register_physical_memory(0xa0000, 0x20000, 0xa0000); |
99 | 84631fd7 | bellard | } else {
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100 | 84631fd7 | bellard | for(addr = 0xa0000; addr < 0xc0000; addr += 4096) { |
101 | 5fafdf24 | ths | cpu_register_physical_memory(addr, 4096,
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102 | 6c009fa4 | Juan Quintela | d->isa_page_descs[(addr - 0xa0000) >> 12]); |
103 | ee0ea1d0 | bellard | } |
104 | ee0ea1d0 | bellard | } |
105 | ee0ea1d0 | bellard | } |
106 | ee0ea1d0 | bellard | |
107 | 0a3bacf3 | Juan Quintela | void i440fx_set_smm(PCII440FXState *d, int val) |
108 | ee0ea1d0 | bellard | { |
109 | ee0ea1d0 | bellard | val = (val != 0);
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110 | 6c009fa4 | Juan Quintela | if (d->smm_enabled != val) {
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111 | 6c009fa4 | Juan Quintela | d->smm_enabled = val; |
112 | ee0ea1d0 | bellard | i440fx_update_memory_mappings(d); |
113 | ee0ea1d0 | bellard | } |
114 | ee0ea1d0 | bellard | } |
115 | ee0ea1d0 | bellard | |
116 | ee0ea1d0 | bellard | |
117 | ee0ea1d0 | bellard | /* XXX: suppress when better memory API. We make the assumption that
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118 | ee0ea1d0 | bellard | no device (in particular the VGA) changes the memory mappings in
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119 | ee0ea1d0 | bellard | the 0xa0000-0x100000 range */
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120 | 0a3bacf3 | Juan Quintela | void i440fx_init_memory_mappings(PCII440FXState *d)
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121 | ee0ea1d0 | bellard | { |
122 | ee0ea1d0 | bellard | int i;
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123 | ee0ea1d0 | bellard | for(i = 0; i < 96; i++) { |
124 | 6c009fa4 | Juan Quintela | d->isa_page_descs[i] = cpu_get_physical_page_desc(0xa0000 + i * 0x1000); |
125 | ee0ea1d0 | bellard | } |
126 | ee0ea1d0 | bellard | } |
127 | ee0ea1d0 | bellard | |
128 | 0a3bacf3 | Juan Quintela | static void i440fx_write_config(PCIDevice *dev, |
129 | ee0ea1d0 | bellard | uint32_t address, uint32_t val, int len)
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130 | ee0ea1d0 | bellard | { |
131 | 0a3bacf3 | Juan Quintela | PCII440FXState *d = DO_UPCAST(PCII440FXState, dev, dev); |
132 | 0a3bacf3 | Juan Quintela | |
133 | ee0ea1d0 | bellard | /* XXX: implement SMRAM.D_LOCK */
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134 | 0a3bacf3 | Juan Quintela | pci_default_write_config(dev, address, val, len); |
135 | 84631fd7 | bellard | if ((address >= 0x59 && address <= 0x5f) || address == 0x72) |
136 | ee0ea1d0 | bellard | i440fx_update_memory_mappings(d); |
137 | ee0ea1d0 | bellard | } |
138 | ee0ea1d0 | bellard | |
139 | 0c7d19e5 | Juan Quintela | static int i440fx_load_old(QEMUFile* f, void *opaque, int version_id) |
140 | ee0ea1d0 | bellard | { |
141 | 0a3bacf3 | Juan Quintela | PCII440FXState *d = opaque; |
142 | 52fc1d83 | balrog | int ret, i;
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143 | ee0ea1d0 | bellard | |
144 | 0a3bacf3 | Juan Quintela | ret = pci_device_load(&d->dev, f); |
145 | ee0ea1d0 | bellard | if (ret < 0) |
146 | ee0ea1d0 | bellard | return ret;
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147 | ee0ea1d0 | bellard | i440fx_update_memory_mappings(d); |
148 | 6c009fa4 | Juan Quintela | qemu_get_8s(f, &d->smm_enabled); |
149 | 52fc1d83 | balrog | |
150 | da64182c | Juan Quintela | if (version_id == 2) |
151 | 52fc1d83 | balrog | for (i = 0; i < 4; i++) |
152 | 7cd9eee0 | Gerd Hoffmann | d->piix3->pci_irq_levels[i] = qemu_get_be32(f); |
153 | 52fc1d83 | balrog | |
154 | ee0ea1d0 | bellard | return 0; |
155 | ee0ea1d0 | bellard | } |
156 | ee0ea1d0 | bellard | |
157 | e59fb374 | Juan Quintela | static int i440fx_post_load(void *opaque, int version_id) |
158 | 0c7d19e5 | Juan Quintela | { |
159 | 0c7d19e5 | Juan Quintela | PCII440FXState *d = opaque; |
160 | 0c7d19e5 | Juan Quintela | |
161 | 0c7d19e5 | Juan Quintela | i440fx_update_memory_mappings(d); |
162 | 0c7d19e5 | Juan Quintela | return 0; |
163 | 0c7d19e5 | Juan Quintela | } |
164 | 0c7d19e5 | Juan Quintela | |
165 | 0c7d19e5 | Juan Quintela | static const VMStateDescription vmstate_i440fx = { |
166 | 0c7d19e5 | Juan Quintela | .name = "I440FX",
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167 | 0c7d19e5 | Juan Quintela | .version_id = 3,
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168 | 0c7d19e5 | Juan Quintela | .minimum_version_id = 3,
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169 | 0c7d19e5 | Juan Quintela | .minimum_version_id_old = 1,
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170 | 0c7d19e5 | Juan Quintela | .load_state_old = i440fx_load_old, |
171 | 752ff2fa | Juan Quintela | .post_load = i440fx_post_load, |
172 | 0c7d19e5 | Juan Quintela | .fields = (VMStateField []) { |
173 | 0c7d19e5 | Juan Quintela | VMSTATE_PCI_DEVICE(dev, PCII440FXState), |
174 | 0c7d19e5 | Juan Quintela | VMSTATE_UINT8(smm_enabled, PCII440FXState), |
175 | 0c7d19e5 | Juan Quintela | VMSTATE_END_OF_LIST() |
176 | 0c7d19e5 | Juan Quintela | } |
177 | 0c7d19e5 | Juan Quintela | }; |
178 | 0c7d19e5 | Juan Quintela | |
179 | 81a322d4 | Gerd Hoffmann | static int i440fx_pcihost_initfn(SysBusDevice *dev) |
180 | 502a5395 | pbrook | { |
181 | 8a14daa5 | Gerd Hoffmann | I440FXState *s = FROM_SYSBUS(I440FXState, dev); |
182 | 502a5395 | pbrook | |
183 | f08b32fe | Isaku Yamahata | pci_host_conf_register_ioport(0xcf8, s);
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184 | 502a5395 | pbrook | |
185 | 4f5e19e6 | Isaku Yamahata | pci_host_data_register_ioport(0xcfc, s);
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186 | 81a322d4 | Gerd Hoffmann | return 0; |
187 | 8a14daa5 | Gerd Hoffmann | } |
188 | 502a5395 | pbrook | |
189 | 0a3bacf3 | Juan Quintela | static int i440fx_initfn(PCIDevice *dev) |
190 | 8a14daa5 | Gerd Hoffmann | { |
191 | 0a3bacf3 | Juan Quintela | PCII440FXState *d = DO_UPCAST(PCII440FXState, dev, dev); |
192 | ee0ea1d0 | bellard | |
193 | 0a3bacf3 | Juan Quintela | pci_config_set_vendor_id(d->dev.config, PCI_VENDOR_ID_INTEL); |
194 | 0a3bacf3 | Juan Quintela | pci_config_set_device_id(d->dev.config, PCI_DEVICE_ID_INTEL_82441); |
195 | 0a3bacf3 | Juan Quintela | d->dev.config[0x08] = 0x02; // revision |
196 | 0a3bacf3 | Juan Quintela | pci_config_set_class(d->dev.config, PCI_CLASS_BRIDGE_HOST); |
197 | 0a3bacf3 | Juan Quintela | d->dev.config[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type
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198 | 0a3bacf3 | Juan Quintela | |
199 | 0a3bacf3 | Juan Quintela | d->dev.config[0x72] = 0x02; /* SMRAM */ |
200 | ee0ea1d0 | bellard | |
201 | 0c7d19e5 | Juan Quintela | vmstate_register(0, &vmstate_i440fx, d);
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202 | 81a322d4 | Gerd Hoffmann | return 0; |
203 | 8a14daa5 | Gerd Hoffmann | } |
204 | 8a14daa5 | Gerd Hoffmann | |
205 | 85a750ca | Juan Quintela | PCIBus *i440fx_init(PCII440FXState **pi440fx_state, int *piix3_devfn, qemu_irq *pic)
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206 | 8a14daa5 | Gerd Hoffmann | { |
207 | 8a14daa5 | Gerd Hoffmann | DeviceState *dev; |
208 | 8a14daa5 | Gerd Hoffmann | PCIBus *b; |
209 | 8a14daa5 | Gerd Hoffmann | PCIDevice *d; |
210 | 8a14daa5 | Gerd Hoffmann | I440FXState *s; |
211 | 7cd9eee0 | Gerd Hoffmann | PIIX3State *piix3; |
212 | 8a14daa5 | Gerd Hoffmann | |
213 | 8a14daa5 | Gerd Hoffmann | dev = qdev_create(NULL, "i440FX-pcihost"); |
214 | 8a14daa5 | Gerd Hoffmann | s = FROM_SYSBUS(I440FXState, sysbus_from_qdev(dev)); |
215 | 7cd9eee0 | Gerd Hoffmann | b = pci_bus_new(&s->busdev.qdev, NULL, 0); |
216 | 8a14daa5 | Gerd Hoffmann | s->bus = b; |
217 | e23a1b33 | Markus Armbruster | qdev_init_nofail(dev); |
218 | 8a14daa5 | Gerd Hoffmann | |
219 | 8a14daa5 | Gerd Hoffmann | d = pci_create_simple(b, 0, "i440FX"); |
220 | 0a3bacf3 | Juan Quintela | *pi440fx_state = DO_UPCAST(PCII440FXState, dev, d); |
221 | 8a14daa5 | Gerd Hoffmann | |
222 | 7cd9eee0 | Gerd Hoffmann | piix3 = DO_UPCAST(PIIX3State, dev, |
223 | fd83e9b9 | Juan Quintela | pci_create_simple(b, -1, "PIIX3")); |
224 | 7cd9eee0 | Gerd Hoffmann | piix3->pic = pic; |
225 | 7cd9eee0 | Gerd Hoffmann | pci_bus_irqs(b, piix3_set_irq, pci_slot_get_pirq, piix3, 4);
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226 | 7cd9eee0 | Gerd Hoffmann | (*pi440fx_state)->piix3 = piix3; |
227 | 7cd9eee0 | Gerd Hoffmann | |
228 | 7cd9eee0 | Gerd Hoffmann | *piix3_devfn = piix3->dev.devfn; |
229 | 85a750ca | Juan Quintela | |
230 | 502a5395 | pbrook | return b;
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231 | 502a5395 | pbrook | } |
232 | 502a5395 | pbrook | |
233 | 502a5395 | pbrook | /* PIIX3 PCI to ISA bridge */
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234 | 502a5395 | pbrook | |
235 | 5d4e84c8 | Juan Quintela | static void piix3_set_irq(void *opaque, int irq_num, int level) |
236 | 502a5395 | pbrook | { |
237 | d2b59317 | pbrook | int i, pic_irq, pic_level;
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238 | 7cd9eee0 | Gerd Hoffmann | PIIX3State *piix3 = opaque; |
239 | 502a5395 | pbrook | |
240 | 7cd9eee0 | Gerd Hoffmann | piix3->pci_irq_levels[irq_num] = level; |
241 | 502a5395 | pbrook | |
242 | 502a5395 | pbrook | /* now we change the pic irq level according to the piix irq mappings */
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243 | 502a5395 | pbrook | /* XXX: optimize */
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244 | 7cd9eee0 | Gerd Hoffmann | pic_irq = piix3->dev.config[0x60 + irq_num];
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245 | 502a5395 | pbrook | if (pic_irq < 16) { |
246 | d2b59317 | pbrook | /* The pic level is the logical OR of all the PCI irqs mapped
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247 | 502a5395 | pbrook | to it */
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248 | 502a5395 | pbrook | pic_level = 0;
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249 | d2b59317 | pbrook | for (i = 0; i < 4; i++) { |
250 | 7cd9eee0 | Gerd Hoffmann | if (pic_irq == piix3->dev.config[0x60 + i]) |
251 | 7cd9eee0 | Gerd Hoffmann | pic_level |= piix3->pci_irq_levels[i]; |
252 | d2b59317 | pbrook | } |
253 | 7cd9eee0 | Gerd Hoffmann | qemu_set_irq(piix3->pic[pic_irq], pic_level); |
254 | 502a5395 | pbrook | } |
255 | 502a5395 | pbrook | } |
256 | 502a5395 | pbrook | |
257 | 15a1956a | Gleb Natapov | static void piix3_reset(void *opaque) |
258 | 502a5395 | pbrook | { |
259 | fd37d881 | Juan Quintela | PIIX3State *d = opaque; |
260 | fd37d881 | Juan Quintela | uint8_t *pci_conf = d->dev.config; |
261 | 502a5395 | pbrook | |
262 | 502a5395 | pbrook | pci_conf[0x04] = 0x07; // master, memory and I/O |
263 | 502a5395 | pbrook | pci_conf[0x05] = 0x00; |
264 | 502a5395 | pbrook | pci_conf[0x06] = 0x00; |
265 | 502a5395 | pbrook | pci_conf[0x07] = 0x02; // PCI_status_devsel_medium |
266 | 502a5395 | pbrook | pci_conf[0x4c] = 0x4d; |
267 | 502a5395 | pbrook | pci_conf[0x4e] = 0x03; |
268 | 502a5395 | pbrook | pci_conf[0x4f] = 0x00; |
269 | 502a5395 | pbrook | pci_conf[0x60] = 0x80; |
270 | 477afee3 | aurel32 | pci_conf[0x61] = 0x80; |
271 | 477afee3 | aurel32 | pci_conf[0x62] = 0x80; |
272 | 477afee3 | aurel32 | pci_conf[0x63] = 0x80; |
273 | 502a5395 | pbrook | pci_conf[0x69] = 0x02; |
274 | 502a5395 | pbrook | pci_conf[0x70] = 0x80; |
275 | 502a5395 | pbrook | pci_conf[0x76] = 0x0c; |
276 | 502a5395 | pbrook | pci_conf[0x77] = 0x0c; |
277 | 502a5395 | pbrook | pci_conf[0x78] = 0x02; |
278 | 502a5395 | pbrook | pci_conf[0x79] = 0x00; |
279 | 502a5395 | pbrook | pci_conf[0x80] = 0x00; |
280 | 502a5395 | pbrook | pci_conf[0x82] = 0x00; |
281 | 502a5395 | pbrook | pci_conf[0xa0] = 0x08; |
282 | 502a5395 | pbrook | pci_conf[0xa2] = 0x00; |
283 | 502a5395 | pbrook | pci_conf[0xa3] = 0x00; |
284 | 502a5395 | pbrook | pci_conf[0xa4] = 0x00; |
285 | 502a5395 | pbrook | pci_conf[0xa5] = 0x00; |
286 | 502a5395 | pbrook | pci_conf[0xa6] = 0x00; |
287 | 502a5395 | pbrook | pci_conf[0xa7] = 0x00; |
288 | 502a5395 | pbrook | pci_conf[0xa8] = 0x0f; |
289 | 502a5395 | pbrook | pci_conf[0xaa] = 0x00; |
290 | 502a5395 | pbrook | pci_conf[0xab] = 0x00; |
291 | 502a5395 | pbrook | pci_conf[0xac] = 0x00; |
292 | 502a5395 | pbrook | pci_conf[0xae] = 0x00; |
293 | 15a1956a | Gleb Natapov | |
294 | 8372615d | Juan Quintela | memset(d->pci_irq_levels, 0, sizeof(d->pci_irq_levels)); |
295 | 502a5395 | pbrook | } |
296 | 502a5395 | pbrook | |
297 | d1f171bd | Juan Quintela | static const VMStateDescription vmstate_piix3 = { |
298 | d1f171bd | Juan Quintela | .name = "PIIX3",
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299 | d1f171bd | Juan Quintela | .version_id = 3,
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300 | d1f171bd | Juan Quintela | .minimum_version_id = 2,
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301 | d1f171bd | Juan Quintela | .minimum_version_id_old = 2,
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302 | d1f171bd | Juan Quintela | .fields = (VMStateField []) { |
303 | d1f171bd | Juan Quintela | VMSTATE_PCI_DEVICE(dev, PIIX3State), |
304 | d1f171bd | Juan Quintela | VMSTATE_INT32_ARRAY_V(pci_irq_levels, PIIX3State, 4, 3), |
305 | d1f171bd | Juan Quintela | VMSTATE_END_OF_LIST() |
306 | da64182c | Juan Quintela | } |
307 | d1f171bd | Juan Quintela | }; |
308 | 1941d19c | bellard | |
309 | fd37d881 | Juan Quintela | static int piix3_initfn(PCIDevice *dev) |
310 | 502a5395 | pbrook | { |
311 | fd37d881 | Juan Quintela | PIIX3State *d = DO_UPCAST(PIIX3State, dev, dev); |
312 | 502a5395 | pbrook | uint8_t *pci_conf; |
313 | 502a5395 | pbrook | |
314 | fd37d881 | Juan Quintela | isa_bus_new(&d->dev.qdev); |
315 | d1f171bd | Juan Quintela | vmstate_register(0, &vmstate_piix3, d);
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316 | 502a5395 | pbrook | |
317 | fd37d881 | Juan Quintela | pci_conf = d->dev.config; |
318 | deb54399 | aliguori | pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL); |
319 | deb54399 | aliguori | pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82371SB_0); // 82371SB PIIX3 PCI-to-ISA bridge (Step A1)
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320 | 173a543b | blueswir1 | pci_config_set_class(pci_conf, PCI_CLASS_BRIDGE_ISA); |
321 | 6407f373 | Isaku Yamahata | pci_conf[PCI_HEADER_TYPE] = |
322 | 6407f373 | Isaku Yamahata | PCI_HEADER_TYPE_NORMAL | PCI_HEADER_TYPE_MULTI_FUNCTION; // header_type = PCI_multifunction, generic
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323 | 502a5395 | pbrook | |
324 | a08d4367 | Jan Kiszka | qemu_register_reset(piix3_reset, d); |
325 | 81a322d4 | Gerd Hoffmann | return 0; |
326 | 502a5395 | pbrook | } |
327 | 5c2b87e3 | ths | |
328 | 8a14daa5 | Gerd Hoffmann | static PCIDeviceInfo i440fx_info[] = {
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329 | 8a14daa5 | Gerd Hoffmann | { |
330 | 8a14daa5 | Gerd Hoffmann | .qdev.name = "i440FX",
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331 | 8a14daa5 | Gerd Hoffmann | .qdev.desc = "Host bridge",
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332 | 0a3bacf3 | Juan Quintela | .qdev.size = sizeof(PCII440FXState),
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333 | 8a14daa5 | Gerd Hoffmann | .qdev.no_user = 1,
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334 | 8a14daa5 | Gerd Hoffmann | .init = i440fx_initfn, |
335 | 8a14daa5 | Gerd Hoffmann | .config_write = i440fx_write_config, |
336 | 8a14daa5 | Gerd Hoffmann | },{ |
337 | 8a14daa5 | Gerd Hoffmann | .qdev.name = "PIIX3",
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338 | 8a14daa5 | Gerd Hoffmann | .qdev.desc = "ISA bridge",
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339 | fd37d881 | Juan Quintela | .qdev.size = sizeof(PIIX3State),
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340 | 8a14daa5 | Gerd Hoffmann | .qdev.no_user = 1,
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341 | 8a14daa5 | Gerd Hoffmann | .init = piix3_initfn, |
342 | 8a14daa5 | Gerd Hoffmann | },{ |
343 | 8a14daa5 | Gerd Hoffmann | /* end of list */
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344 | 8a14daa5 | Gerd Hoffmann | } |
345 | 8a14daa5 | Gerd Hoffmann | }; |
346 | 8a14daa5 | Gerd Hoffmann | |
347 | 8a14daa5 | Gerd Hoffmann | static SysBusDeviceInfo i440fx_pcihost_info = {
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348 | 8a14daa5 | Gerd Hoffmann | .init = i440fx_pcihost_initfn, |
349 | 8a14daa5 | Gerd Hoffmann | .qdev.name = "i440FX-pcihost",
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350 | 8a14daa5 | Gerd Hoffmann | .qdev.size = sizeof(I440FXState),
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351 | 8a14daa5 | Gerd Hoffmann | .qdev.no_user = 1,
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352 | 8a14daa5 | Gerd Hoffmann | }; |
353 | 8a14daa5 | Gerd Hoffmann | |
354 | 8a14daa5 | Gerd Hoffmann | static void i440fx_register(void) |
355 | 8a14daa5 | Gerd Hoffmann | { |
356 | 8a14daa5 | Gerd Hoffmann | sysbus_register_withprop(&i440fx_pcihost_info); |
357 | 8a14daa5 | Gerd Hoffmann | pci_qdev_register_many(i440fx_info); |
358 | 8a14daa5 | Gerd Hoffmann | } |
359 | 8a14daa5 | Gerd Hoffmann | device_init(i440fx_register); |