root / hw / mainstone.h @ a15fdf86
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/*
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* PXA270-based Intel Mainstone platforms.
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*
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* Copyright (c) 2007 by Armin Kuster <akuster@kama-aina.net> or
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* <akuster@mvista.com>
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*
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* This code is licensed under the GNU GPL v2.
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*/
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#ifndef __MAINSTONE_H__
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#define __MAINSTONE_H__
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/* Device addresses */
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#define MST_FPGA_PHYS 0x08000000 |
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#define MST_ETH_PHYS 0x10000300 |
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#define MST_FLASH_0 0x00000000 |
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#define MST_FLASH_1 0x04000000 |
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/* IRQ definitions */
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#define MMC_IRQ 0 |
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#define USIM_IRQ 1 |
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#define USBC_IRQ 2 |
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#define ETHERNET_IRQ 3 |
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#define AC97_IRQ 4 |
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#define PEN_IRQ 5 |
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#define MSINS_IRQ 6 |
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#define EXBRD_IRQ 7 |
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#define S0_CD_IRQ 9 |
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#define S0_STSCHG_IRQ 10 |
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#define S0_IRQ 11 |
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#define S1_CD_IRQ 13 |
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#define S1_STSCHG_IRQ 14 |
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#define S1_IRQ 15 |
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extern qemu_irq
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*mst_irq_init(PXA2xxState *cpu, uint32_t base, int irq);
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#endif /* __MAINSTONE_H__ */ |