Archipelago » qemu

/* Bit usage in the TB flags field: */

#define ARM_TBFLAG_THUMB_SHIFT      0

#define ARM_TBFLAG_THUMB_MASK       (1 << ARM_TBFLAG_THUMB_SHIFT)

#define ARM_TBFLAG_VECLEN_SHIFT     1

#define ARM_TBFLAG_VECLEN_MASK      (0x7 << ARM_TBFLAG_VECLEN_SHIFT)

#define ARM_TBFLAG_VECSTRIDE_SHIFT  4

#define ARM_TBFLAG_VECSTRIDE_MASK   (0x3 << ARM_TBFLAG_VECSTRIDE_SHIFT)

#define ARM_TBFLAG_PRIV_SHIFT       6

#define ARM_TBFLAG_PRIV_MASK        (1 << ARM_TBFLAG_PRIV_SHIFT)

#define ARM_TBFLAG_VFPEN_SHIFT      7

#define ARM_TBFLAG_VFPEN_MASK       (1 << ARM_TBFLAG_VFPEN_SHIFT)

#define ARM_TBFLAG_CONDEXEC_SHIFT   8

#define ARM_TBFLAG_CONDEXEC_MASK    (0xff << ARM_TBFLAG_CONDEXEC_SHIFT)

/* Bits 31..16 are currently unused. */

/* some convenience accessor macros */

#define ARM_TBFLAG_THUMB(F) \

    (((F) & ARM_TBFLAG_THUMB_MASK) >> ARM_TBFLAG_THUMB_SHIFT)

#define ARM_TBFLAG_VECLEN(F) \

    (((F) & ARM_TBFLAG_VECLEN_MASK) >> ARM_TBFLAG_VECLEN_SHIFT)

#define ARM_TBFLAG_VECSTRIDE(F) \

    (((F) & ARM_TBFLAG_VECSTRIDE_MASK) >> ARM_TBFLAG_VECSTRIDE_SHIFT)

#define ARM_TBFLAG_PRIV(F) \

    (((F) & ARM_TBFLAG_PRIV_MASK) >> ARM_TBFLAG_PRIV_SHIFT)

#define ARM_TBFLAG_VFPEN(F) \

    (((F) & ARM_TBFLAG_VFPEN_MASK) >> ARM_TBFLAG_VFPEN_SHIFT)

#define ARM_TBFLAG_CONDEXEC(F) \

    (((F) & ARM_TBFLAG_CONDEXEC_MASK) >> ARM_TBFLAG_CONDEXEC_SHIFT)

    *flags = (env->thumb << ARM_TBFLAG_THUMB_SHIFT)

        | (env->vfp.vec_len << ARM_TBFLAG_VECLEN_SHIFT)

        | (env->vfp.vec_stride << ARM_TBFLAG_VECSTRIDE_SHIFT)

        | (env->condexec_bits << ARM_TBFLAG_CONDEXEC_SHIFT);

    if ((env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR) {

        *flags |= ARM_TBFLAG_PRIV_MASK;

    }

    if (env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30)) {

        *flags |= ARM_TBFLAG_VFPEN_MASK;

    }