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1 | b92e5a22 | bellard | /*
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2 | b92e5a22 | bellard | * Software MMU support
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3 | 5fafdf24 | ths | *
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4 | b92e5a22 | bellard | * Copyright (c) 2003 Fabrice Bellard
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5 | b92e5a22 | bellard | *
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6 | b92e5a22 | bellard | * This library is free software; you can redistribute it and/or
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7 | b92e5a22 | bellard | * modify it under the terms of the GNU Lesser General Public
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8 | b92e5a22 | bellard | * License as published by the Free Software Foundation; either
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9 | b92e5a22 | bellard | * version 2 of the License, or (at your option) any later version.
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10 | b92e5a22 | bellard | *
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11 | b92e5a22 | bellard | * This library is distributed in the hope that it will be useful,
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12 | b92e5a22 | bellard | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 | b92e5a22 | bellard | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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14 | b92e5a22 | bellard | * Lesser General Public License for more details.
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15 | b92e5a22 | bellard | *
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16 | b92e5a22 | bellard | * You should have received a copy of the GNU Lesser General Public
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17 | 8167ee88 | Blue Swirl | * License along with this library; if not, see <http://www.gnu.org/licenses/>.
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18 | b92e5a22 | bellard | */
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19 | 29e922b6 | Blue Swirl | #include "qemu-timer.h" |
20 | 29e922b6 | Blue Swirl | |
21 | b92e5a22 | bellard | #define DATA_SIZE (1 << SHIFT) |
22 | b92e5a22 | bellard | |
23 | b92e5a22 | bellard | #if DATA_SIZE == 8 |
24 | b92e5a22 | bellard | #define SUFFIX q
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25 | 61382a50 | bellard | #define USUFFIX q
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26 | b92e5a22 | bellard | #define DATA_TYPE uint64_t
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27 | b92e5a22 | bellard | #elif DATA_SIZE == 4 |
28 | b92e5a22 | bellard | #define SUFFIX l
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29 | 61382a50 | bellard | #define USUFFIX l
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30 | b92e5a22 | bellard | #define DATA_TYPE uint32_t
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31 | b92e5a22 | bellard | #elif DATA_SIZE == 2 |
32 | b92e5a22 | bellard | #define SUFFIX w
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33 | 61382a50 | bellard | #define USUFFIX uw
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34 | b92e5a22 | bellard | #define DATA_TYPE uint16_t
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35 | b92e5a22 | bellard | #elif DATA_SIZE == 1 |
36 | b92e5a22 | bellard | #define SUFFIX b
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37 | 61382a50 | bellard | #define USUFFIX ub
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38 | b92e5a22 | bellard | #define DATA_TYPE uint8_t
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39 | b92e5a22 | bellard | #else
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40 | b92e5a22 | bellard | #error unsupported data size
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41 | b92e5a22 | bellard | #endif
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42 | b92e5a22 | bellard | |
43 | b769d8fe | bellard | #ifdef SOFTMMU_CODE_ACCESS
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44 | b769d8fe | bellard | #define READ_ACCESS_TYPE 2 |
45 | 84b7b8e7 | bellard | #define ADDR_READ addr_code
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46 | b769d8fe | bellard | #else
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47 | b769d8fe | bellard | #define READ_ACCESS_TYPE 0 |
48 | 84b7b8e7 | bellard | #define ADDR_READ addr_read
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49 | b769d8fe | bellard | #endif
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50 | b769d8fe | bellard | |
51 | 5fafdf24 | ths | static DATA_TYPE glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(target_ulong addr,
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52 | 6ebbf390 | j_mayer | int mmu_idx,
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53 | 61382a50 | bellard | void *retaddr);
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54 | c227f099 | Anthony Liguori | static inline DATA_TYPE glue(io_read, SUFFIX)(target_phys_addr_t physaddr, |
55 | 2e70f6ef | pbrook | target_ulong addr, |
56 | 2e70f6ef | pbrook | void *retaddr)
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57 | b92e5a22 | bellard | { |
58 | b92e5a22 | bellard | DATA_TYPE res; |
59 | b92e5a22 | bellard | int index;
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60 | 0f459d16 | pbrook | index = (physaddr >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1);
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61 | 0f459d16 | pbrook | physaddr = (physaddr & TARGET_PAGE_MASK) + addr; |
62 | 2e70f6ef | pbrook | env->mem_io_pc = (unsigned long)retaddr; |
63 | 2e70f6ef | pbrook | if (index > (IO_MEM_NOTDIRTY >> IO_MEM_SHIFT)
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64 | 2e70f6ef | pbrook | && !can_do_io(env)) { |
65 | 2e70f6ef | pbrook | cpu_io_recompile(env, retaddr); |
66 | 2e70f6ef | pbrook | } |
67 | b92e5a22 | bellard | |
68 | db8886d3 | aliguori | env->mem_io_vaddr = addr; |
69 | b92e5a22 | bellard | #if SHIFT <= 2 |
70 | a4193c8a | bellard | res = io_mem_read[index][SHIFT](io_mem_opaque[index], physaddr); |
71 | b92e5a22 | bellard | #else
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72 | b92e5a22 | bellard | #ifdef TARGET_WORDS_BIGENDIAN
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73 | a4193c8a | bellard | res = (uint64_t)io_mem_read[index][2](io_mem_opaque[index], physaddr) << 32; |
74 | a4193c8a | bellard | res |= io_mem_read[index][2](io_mem_opaque[index], physaddr + 4); |
75 | b92e5a22 | bellard | #else
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76 | a4193c8a | bellard | res = io_mem_read[index][2](io_mem_opaque[index], physaddr);
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77 | a4193c8a | bellard | res |= (uint64_t)io_mem_read[index][2](io_mem_opaque[index], physaddr + 4) << 32; |
78 | b92e5a22 | bellard | #endif
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79 | b92e5a22 | bellard | #endif /* SHIFT > 2 */ |
80 | b92e5a22 | bellard | return res;
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81 | b92e5a22 | bellard | } |
82 | b92e5a22 | bellard | |
83 | b92e5a22 | bellard | /* handle all cases except unaligned access which span two pages */
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84 | d656469f | bellard | DATA_TYPE REGPARM glue(glue(__ld, SUFFIX), MMUSUFFIX)(target_ulong addr, |
85 | d656469f | bellard | int mmu_idx)
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86 | b92e5a22 | bellard | { |
87 | b92e5a22 | bellard | DATA_TYPE res; |
88 | 61382a50 | bellard | int index;
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89 | c27004ec | bellard | target_ulong tlb_addr; |
90 | c227f099 | Anthony Liguori | target_phys_addr_t addend; |
91 | b92e5a22 | bellard | void *retaddr;
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92 | 3b46e624 | ths | |
93 | b92e5a22 | bellard | /* test if there is match for unaligned or IO access */
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94 | b92e5a22 | bellard | /* XXX: could done more in memory macro in a non portable way */
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95 | b92e5a22 | bellard | index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
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96 | b92e5a22 | bellard | redo:
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97 | 6ebbf390 | j_mayer | tlb_addr = env->tlb_table[mmu_idx][index].ADDR_READ; |
98 | b92e5a22 | bellard | if ((addr & TARGET_PAGE_MASK) == (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
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99 | b92e5a22 | bellard | if (tlb_addr & ~TARGET_PAGE_MASK) {
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100 | b92e5a22 | bellard | /* IO access */
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101 | b92e5a22 | bellard | if ((addr & (DATA_SIZE - 1)) != 0) |
102 | b92e5a22 | bellard | goto do_unaligned_access;
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103 | 2e70f6ef | pbrook | retaddr = GETPC(); |
104 | 0f459d16 | pbrook | addend = env->iotlb[mmu_idx][index]; |
105 | 2e70f6ef | pbrook | res = glue(io_read, SUFFIX)(addend, addr, retaddr); |
106 | 98699967 | bellard | } else if (((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1) >= TARGET_PAGE_SIZE) { |
107 | b92e5a22 | bellard | /* slow unaligned access (it spans two pages or IO) */
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108 | b92e5a22 | bellard | do_unaligned_access:
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109 | 61382a50 | bellard | retaddr = GETPC(); |
110 | a64d4718 | bellard | #ifdef ALIGNED_ONLY
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111 | 6ebbf390 | j_mayer | do_unaligned_access(addr, READ_ACCESS_TYPE, mmu_idx, retaddr); |
112 | a64d4718 | bellard | #endif
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113 | 5fafdf24 | ths | res = glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(addr, |
114 | 6ebbf390 | j_mayer | mmu_idx, retaddr); |
115 | b92e5a22 | bellard | } else {
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116 | a64d4718 | bellard | /* unaligned/aligned access in the same page */
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117 | a64d4718 | bellard | #ifdef ALIGNED_ONLY
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118 | a64d4718 | bellard | if ((addr & (DATA_SIZE - 1)) != 0) { |
119 | a64d4718 | bellard | retaddr = GETPC(); |
120 | 6ebbf390 | j_mayer | do_unaligned_access(addr, READ_ACCESS_TYPE, mmu_idx, retaddr); |
121 | a64d4718 | bellard | } |
122 | a64d4718 | bellard | #endif
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123 | 0f459d16 | pbrook | addend = env->tlb_table[mmu_idx][index].addend; |
124 | 0f459d16 | pbrook | res = glue(glue(ld, USUFFIX), _raw)((uint8_t *)(long)(addr+addend));
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125 | b92e5a22 | bellard | } |
126 | b92e5a22 | bellard | } else {
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127 | b92e5a22 | bellard | /* the page is not in the TLB : fill it */
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128 | 61382a50 | bellard | retaddr = GETPC(); |
129 | a64d4718 | bellard | #ifdef ALIGNED_ONLY
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130 | a64d4718 | bellard | if ((addr & (DATA_SIZE - 1)) != 0) |
131 | 6ebbf390 | j_mayer | do_unaligned_access(addr, READ_ACCESS_TYPE, mmu_idx, retaddr); |
132 | a64d4718 | bellard | #endif
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133 | 6ebbf390 | j_mayer | tlb_fill(addr, READ_ACCESS_TYPE, mmu_idx, retaddr); |
134 | b92e5a22 | bellard | goto redo;
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135 | b92e5a22 | bellard | } |
136 | b92e5a22 | bellard | return res;
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137 | b92e5a22 | bellard | } |
138 | b92e5a22 | bellard | |
139 | b92e5a22 | bellard | /* handle all unaligned cases */
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140 | 5fafdf24 | ths | static DATA_TYPE glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(target_ulong addr,
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141 | 6ebbf390 | j_mayer | int mmu_idx,
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142 | 61382a50 | bellard | void *retaddr)
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143 | b92e5a22 | bellard | { |
144 | b92e5a22 | bellard | DATA_TYPE res, res1, res2; |
145 | 61382a50 | bellard | int index, shift;
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146 | c227f099 | Anthony Liguori | target_phys_addr_t addend; |
147 | c27004ec | bellard | target_ulong tlb_addr, addr1, addr2; |
148 | b92e5a22 | bellard | |
149 | b92e5a22 | bellard | index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
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150 | b92e5a22 | bellard | redo:
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151 | 6ebbf390 | j_mayer | tlb_addr = env->tlb_table[mmu_idx][index].ADDR_READ; |
152 | b92e5a22 | bellard | if ((addr & TARGET_PAGE_MASK) == (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
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153 | b92e5a22 | bellard | if (tlb_addr & ~TARGET_PAGE_MASK) {
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154 | b92e5a22 | bellard | /* IO access */
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155 | b92e5a22 | bellard | if ((addr & (DATA_SIZE - 1)) != 0) |
156 | b92e5a22 | bellard | goto do_unaligned_access;
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157 | 0f459d16 | pbrook | addend = env->iotlb[mmu_idx][index]; |
158 | 2e70f6ef | pbrook | res = glue(io_read, SUFFIX)(addend, addr, retaddr); |
159 | 98699967 | bellard | } else if (((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1) >= TARGET_PAGE_SIZE) { |
160 | b92e5a22 | bellard | do_unaligned_access:
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161 | b92e5a22 | bellard | /* slow unaligned access (it spans two pages) */
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162 | b92e5a22 | bellard | addr1 = addr & ~(DATA_SIZE - 1);
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163 | b92e5a22 | bellard | addr2 = addr1 + DATA_SIZE; |
164 | 5fafdf24 | ths | res1 = glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(addr1, |
165 | 6ebbf390 | j_mayer | mmu_idx, retaddr); |
166 | 5fafdf24 | ths | res2 = glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(addr2, |
167 | 6ebbf390 | j_mayer | mmu_idx, retaddr); |
168 | b92e5a22 | bellard | shift = (addr & (DATA_SIZE - 1)) * 8; |
169 | b92e5a22 | bellard | #ifdef TARGET_WORDS_BIGENDIAN
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170 | b92e5a22 | bellard | res = (res1 << shift) | (res2 >> ((DATA_SIZE * 8) - shift));
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171 | b92e5a22 | bellard | #else
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172 | b92e5a22 | bellard | res = (res1 >> shift) | (res2 << ((DATA_SIZE * 8) - shift));
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173 | b92e5a22 | bellard | #endif
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174 | 6986f88c | bellard | res = (DATA_TYPE)res; |
175 | b92e5a22 | bellard | } else {
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176 | b92e5a22 | bellard | /* unaligned/aligned access in the same page */
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177 | 0f459d16 | pbrook | addend = env->tlb_table[mmu_idx][index].addend; |
178 | 0f459d16 | pbrook | res = glue(glue(ld, USUFFIX), _raw)((uint8_t *)(long)(addr+addend));
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179 | b92e5a22 | bellard | } |
180 | b92e5a22 | bellard | } else {
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181 | b92e5a22 | bellard | /* the page is not in the TLB : fill it */
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182 | 6ebbf390 | j_mayer | tlb_fill(addr, READ_ACCESS_TYPE, mmu_idx, retaddr); |
183 | b92e5a22 | bellard | goto redo;
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184 | b92e5a22 | bellard | } |
185 | b92e5a22 | bellard | return res;
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186 | b92e5a22 | bellard | } |
187 | b92e5a22 | bellard | |
188 | b769d8fe | bellard | #ifndef SOFTMMU_CODE_ACCESS
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189 | b769d8fe | bellard | |
190 | 5fafdf24 | ths | static void glue(glue(slow_st, SUFFIX), MMUSUFFIX)(target_ulong addr, |
191 | 5fafdf24 | ths | DATA_TYPE val, |
192 | 6ebbf390 | j_mayer | int mmu_idx,
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193 | b769d8fe | bellard | void *retaddr);
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194 | b769d8fe | bellard | |
195 | c227f099 | Anthony Liguori | static inline void glue(io_write, SUFFIX)(target_phys_addr_t physaddr, |
196 | b769d8fe | bellard | DATA_TYPE val, |
197 | 0f459d16 | pbrook | target_ulong addr, |
198 | b769d8fe | bellard | void *retaddr)
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199 | b769d8fe | bellard | { |
200 | b769d8fe | bellard | int index;
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201 | 0f459d16 | pbrook | index = (physaddr >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1);
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202 | 0f459d16 | pbrook | physaddr = (physaddr & TARGET_PAGE_MASK) + addr; |
203 | 2e70f6ef | pbrook | if (index > (IO_MEM_NOTDIRTY >> IO_MEM_SHIFT)
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204 | 2e70f6ef | pbrook | && !can_do_io(env)) { |
205 | 2e70f6ef | pbrook | cpu_io_recompile(env, retaddr); |
206 | 2e70f6ef | pbrook | } |
207 | b769d8fe | bellard | |
208 | 2e70f6ef | pbrook | env->mem_io_vaddr = addr; |
209 | 2e70f6ef | pbrook | env->mem_io_pc = (unsigned long)retaddr; |
210 | b769d8fe | bellard | #if SHIFT <= 2 |
211 | b769d8fe | bellard | io_mem_write[index][SHIFT](io_mem_opaque[index], physaddr, val); |
212 | b769d8fe | bellard | #else
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213 | b769d8fe | bellard | #ifdef TARGET_WORDS_BIGENDIAN
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214 | b769d8fe | bellard | io_mem_write[index][2](io_mem_opaque[index], physaddr, val >> 32); |
215 | b769d8fe | bellard | io_mem_write[index][2](io_mem_opaque[index], physaddr + 4, val); |
216 | b769d8fe | bellard | #else
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217 | b769d8fe | bellard | io_mem_write[index][2](io_mem_opaque[index], physaddr, val);
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218 | b769d8fe | bellard | io_mem_write[index][2](io_mem_opaque[index], physaddr + 4, val >> 32); |
219 | b769d8fe | bellard | #endif
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220 | b769d8fe | bellard | #endif /* SHIFT > 2 */ |
221 | b769d8fe | bellard | } |
222 | b92e5a22 | bellard | |
223 | d656469f | bellard | void REGPARM glue(glue(__st, SUFFIX), MMUSUFFIX)(target_ulong addr,
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224 | d656469f | bellard | DATA_TYPE val, |
225 | d656469f | bellard | int mmu_idx)
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226 | b92e5a22 | bellard | { |
227 | c227f099 | Anthony Liguori | target_phys_addr_t addend; |
228 | c27004ec | bellard | target_ulong tlb_addr; |
229 | b92e5a22 | bellard | void *retaddr;
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230 | 61382a50 | bellard | int index;
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231 | 3b46e624 | ths | |
232 | b92e5a22 | bellard | index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
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233 | b92e5a22 | bellard | redo:
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234 | 6ebbf390 | j_mayer | tlb_addr = env->tlb_table[mmu_idx][index].addr_write; |
235 | b92e5a22 | bellard | if ((addr & TARGET_PAGE_MASK) == (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
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236 | b92e5a22 | bellard | if (tlb_addr & ~TARGET_PAGE_MASK) {
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237 | b92e5a22 | bellard | /* IO access */
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238 | b92e5a22 | bellard | if ((addr & (DATA_SIZE - 1)) != 0) |
239 | b92e5a22 | bellard | goto do_unaligned_access;
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240 | d720b93d | bellard | retaddr = GETPC(); |
241 | 0f459d16 | pbrook | addend = env->iotlb[mmu_idx][index]; |
242 | 0f459d16 | pbrook | glue(io_write, SUFFIX)(addend, val, addr, retaddr); |
243 | 98699967 | bellard | } else if (((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1) >= TARGET_PAGE_SIZE) { |
244 | b92e5a22 | bellard | do_unaligned_access:
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245 | 61382a50 | bellard | retaddr = GETPC(); |
246 | a64d4718 | bellard | #ifdef ALIGNED_ONLY
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247 | 6ebbf390 | j_mayer | do_unaligned_access(addr, 1, mmu_idx, retaddr);
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248 | a64d4718 | bellard | #endif
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249 | 5fafdf24 | ths | glue(glue(slow_st, SUFFIX), MMUSUFFIX)(addr, val, |
250 | 6ebbf390 | j_mayer | mmu_idx, retaddr); |
251 | b92e5a22 | bellard | } else {
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252 | b92e5a22 | bellard | /* aligned/unaligned access in the same page */
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253 | a64d4718 | bellard | #ifdef ALIGNED_ONLY
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254 | a64d4718 | bellard | if ((addr & (DATA_SIZE - 1)) != 0) { |
255 | a64d4718 | bellard | retaddr = GETPC(); |
256 | 6ebbf390 | j_mayer | do_unaligned_access(addr, 1, mmu_idx, retaddr);
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257 | a64d4718 | bellard | } |
258 | a64d4718 | bellard | #endif
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259 | 0f459d16 | pbrook | addend = env->tlb_table[mmu_idx][index].addend; |
260 | 0f459d16 | pbrook | glue(glue(st, SUFFIX), _raw)((uint8_t *)(long)(addr+addend), val);
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261 | b92e5a22 | bellard | } |
262 | b92e5a22 | bellard | } else {
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263 | b92e5a22 | bellard | /* the page is not in the TLB : fill it */
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264 | 61382a50 | bellard | retaddr = GETPC(); |
265 | a64d4718 | bellard | #ifdef ALIGNED_ONLY
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266 | a64d4718 | bellard | if ((addr & (DATA_SIZE - 1)) != 0) |
267 | 6ebbf390 | j_mayer | do_unaligned_access(addr, 1, mmu_idx, retaddr);
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268 | a64d4718 | bellard | #endif
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269 | 6ebbf390 | j_mayer | tlb_fill(addr, 1, mmu_idx, retaddr);
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270 | b92e5a22 | bellard | goto redo;
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271 | b92e5a22 | bellard | } |
272 | b92e5a22 | bellard | } |
273 | b92e5a22 | bellard | |
274 | b92e5a22 | bellard | /* handles all unaligned cases */
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275 | 5fafdf24 | ths | static void glue(glue(slow_st, SUFFIX), MMUSUFFIX)(target_ulong addr, |
276 | 61382a50 | bellard | DATA_TYPE val, |
277 | 6ebbf390 | j_mayer | int mmu_idx,
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278 | 61382a50 | bellard | void *retaddr)
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279 | b92e5a22 | bellard | { |
280 | c227f099 | Anthony Liguori | target_phys_addr_t addend; |
281 | c27004ec | bellard | target_ulong tlb_addr; |
282 | 61382a50 | bellard | int index, i;
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283 | b92e5a22 | bellard | |
284 | b92e5a22 | bellard | index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
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285 | b92e5a22 | bellard | redo:
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286 | 6ebbf390 | j_mayer | tlb_addr = env->tlb_table[mmu_idx][index].addr_write; |
287 | b92e5a22 | bellard | if ((addr & TARGET_PAGE_MASK) == (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
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288 | b92e5a22 | bellard | if (tlb_addr & ~TARGET_PAGE_MASK) {
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289 | b92e5a22 | bellard | /* IO access */
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290 | b92e5a22 | bellard | if ((addr & (DATA_SIZE - 1)) != 0) |
291 | b92e5a22 | bellard | goto do_unaligned_access;
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292 | 0f459d16 | pbrook | addend = env->iotlb[mmu_idx][index]; |
293 | 0f459d16 | pbrook | glue(io_write, SUFFIX)(addend, val, addr, retaddr); |
294 | 98699967 | bellard | } else if (((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1) >= TARGET_PAGE_SIZE) { |
295 | b92e5a22 | bellard | do_unaligned_access:
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296 | b92e5a22 | bellard | /* XXX: not efficient, but simple */
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297 | 6c41b272 | balrog | /* Note: relies on the fact that tlb_fill() does not remove the
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298 | 6c41b272 | balrog | * previous page from the TLB cache. */
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299 | 7221fa98 | balrog | for(i = DATA_SIZE - 1; i >= 0; i--) { |
300 | b92e5a22 | bellard | #ifdef TARGET_WORDS_BIGENDIAN
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301 | 5fafdf24 | ths | glue(slow_stb, MMUSUFFIX)(addr + i, val >> (((DATA_SIZE - 1) * 8) - (i * 8)), |
302 | 6ebbf390 | j_mayer | mmu_idx, retaddr); |
303 | b92e5a22 | bellard | #else
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304 | 5fafdf24 | ths | glue(slow_stb, MMUSUFFIX)(addr + i, val >> (i * 8),
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305 | 6ebbf390 | j_mayer | mmu_idx, retaddr); |
306 | b92e5a22 | bellard | #endif
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307 | b92e5a22 | bellard | } |
308 | b92e5a22 | bellard | } else {
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309 | b92e5a22 | bellard | /* aligned/unaligned access in the same page */
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310 | 0f459d16 | pbrook | addend = env->tlb_table[mmu_idx][index].addend; |
311 | 0f459d16 | pbrook | glue(glue(st, SUFFIX), _raw)((uint8_t *)(long)(addr+addend), val);
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312 | b92e5a22 | bellard | } |
313 | b92e5a22 | bellard | } else {
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314 | b92e5a22 | bellard | /* the page is not in the TLB : fill it */
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315 | 6ebbf390 | j_mayer | tlb_fill(addr, 1, mmu_idx, retaddr);
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316 | b92e5a22 | bellard | goto redo;
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317 | b92e5a22 | bellard | } |
318 | b92e5a22 | bellard | } |
319 | b92e5a22 | bellard | |
320 | b769d8fe | bellard | #endif /* !defined(SOFTMMU_CODE_ACCESS) */ |
321 | b769d8fe | bellard | |
322 | b769d8fe | bellard | #undef READ_ACCESS_TYPE
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323 | b92e5a22 | bellard | #undef SHIFT
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324 | b92e5a22 | bellard | #undef DATA_TYPE
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325 | b92e5a22 | bellard | #undef SUFFIX
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326 | 61382a50 | bellard | #undef USUFFIX
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327 | b92e5a22 | bellard | #undef DATA_SIZE
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328 | 84b7b8e7 | bellard | #undef ADDR_READ |