root / hw / ioh3420.c @ a1bc20df
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1 | 8135aeed | Isaku Yamahata | /*
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2 | 8135aeed | Isaku Yamahata | * ioh3420.c
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3 | 8135aeed | Isaku Yamahata | * Intel X58 north bridge IOH
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4 | 8135aeed | Isaku Yamahata | * PCI Express root port device id 3420
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5 | 8135aeed | Isaku Yamahata | *
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6 | 8135aeed | Isaku Yamahata | * Copyright (c) 2010 Isaku Yamahata <yamahata at valinux co jp>
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7 | 8135aeed | Isaku Yamahata | * VA Linux Systems Japan K.K.
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8 | 8135aeed | Isaku Yamahata | *
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9 | 8135aeed | Isaku Yamahata | * This program is free software; you can redistribute it and/or modify
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10 | 8135aeed | Isaku Yamahata | * it under the terms of the GNU General Public License as published by
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11 | 8135aeed | Isaku Yamahata | * the Free Software Foundation; either version 2 of the License, or
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12 | 8135aeed | Isaku Yamahata | * (at your option) any later version.
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13 | 8135aeed | Isaku Yamahata | *
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14 | 8135aeed | Isaku Yamahata | * This program is distributed in the hope that it will be useful,
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15 | 8135aeed | Isaku Yamahata | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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16 | 8135aeed | Isaku Yamahata | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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17 | 8135aeed | Isaku Yamahata | * GNU General Public License for more details.
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18 | 8135aeed | Isaku Yamahata | *
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19 | 8135aeed | Isaku Yamahata | * You should have received a copy of the GNU General Public License along
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20 | 8135aeed | Isaku Yamahata | * with this program; if not, see <http://www.gnu.org/licenses/>.
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21 | 8135aeed | Isaku Yamahata | */
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22 | 8135aeed | Isaku Yamahata | |
23 | 8135aeed | Isaku Yamahata | #include "pci_ids.h" |
24 | 8135aeed | Isaku Yamahata | #include "msi.h" |
25 | 8135aeed | Isaku Yamahata | #include "pcie.h" |
26 | 8135aeed | Isaku Yamahata | #include "ioh3420.h" |
27 | 8135aeed | Isaku Yamahata | |
28 | 8135aeed | Isaku Yamahata | #define PCI_DEVICE_ID_IOH_EPORT 0x3420 /* D0:F0 express mode */ |
29 | 8135aeed | Isaku Yamahata | #define PCI_DEVICE_ID_IOH_REV 0x2 |
30 | 8135aeed | Isaku Yamahata | #define IOH_EP_SSVID_OFFSET 0x40 |
31 | 8135aeed | Isaku Yamahata | #define IOH_EP_SSVID_SVID PCI_VENDOR_ID_INTEL
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32 | 8135aeed | Isaku Yamahata | #define IOH_EP_SSVID_SSID 0 |
33 | 8135aeed | Isaku Yamahata | #define IOH_EP_MSI_OFFSET 0x60 |
34 | 8135aeed | Isaku Yamahata | #define IOH_EP_MSI_SUPPORTED_FLAGS PCI_MSI_FLAGS_MASKBIT
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35 | 8135aeed | Isaku Yamahata | #define IOH_EP_MSI_NR_VECTOR 2 |
36 | 8135aeed | Isaku Yamahata | #define IOH_EP_EXP_OFFSET 0x90 |
37 | 8135aeed | Isaku Yamahata | #define IOH_EP_AER_OFFSET 0x100 |
38 | 8135aeed | Isaku Yamahata | |
39 | 61620c2f | Isaku Yamahata | /*
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40 | 61620c2f | Isaku Yamahata | * If two MSI vector are allocated, Advanced Error Interrupt Message Number
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41 | 61620c2f | Isaku Yamahata | * is 1. otherwise 0.
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42 | 61620c2f | Isaku Yamahata | * 17.12.5.10 RPERRSTS, 32:27 bit Advanced Error Interrupt Message Number.
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43 | 61620c2f | Isaku Yamahata | */
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44 | 61620c2f | Isaku Yamahata | static uint8_t ioh3420_aer_vector(const PCIDevice *d) |
45 | 61620c2f | Isaku Yamahata | { |
46 | 61620c2f | Isaku Yamahata | switch (msi_nr_vectors_allocated(d)) {
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47 | 61620c2f | Isaku Yamahata | case 1: |
48 | 61620c2f | Isaku Yamahata | return 0; |
49 | 61620c2f | Isaku Yamahata | case 2: |
50 | 61620c2f | Isaku Yamahata | return 1; |
51 | 61620c2f | Isaku Yamahata | case 4: |
52 | 61620c2f | Isaku Yamahata | case 8: |
53 | 61620c2f | Isaku Yamahata | case 16: |
54 | 61620c2f | Isaku Yamahata | case 32: |
55 | 61620c2f | Isaku Yamahata | default:
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56 | 61620c2f | Isaku Yamahata | break;
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57 | 61620c2f | Isaku Yamahata | } |
58 | 61620c2f | Isaku Yamahata | abort(); |
59 | 61620c2f | Isaku Yamahata | return 0; |
60 | 61620c2f | Isaku Yamahata | } |
61 | 61620c2f | Isaku Yamahata | |
62 | 61620c2f | Isaku Yamahata | static void ioh3420_aer_vector_update(PCIDevice *d) |
63 | 61620c2f | Isaku Yamahata | { |
64 | 61620c2f | Isaku Yamahata | pcie_aer_root_set_vector(d, ioh3420_aer_vector(d)); |
65 | 61620c2f | Isaku Yamahata | } |
66 | 61620c2f | Isaku Yamahata | |
67 | 8135aeed | Isaku Yamahata | static void ioh3420_write_config(PCIDevice *d, |
68 | 8135aeed | Isaku Yamahata | uint32_t address, uint32_t val, int len)
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69 | 8135aeed | Isaku Yamahata | { |
70 | 61620c2f | Isaku Yamahata | uint32_t root_cmd = |
71 | 61620c2f | Isaku Yamahata | pci_get_long(d->config + d->exp.aer_cap + PCI_ERR_ROOT_COMMAND); |
72 | 61620c2f | Isaku Yamahata | |
73 | 8135aeed | Isaku Yamahata | pci_bridge_write_config(d, address, val, len); |
74 | 61620c2f | Isaku Yamahata | ioh3420_aer_vector_update(d); |
75 | 6bde6aaa | Michael S. Tsirkin | pcie_cap_slot_write_config(d, address, val, len); |
76 | 61620c2f | Isaku Yamahata | pcie_aer_write_config(d, address, val, len); |
77 | 61620c2f | Isaku Yamahata | pcie_aer_root_write_config(d, address, val, len, root_cmd); |
78 | 8135aeed | Isaku Yamahata | } |
79 | 8135aeed | Isaku Yamahata | |
80 | 8135aeed | Isaku Yamahata | static void ioh3420_reset(DeviceState *qdev) |
81 | 8135aeed | Isaku Yamahata | { |
82 | 40021f08 | Anthony Liguori | PCIDevice *d = PCI_DEVICE(qdev); |
83 | cbd2d434 | Jan Kiszka | |
84 | 61620c2f | Isaku Yamahata | ioh3420_aer_vector_update(d); |
85 | 8135aeed | Isaku Yamahata | pcie_cap_root_reset(d); |
86 | 8135aeed | Isaku Yamahata | pcie_cap_deverr_reset(d); |
87 | 8135aeed | Isaku Yamahata | pcie_cap_slot_reset(d); |
88 | 61620c2f | Isaku Yamahata | pcie_aer_root_reset(d); |
89 | 8135aeed | Isaku Yamahata | pci_bridge_reset(qdev); |
90 | 8135aeed | Isaku Yamahata | pci_bridge_disable_base_limit(d); |
91 | 8135aeed | Isaku Yamahata | } |
92 | 8135aeed | Isaku Yamahata | |
93 | 8135aeed | Isaku Yamahata | static int ioh3420_initfn(PCIDevice *d) |
94 | 8135aeed | Isaku Yamahata | { |
95 | 8135aeed | Isaku Yamahata | PCIBridge* br = DO_UPCAST(PCIBridge, dev, d); |
96 | 8135aeed | Isaku Yamahata | PCIEPort *p = DO_UPCAST(PCIEPort, br, br); |
97 | 8135aeed | Isaku Yamahata | PCIESlot *s = DO_UPCAST(PCIESlot, port, p); |
98 | 8135aeed | Isaku Yamahata | int rc;
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99 | 8135aeed | Isaku Yamahata | |
100 | 8135aeed | Isaku Yamahata | rc = pci_bridge_initfn(d); |
101 | 8135aeed | Isaku Yamahata | if (rc < 0) { |
102 | 8135aeed | Isaku Yamahata | return rc;
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103 | 8135aeed | Isaku Yamahata | } |
104 | 8135aeed | Isaku Yamahata | |
105 | 8135aeed | Isaku Yamahata | pcie_port_init_reg(d); |
106 | 8135aeed | Isaku Yamahata | |
107 | 8135aeed | Isaku Yamahata | rc = pci_bridge_ssvid_init(d, IOH_EP_SSVID_OFFSET, |
108 | 8135aeed | Isaku Yamahata | IOH_EP_SSVID_SVID, IOH_EP_SSVID_SSID); |
109 | 8135aeed | Isaku Yamahata | if (rc < 0) { |
110 | 61620c2f | Isaku Yamahata | goto err_bridge;
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111 | 8135aeed | Isaku Yamahata | } |
112 | 8135aeed | Isaku Yamahata | rc = msi_init(d, IOH_EP_MSI_OFFSET, IOH_EP_MSI_NR_VECTOR, |
113 | 8135aeed | Isaku Yamahata | IOH_EP_MSI_SUPPORTED_FLAGS & PCI_MSI_FLAGS_64BIT, |
114 | 8135aeed | Isaku Yamahata | IOH_EP_MSI_SUPPORTED_FLAGS & PCI_MSI_FLAGS_MASKBIT); |
115 | 8135aeed | Isaku Yamahata | if (rc < 0) { |
116 | 61620c2f | Isaku Yamahata | goto err_bridge;
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117 | 8135aeed | Isaku Yamahata | } |
118 | 8135aeed | Isaku Yamahata | rc = pcie_cap_init(d, IOH_EP_EXP_OFFSET, PCI_EXP_TYPE_ROOT_PORT, p->port); |
119 | 8135aeed | Isaku Yamahata | if (rc < 0) { |
120 | 61620c2f | Isaku Yamahata | goto err_msi;
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121 | 8135aeed | Isaku Yamahata | } |
122 | 8135aeed | Isaku Yamahata | pcie_cap_deverr_init(d); |
123 | 8135aeed | Isaku Yamahata | pcie_cap_slot_init(d, s->slot); |
124 | 8135aeed | Isaku Yamahata | pcie_chassis_create(s->chassis); |
125 | 8135aeed | Isaku Yamahata | rc = pcie_chassis_add_slot(s); |
126 | 8135aeed | Isaku Yamahata | if (rc < 0) { |
127 | 61620c2f | Isaku Yamahata | goto err_pcie_cap;
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128 | 8135aeed | Isaku Yamahata | } |
129 | 8135aeed | Isaku Yamahata | pcie_cap_root_init(d); |
130 | 61620c2f | Isaku Yamahata | rc = pcie_aer_init(d, IOH_EP_AER_OFFSET); |
131 | 61620c2f | Isaku Yamahata | if (rc < 0) { |
132 | 61620c2f | Isaku Yamahata | goto err;
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133 | 61620c2f | Isaku Yamahata | } |
134 | 61620c2f | Isaku Yamahata | pcie_aer_root_init(d); |
135 | 61620c2f | Isaku Yamahata | ioh3420_aer_vector_update(d); |
136 | 8135aeed | Isaku Yamahata | return 0; |
137 | 61620c2f | Isaku Yamahata | |
138 | 61620c2f | Isaku Yamahata | err:
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139 | 61620c2f | Isaku Yamahata | pcie_chassis_del_slot(s); |
140 | 61620c2f | Isaku Yamahata | err_pcie_cap:
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141 | 61620c2f | Isaku Yamahata | pcie_cap_exit(d); |
142 | 61620c2f | Isaku Yamahata | err_msi:
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143 | 61620c2f | Isaku Yamahata | msi_uninit(d); |
144 | 61620c2f | Isaku Yamahata | err_bridge:
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145 | f90c2bcd | Alex Williamson | pci_bridge_exitfn(d); |
146 | 61620c2f | Isaku Yamahata | return rc;
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147 | 8135aeed | Isaku Yamahata | } |
148 | 8135aeed | Isaku Yamahata | |
149 | f90c2bcd | Alex Williamson | static void ioh3420_exitfn(PCIDevice *d) |
150 | 8135aeed | Isaku Yamahata | { |
151 | 61620c2f | Isaku Yamahata | PCIBridge* br = DO_UPCAST(PCIBridge, dev, d); |
152 | 61620c2f | Isaku Yamahata | PCIEPort *p = DO_UPCAST(PCIEPort, br, br); |
153 | 61620c2f | Isaku Yamahata | PCIESlot *s = DO_UPCAST(PCIESlot, port, p); |
154 | 61620c2f | Isaku Yamahata | |
155 | 61620c2f | Isaku Yamahata | pcie_aer_exit(d); |
156 | 61620c2f | Isaku Yamahata | pcie_chassis_del_slot(s); |
157 | 8135aeed | Isaku Yamahata | pcie_cap_exit(d); |
158 | 61620c2f | Isaku Yamahata | msi_uninit(d); |
159 | f90c2bcd | Alex Williamson | pci_bridge_exitfn(d); |
160 | 8135aeed | Isaku Yamahata | } |
161 | 8135aeed | Isaku Yamahata | |
162 | 8135aeed | Isaku Yamahata | PCIESlot *ioh3420_init(PCIBus *bus, int devfn, bool multifunction, |
163 | 8135aeed | Isaku Yamahata | const char *bus_name, pci_map_irq_fn map_irq, |
164 | 8135aeed | Isaku Yamahata | uint8_t port, uint8_t chassis, uint16_t slot) |
165 | 8135aeed | Isaku Yamahata | { |
166 | 8135aeed | Isaku Yamahata | PCIDevice *d; |
167 | 8135aeed | Isaku Yamahata | PCIBridge *br; |
168 | 8135aeed | Isaku Yamahata | DeviceState *qdev; |
169 | 8135aeed | Isaku Yamahata | |
170 | 8135aeed | Isaku Yamahata | d = pci_create_multifunction(bus, devfn, multifunction, "ioh3420");
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171 | 8135aeed | Isaku Yamahata | if (!d) {
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172 | 8135aeed | Isaku Yamahata | return NULL; |
173 | 8135aeed | Isaku Yamahata | } |
174 | 8135aeed | Isaku Yamahata | br = DO_UPCAST(PCIBridge, dev, d); |
175 | 8135aeed | Isaku Yamahata | |
176 | 8135aeed | Isaku Yamahata | qdev = &br->dev.qdev; |
177 | 8135aeed | Isaku Yamahata | pci_bridge_map_irq(br, bus_name, map_irq); |
178 | 8135aeed | Isaku Yamahata | qdev_prop_set_uint8(qdev, "port", port);
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179 | 8135aeed | Isaku Yamahata | qdev_prop_set_uint8(qdev, "chassis", chassis);
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180 | 8135aeed | Isaku Yamahata | qdev_prop_set_uint16(qdev, "slot", slot);
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181 | 8135aeed | Isaku Yamahata | qdev_init_nofail(qdev); |
182 | 8135aeed | Isaku Yamahata | |
183 | 8135aeed | Isaku Yamahata | return DO_UPCAST(PCIESlot, port, DO_UPCAST(PCIEPort, br, br));
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184 | 8135aeed | Isaku Yamahata | } |
185 | 8135aeed | Isaku Yamahata | |
186 | 8135aeed | Isaku Yamahata | static const VMStateDescription vmstate_ioh3420 = { |
187 | 8135aeed | Isaku Yamahata | .name = "ioh-3240-express-root-port",
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188 | 8135aeed | Isaku Yamahata | .version_id = 1,
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189 | 8135aeed | Isaku Yamahata | .minimum_version_id = 1,
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190 | 8135aeed | Isaku Yamahata | .minimum_version_id_old = 1,
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191 | 6bde6aaa | Michael S. Tsirkin | .post_load = pcie_cap_slot_post_load, |
192 | 8135aeed | Isaku Yamahata | .fields = (VMStateField[]) { |
193 | 8135aeed | Isaku Yamahata | VMSTATE_PCIE_DEVICE(port.br.dev, PCIESlot), |
194 | 61620c2f | Isaku Yamahata | VMSTATE_STRUCT(port.br.dev.exp.aer_log, PCIESlot, 0,
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195 | 61620c2f | Isaku Yamahata | vmstate_pcie_aer_log, PCIEAERLog), |
196 | 8135aeed | Isaku Yamahata | VMSTATE_END_OF_LIST() |
197 | 8135aeed | Isaku Yamahata | } |
198 | 8135aeed | Isaku Yamahata | }; |
199 | 8135aeed | Isaku Yamahata | |
200 | 40021f08 | Anthony Liguori | static Property ioh3420_properties[] = {
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201 | 40021f08 | Anthony Liguori | DEFINE_PROP_UINT8("port", PCIESlot, port.port, 0), |
202 | 40021f08 | Anthony Liguori | DEFINE_PROP_UINT8("chassis", PCIESlot, chassis, 0), |
203 | 40021f08 | Anthony Liguori | DEFINE_PROP_UINT16("slot", PCIESlot, slot, 0), |
204 | 40021f08 | Anthony Liguori | DEFINE_PROP_UINT16("aer_log_max", PCIESlot,
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205 | 40021f08 | Anthony Liguori | port.br.dev.exp.aer_log.log_max, |
206 | 40021f08 | Anthony Liguori | PCIE_AER_LOG_MAX_DEFAULT), |
207 | 40021f08 | Anthony Liguori | DEFINE_PROP_END_OF_LIST(), |
208 | 40021f08 | Anthony Liguori | }; |
209 | 40021f08 | Anthony Liguori | |
210 | 40021f08 | Anthony Liguori | static void ioh3420_class_init(ObjectClass *klass, void *data) |
211 | 40021f08 | Anthony Liguori | { |
212 | 39bffca2 | Anthony Liguori | DeviceClass *dc = DEVICE_CLASS(klass); |
213 | 40021f08 | Anthony Liguori | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
214 | 40021f08 | Anthony Liguori | |
215 | 40021f08 | Anthony Liguori | k->is_express = 1;
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216 | 40021f08 | Anthony Liguori | k->is_bridge = 1;
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217 | 40021f08 | Anthony Liguori | k->config_write = ioh3420_write_config; |
218 | 40021f08 | Anthony Liguori | k->init = ioh3420_initfn; |
219 | 40021f08 | Anthony Liguori | k->exit = ioh3420_exitfn; |
220 | 40021f08 | Anthony Liguori | k->vendor_id = PCI_VENDOR_ID_INTEL; |
221 | 40021f08 | Anthony Liguori | k->device_id = PCI_DEVICE_ID_IOH_EPORT; |
222 | 40021f08 | Anthony Liguori | k->revision = PCI_DEVICE_ID_IOH_REV; |
223 | 39bffca2 | Anthony Liguori | dc->desc = "Intel IOH device id 3420 PCIE Root Port";
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224 | 39bffca2 | Anthony Liguori | dc->reset = ioh3420_reset; |
225 | 39bffca2 | Anthony Liguori | dc->vmsd = &vmstate_ioh3420; |
226 | 39bffca2 | Anthony Liguori | dc->props = ioh3420_properties; |
227 | 40021f08 | Anthony Liguori | } |
228 | 40021f08 | Anthony Liguori | |
229 | 39bffca2 | Anthony Liguori | static TypeInfo ioh3420_info = {
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230 | 39bffca2 | Anthony Liguori | .name = "ioh3420",
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231 | 39bffca2 | Anthony Liguori | .parent = TYPE_PCI_DEVICE, |
232 | 39bffca2 | Anthony Liguori | .instance_size = sizeof(PCIESlot),
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233 | 39bffca2 | Anthony Liguori | .class_init = ioh3420_class_init, |
234 | 8135aeed | Isaku Yamahata | }; |
235 | 8135aeed | Isaku Yamahata | |
236 | 83f7d43a | Andreas Färber | static void ioh3420_register_types(void) |
237 | 8135aeed | Isaku Yamahata | { |
238 | 39bffca2 | Anthony Liguori | type_register_static(&ioh3420_info); |
239 | 8135aeed | Isaku Yamahata | } |
240 | 8135aeed | Isaku Yamahata | |
241 | 83f7d43a | Andreas Färber | type_init(ioh3420_register_types) |
242 | 8135aeed | Isaku Yamahata | |
243 | 8135aeed | Isaku Yamahata | /*
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244 | 8135aeed | Isaku Yamahata | * Local variables:
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245 | 8135aeed | Isaku Yamahata | * c-indent-level: 4
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246 | 8135aeed | Isaku Yamahata | * c-basic-offset: 4
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247 | 8135aeed | Isaku Yamahata | * tab-width: 8
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248 | 8135aeed | Isaku Yamahata | * indent-tab-mode: nil
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249 | 8135aeed | Isaku Yamahata | * End:
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250 | 8135aeed | Isaku Yamahata | */ |