root / hw / acpi_piix4.c @ a1bc20df
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/*
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* ACPI implementation
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*
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* Copyright (c) 2006 Fabrice Bellard
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License version 2 as published by the Free Software Foundation.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>
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*
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* Contributions after 2012-01-13 are licensed under the terms of the
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* GNU GPL, version 2 or (at your option) any later version.
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*/
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#include "hw.h" |
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#include "pc.h" |
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#include "apm.h" |
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#include "pm_smbus.h" |
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#include "pci.h" |
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#include "acpi.h" |
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#include "sysemu.h" |
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#include "range.h" |
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#include "ioport.h" |
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#include "fw_cfg.h" |
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//#define DEBUG
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#ifdef DEBUG
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# define PIIX4_DPRINTF(format, ...) printf(format, ## __VA_ARGS__) |
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#else
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# define PIIX4_DPRINTF(format, ...) do { } while (0) |
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#endif
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#define ACPI_DBG_IO_ADDR 0xb044 |
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#define GPE_BASE 0xafe0 |
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#define GPE_LEN 4 |
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#define PCI_UP_BASE 0xae00 |
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#define PCI_DOWN_BASE 0xae04 |
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#define PCI_EJ_BASE 0xae08 |
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#define PCI_RMV_BASE 0xae0c |
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#define PIIX4_PCI_HOTPLUG_STATUS 2 |
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struct pci_status {
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uint32_t up; /* deprecated, maintained for migration compatibility */
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uint32_t down; |
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}; |
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typedef struct PIIX4PMState { |
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PCIDevice dev; |
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IORange ioport; |
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ACPIREGS ar; |
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APMState apm; |
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PMSMBus smb; |
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uint32_t smb_io_base; |
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qemu_irq irq; |
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qemu_irq smi_irq; |
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int kvm_enabled;
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Notifier machine_ready; |
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Notifier powerdown_notifier; |
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/* for pci hotplug */
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struct pci_status pci0_status;
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uint32_t pci0_hotplug_enable; |
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uint32_t pci0_slot_device_present; |
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uint8_t disable_s3; |
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uint8_t disable_s4; |
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uint8_t s4_val; |
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} PIIX4PMState; |
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static void piix4_acpi_system_hot_add_init(PCIBus *bus, PIIX4PMState *s); |
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#define ACPI_ENABLE 0xf1 |
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#define ACPI_DISABLE 0xf0 |
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static void pm_update_sci(PIIX4PMState *s) |
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{ |
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int sci_level, pmsts;
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pmsts = acpi_pm1_evt_get_sts(&s->ar); |
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sci_level = (((pmsts & s->ar.pm1.evt.en) & |
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(ACPI_BITMASK_RT_CLOCK_ENABLE | |
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ACPI_BITMASK_POWER_BUTTON_ENABLE | |
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ACPI_BITMASK_GLOBAL_LOCK_ENABLE | |
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ACPI_BITMASK_TIMER_ENABLE)) != 0) ||
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(((s->ar.gpe.sts[0] & s->ar.gpe.en[0]) |
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& PIIX4_PCI_HOTPLUG_STATUS) != 0);
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qemu_set_irq(s->irq, sci_level); |
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/* schedule a timer interruption if needed */
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acpi_pm_tmr_update(&s->ar, (s->ar.pm1.evt.en & ACPI_BITMASK_TIMER_ENABLE) && |
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!(pmsts & ACPI_BITMASK_TIMER_STATUS)); |
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} |
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static void pm_tmr_timer(ACPIREGS *ar) |
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{ |
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PIIX4PMState *s = container_of(ar, PIIX4PMState, ar); |
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pm_update_sci(s); |
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} |
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static void pm_ioport_write(IORange *ioport, uint64_t addr, unsigned width, |
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uint64_t val) |
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{ |
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PIIX4PMState *s = container_of(ioport, PIIX4PMState, ioport); |
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if (width != 2) { |
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PIIX4_DPRINTF("PM write port=0x%04x width=%d val=0x%08x\n",
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(unsigned)addr, width, (unsigned)val); |
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} |
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switch(addr) {
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case 0x00: |
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acpi_pm1_evt_write_sts(&s->ar, val); |
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pm_update_sci(s); |
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break;
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case 0x02: |
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acpi_pm1_evt_write_en(&s->ar, val); |
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pm_update_sci(s); |
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break;
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case 0x04: |
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acpi_pm1_cnt_write(&s->ar, val, s->s4_val); |
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break;
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default:
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break;
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} |
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PIIX4_DPRINTF("PM writew port=0x%04x val=0x%04x\n", (unsigned int)addr, |
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(unsigned int)val); |
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} |
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static void pm_ioport_read(IORange *ioport, uint64_t addr, unsigned width, |
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uint64_t *data) |
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{ |
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PIIX4PMState *s = container_of(ioport, PIIX4PMState, ioport); |
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uint32_t val; |
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switch(addr) {
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case 0x00: |
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val = acpi_pm1_evt_get_sts(&s->ar); |
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break;
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case 0x02: |
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val = s->ar.pm1.evt.en; |
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break;
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case 0x04: |
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val = s->ar.pm1.cnt.cnt; |
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break;
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case 0x08: |
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val = acpi_pm_tmr_get(&s->ar); |
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break;
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default:
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val = 0;
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break;
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} |
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PIIX4_DPRINTF("PM readw port=0x%04x val=0x%04x\n", (unsigned int)addr, val); |
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*data = val; |
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} |
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static const IORangeOps pm_iorange_ops = { |
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.read = pm_ioport_read, |
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.write = pm_ioport_write, |
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}; |
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static void apm_ctrl_changed(uint32_t val, void *arg) |
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{ |
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PIIX4PMState *s = arg; |
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/* ACPI specs 3.0, 4.7.2.5 */
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acpi_pm1_cnt_update(&s->ar, val == ACPI_ENABLE, val == ACPI_DISABLE); |
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if (s->dev.config[0x5b] & (1 << 1)) { |
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if (s->smi_irq) {
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qemu_irq_raise(s->smi_irq); |
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} |
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} |
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} |
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static void acpi_dbg_writel(void *opaque, uint32_t addr, uint32_t val) |
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{ |
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PIIX4_DPRINTF("ACPI: DBG: 0x%08x\n", val);
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} |
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static void pm_io_space_update(PIIX4PMState *s) |
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{ |
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uint32_t pm_io_base; |
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if (s->dev.config[0x80] & 1) { |
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pm_io_base = le32_to_cpu(*(uint32_t *)(s->dev.config + 0x40));
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pm_io_base &= 0xffc0;
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/* XXX: need to improve memory and ioport allocation */
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PIIX4_DPRINTF("PM: mapping to 0x%x\n", pm_io_base);
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iorange_init(&s->ioport, &pm_iorange_ops, pm_io_base, 64);
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ioport_register(&s->ioport); |
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} |
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} |
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static void pm_write_config(PCIDevice *d, |
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uint32_t address, uint32_t val, int len)
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{ |
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pci_default_write_config(d, address, val, len); |
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if (range_covers_byte(address, len, 0x80)) |
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pm_io_space_update((PIIX4PMState *)d); |
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} |
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static void vmstate_pci_status_pre_save(void *opaque) |
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{ |
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struct pci_status *pci0_status = opaque;
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PIIX4PMState *s = container_of(pci0_status, PIIX4PMState, pci0_status); |
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/* We no longer track up, so build a safe value for migrating
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* to a version that still does... of course these might get lost
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* by an old buggy implementation, but we try. */
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pci0_status->up = s->pci0_slot_device_present & s->pci0_hotplug_enable; |
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} |
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static int vmstate_acpi_post_load(void *opaque, int version_id) |
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{ |
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PIIX4PMState *s = opaque; |
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pm_io_space_update(s); |
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return 0; |
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} |
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#define VMSTATE_GPE_ARRAY(_field, _state) \
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{ \ |
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.name = (stringify(_field)), \ |
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.version_id = 0, \
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.num = GPE_LEN, \ |
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.info = &vmstate_info_uint16, \ |
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.size = sizeof(uint16_t), \
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.flags = VMS_ARRAY | VMS_POINTER, \ |
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.offset = vmstate_offset_pointer(_state, _field, uint8_t), \ |
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} |
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static const VMStateDescription vmstate_gpe = { |
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.name = "gpe",
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.version_id = 1,
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.minimum_version_id = 1,
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.minimum_version_id_old = 1,
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.fields = (VMStateField []) { |
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VMSTATE_GPE_ARRAY(sts, ACPIGPE), |
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VMSTATE_GPE_ARRAY(en, ACPIGPE), |
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VMSTATE_END_OF_LIST() |
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} |
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}; |
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static const VMStateDescription vmstate_pci_status = { |
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.name = "pci_status",
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.version_id = 1,
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.minimum_version_id = 1,
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.minimum_version_id_old = 1,
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.pre_save = vmstate_pci_status_pre_save, |
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.fields = (VMStateField []) { |
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VMSTATE_UINT32(up, struct pci_status),
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VMSTATE_UINT32(down, struct pci_status),
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VMSTATE_END_OF_LIST() |
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} |
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}; |
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static const VMStateDescription vmstate_acpi = { |
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.name = "piix4_pm",
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.version_id = 2,
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.minimum_version_id = 1,
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.minimum_version_id_old = 1,
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.post_load = vmstate_acpi_post_load, |
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.fields = (VMStateField []) { |
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VMSTATE_PCI_DEVICE(dev, PIIX4PMState), |
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VMSTATE_UINT16(ar.pm1.evt.sts, PIIX4PMState), |
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VMSTATE_UINT16(ar.pm1.evt.en, PIIX4PMState), |
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VMSTATE_UINT16(ar.pm1.cnt.cnt, PIIX4PMState), |
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VMSTATE_STRUCT(apm, PIIX4PMState, 0, vmstate_apm, APMState),
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VMSTATE_TIMER(ar.tmr.timer, PIIX4PMState), |
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VMSTATE_INT64(ar.tmr.overflow_time, PIIX4PMState), |
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VMSTATE_STRUCT(ar.gpe, PIIX4PMState, 2, vmstate_gpe, ACPIGPE),
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VMSTATE_STRUCT(pci0_status, PIIX4PMState, 2, vmstate_pci_status,
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struct pci_status),
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VMSTATE_END_OF_LIST() |
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} |
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}; |
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static void acpi_piix_eject_slot(PIIX4PMState *s, unsigned slots) |
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{ |
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BusChild *kid, *next; |
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BusState *bus = qdev_get_parent_bus(&s->dev.qdev); |
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int slot = ffs(slots) - 1; |
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bool slot_free = true; |
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/* Mark request as complete */
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s->pci0_status.down &= ~(1U << slot);
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QTAILQ_FOREACH_SAFE(kid, &bus->children, sibling, next) { |
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DeviceState *qdev = kid->child; |
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PCIDevice *dev = PCI_DEVICE(qdev); |
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PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev); |
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if (PCI_SLOT(dev->devfn) == slot) {
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if (pc->no_hotplug) {
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slot_free = false;
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} else {
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qdev_free(qdev); |
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} |
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} |
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} |
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if (slot_free) {
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s->pci0_slot_device_present &= ~(1U << slot);
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} |
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} |
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static void piix4_update_hotplug(PIIX4PMState *s) |
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{ |
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PCIDevice *dev = &s->dev; |
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BusState *bus = qdev_get_parent_bus(&dev->qdev); |
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BusChild *kid, *next; |
323 |
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/* Execute any pending removes during reset */
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while (s->pci0_status.down) {
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acpi_piix_eject_slot(s, s->pci0_status.down); |
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} |
328 |
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s->pci0_hotplug_enable = ~0;
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s->pci0_slot_device_present = 0;
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QTAILQ_FOREACH_SAFE(kid, &bus->children, sibling, next) { |
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DeviceState *qdev = kid->child; |
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PCIDevice *pdev = PCI_DEVICE(qdev); |
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PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(pdev); |
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int slot = PCI_SLOT(pdev->devfn);
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if (pc->no_hotplug) {
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s->pci0_hotplug_enable &= ~(1U << slot);
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} |
341 |
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s->pci0_slot_device_present |= (1U << slot);
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} |
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} |
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|
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static void piix4_reset(void *opaque) |
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{ |
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PIIX4PMState *s = opaque; |
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uint8_t *pci_conf = s->dev.config; |
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|
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pci_conf[0x58] = 0; |
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pci_conf[0x59] = 0; |
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pci_conf[0x5a] = 0; |
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pci_conf[0x5b] = 0; |
355 |
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pci_conf[0x40] = 0x01; /* PM io base read only bit */ |
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pci_conf[0x80] = 0; |
358 |
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if (s->kvm_enabled) {
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/* Mark SMM as already inited (until KVM supports SMM). */
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pci_conf[0x5B] = 0x02; |
362 |
} |
363 |
piix4_update_hotplug(s); |
364 |
} |
365 |
|
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static void piix4_pm_powerdown_req(Notifier *n, void *opaque) |
367 |
{ |
368 |
PIIX4PMState *s = container_of(n, PIIX4PMState, powerdown_notifier); |
369 |
|
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assert(s != NULL);
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acpi_pm1_evt_power_down(&s->ar); |
372 |
} |
373 |
|
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static void piix4_pm_machine_ready(Notifier *n, void *opaque) |
375 |
{ |
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PIIX4PMState *s = container_of(n, PIIX4PMState, machine_ready); |
377 |
uint8_t *pci_conf; |
378 |
|
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pci_conf = s->dev.config; |
380 |
pci_conf[0x5f] = (isa_is_ioport_assigned(0x378) ? 0x80 : 0) | 0x10; |
381 |
pci_conf[0x63] = 0x60; |
382 |
pci_conf[0x67] = (isa_is_ioport_assigned(0x3f8) ? 0x08 : 0) | |
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(isa_is_ioport_assigned(0x2f8) ? 0x90 : 0); |
384 |
|
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} |
386 |
|
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static int piix4_pm_initfn(PCIDevice *dev) |
388 |
{ |
389 |
PIIX4PMState *s = DO_UPCAST(PIIX4PMState, dev, dev); |
390 |
uint8_t *pci_conf; |
391 |
|
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pci_conf = s->dev.config; |
393 |
pci_conf[0x06] = 0x80; |
394 |
pci_conf[0x07] = 0x02; |
395 |
pci_conf[0x09] = 0x00; |
396 |
pci_conf[0x3d] = 0x01; // interrupt pin 1 |
397 |
|
398 |
/* APM */
|
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apm_init(&s->apm, apm_ctrl_changed, s); |
400 |
|
401 |
register_ioport_write(ACPI_DBG_IO_ADDR, 4, 4, acpi_dbg_writel, s); |
402 |
|
403 |
if (s->kvm_enabled) {
|
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/* Mark SMM as already inited to prevent SMM from running. KVM does not
|
405 |
* support SMM mode. */
|
406 |
pci_conf[0x5B] = 0x02; |
407 |
} |
408 |
|
409 |
/* XXX: which specification is used ? The i82731AB has different
|
410 |
mappings */
|
411 |
pci_conf[0x90] = s->smb_io_base | 1; |
412 |
pci_conf[0x91] = s->smb_io_base >> 8; |
413 |
pci_conf[0xd2] = 0x09; |
414 |
register_ioport_write(s->smb_io_base, 64, 1, smb_ioport_writeb, &s->smb); |
415 |
register_ioport_read(s->smb_io_base, 64, 1, smb_ioport_readb, &s->smb); |
416 |
|
417 |
acpi_pm_tmr_init(&s->ar, pm_tmr_timer); |
418 |
acpi_gpe_init(&s->ar, GPE_LEN); |
419 |
|
420 |
s->powerdown_notifier.notify = piix4_pm_powerdown_req; |
421 |
qemu_register_powerdown_notifier(&s->powerdown_notifier); |
422 |
|
423 |
pm_smbus_init(&s->dev.qdev, &s->smb); |
424 |
s->machine_ready.notify = piix4_pm_machine_ready; |
425 |
qemu_add_machine_init_done_notifier(&s->machine_ready); |
426 |
qemu_register_reset(piix4_reset, s); |
427 |
piix4_acpi_system_hot_add_init(dev->bus, s); |
428 |
|
429 |
return 0; |
430 |
} |
431 |
|
432 |
i2c_bus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
|
433 |
qemu_irq sci_irq, qemu_irq smi_irq, |
434 |
int kvm_enabled, void *fw_cfg) |
435 |
{ |
436 |
PCIDevice *dev; |
437 |
PIIX4PMState *s; |
438 |
|
439 |
dev = pci_create(bus, devfn, "PIIX4_PM");
|
440 |
qdev_prop_set_uint32(&dev->qdev, "smb_io_base", smb_io_base);
|
441 |
|
442 |
s = DO_UPCAST(PIIX4PMState, dev, dev); |
443 |
s->irq = sci_irq; |
444 |
acpi_pm1_cnt_init(&s->ar); |
445 |
s->smi_irq = smi_irq; |
446 |
s->kvm_enabled = kvm_enabled; |
447 |
|
448 |
qdev_init_nofail(&dev->qdev); |
449 |
|
450 |
if (fw_cfg) {
|
451 |
uint8_t suspend[6] = {128, 0, 0, 129, 128, 128}; |
452 |
suspend[3] = 1 | ((!s->disable_s3) << 7); |
453 |
suspend[4] = s->s4_val | ((!s->disable_s4) << 7); |
454 |
|
455 |
fw_cfg_add_file(fw_cfg, "etc/system-states", g_memdup(suspend, 6), 6); |
456 |
} |
457 |
|
458 |
return s->smb.smbus;
|
459 |
} |
460 |
|
461 |
static Property piix4_pm_properties[] = {
|
462 |
DEFINE_PROP_UINT32("smb_io_base", PIIX4PMState, smb_io_base, 0), |
463 |
DEFINE_PROP_UINT8("disable_s3", PIIX4PMState, disable_s3, 0), |
464 |
DEFINE_PROP_UINT8("disable_s4", PIIX4PMState, disable_s4, 0), |
465 |
DEFINE_PROP_UINT8("s4_val", PIIX4PMState, s4_val, 2), |
466 |
DEFINE_PROP_END_OF_LIST(), |
467 |
}; |
468 |
|
469 |
static void piix4_pm_class_init(ObjectClass *klass, void *data) |
470 |
{ |
471 |
DeviceClass *dc = DEVICE_CLASS(klass); |
472 |
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
473 |
|
474 |
k->no_hotplug = 1;
|
475 |
k->init = piix4_pm_initfn; |
476 |
k->config_write = pm_write_config; |
477 |
k->vendor_id = PCI_VENDOR_ID_INTEL; |
478 |
k->device_id = PCI_DEVICE_ID_INTEL_82371AB_3; |
479 |
k->revision = 0x03;
|
480 |
k->class_id = PCI_CLASS_BRIDGE_OTHER; |
481 |
dc->desc = "PM";
|
482 |
dc->no_user = 1;
|
483 |
dc->vmsd = &vmstate_acpi; |
484 |
dc->props = piix4_pm_properties; |
485 |
} |
486 |
|
487 |
static TypeInfo piix4_pm_info = {
|
488 |
.name = "PIIX4_PM",
|
489 |
.parent = TYPE_PCI_DEVICE, |
490 |
.instance_size = sizeof(PIIX4PMState),
|
491 |
.class_init = piix4_pm_class_init, |
492 |
}; |
493 |
|
494 |
static void piix4_pm_register_types(void) |
495 |
{ |
496 |
type_register_static(&piix4_pm_info); |
497 |
} |
498 |
|
499 |
type_init(piix4_pm_register_types) |
500 |
|
501 |
static uint32_t gpe_readb(void *opaque, uint32_t addr) |
502 |
{ |
503 |
PIIX4PMState *s = opaque; |
504 |
uint32_t val = acpi_gpe_ioport_readb(&s->ar, addr); |
505 |
|
506 |
PIIX4_DPRINTF("gpe read %x == %x\n", addr, val);
|
507 |
return val;
|
508 |
} |
509 |
|
510 |
static void gpe_writeb(void *opaque, uint32_t addr, uint32_t val) |
511 |
{ |
512 |
PIIX4PMState *s = opaque; |
513 |
|
514 |
acpi_gpe_ioport_writeb(&s->ar, addr, val); |
515 |
pm_update_sci(s); |
516 |
|
517 |
PIIX4_DPRINTF("gpe write %x <== %d\n", addr, val);
|
518 |
} |
519 |
|
520 |
static uint32_t pci_up_read(void *opaque, uint32_t addr) |
521 |
{ |
522 |
PIIX4PMState *s = opaque; |
523 |
uint32_t val; |
524 |
|
525 |
/* Manufacture an "up" value to cause a device check on any hotplug
|
526 |
* slot with a device. Extra device checks are harmless. */
|
527 |
val = s->pci0_slot_device_present & s->pci0_hotplug_enable; |
528 |
|
529 |
PIIX4_DPRINTF("pci_up_read %x\n", val);
|
530 |
return val;
|
531 |
} |
532 |
|
533 |
static uint32_t pci_down_read(void *opaque, uint32_t addr) |
534 |
{ |
535 |
PIIX4PMState *s = opaque; |
536 |
uint32_t val = s->pci0_status.down; |
537 |
|
538 |
PIIX4_DPRINTF("pci_down_read %x\n", val);
|
539 |
return val;
|
540 |
} |
541 |
|
542 |
static uint32_t pci_features_read(void *opaque, uint32_t addr) |
543 |
{ |
544 |
/* No feature defined yet */
|
545 |
PIIX4_DPRINTF("pci_features_read %x\n", 0); |
546 |
return 0; |
547 |
} |
548 |
|
549 |
static void pciej_write(void *opaque, uint32_t addr, uint32_t val) |
550 |
{ |
551 |
acpi_piix_eject_slot(opaque, val); |
552 |
|
553 |
PIIX4_DPRINTF("pciej write %x <== %d\n", addr, val);
|
554 |
} |
555 |
|
556 |
static uint32_t pcirmv_read(void *opaque, uint32_t addr) |
557 |
{ |
558 |
PIIX4PMState *s = opaque; |
559 |
|
560 |
return s->pci0_hotplug_enable;
|
561 |
} |
562 |
|
563 |
static int piix4_device_hotplug(DeviceState *qdev, PCIDevice *dev, |
564 |
PCIHotplugState state); |
565 |
|
566 |
static void piix4_acpi_system_hot_add_init(PCIBus *bus, PIIX4PMState *s) |
567 |
{ |
568 |
|
569 |
register_ioport_write(GPE_BASE, GPE_LEN, 1, gpe_writeb, s);
|
570 |
register_ioport_read(GPE_BASE, GPE_LEN, 1, gpe_readb, s);
|
571 |
acpi_gpe_blk(&s->ar, GPE_BASE); |
572 |
|
573 |
register_ioport_read(PCI_UP_BASE, 4, 4, pci_up_read, s); |
574 |
register_ioport_read(PCI_DOWN_BASE, 4, 4, pci_down_read, s); |
575 |
|
576 |
register_ioport_write(PCI_EJ_BASE, 4, 4, pciej_write, s); |
577 |
register_ioport_read(PCI_EJ_BASE, 4, 4, pci_features_read, s); |
578 |
|
579 |
register_ioport_read(PCI_RMV_BASE, 4, 4, pcirmv_read, s); |
580 |
|
581 |
pci_bus_hotplug(bus, piix4_device_hotplug, &s->dev.qdev); |
582 |
} |
583 |
|
584 |
static void enable_device(PIIX4PMState *s, int slot) |
585 |
{ |
586 |
s->ar.gpe.sts[0] |= PIIX4_PCI_HOTPLUG_STATUS;
|
587 |
s->pci0_slot_device_present |= (1U << slot);
|
588 |
} |
589 |
|
590 |
static void disable_device(PIIX4PMState *s, int slot) |
591 |
{ |
592 |
s->ar.gpe.sts[0] |= PIIX4_PCI_HOTPLUG_STATUS;
|
593 |
s->pci0_status.down |= (1U << slot);
|
594 |
} |
595 |
|
596 |
static int piix4_device_hotplug(DeviceState *qdev, PCIDevice *dev, |
597 |
PCIHotplugState state) |
598 |
{ |
599 |
int slot = PCI_SLOT(dev->devfn);
|
600 |
PIIX4PMState *s = DO_UPCAST(PIIX4PMState, dev, |
601 |
PCI_DEVICE(qdev)); |
602 |
|
603 |
/* Don't send event when device is enabled during qemu machine creation:
|
604 |
* it is present on boot, no hotplug event is necessary. We do send an
|
605 |
* event when the device is disabled later. */
|
606 |
if (state == PCI_COLDPLUG_ENABLED) {
|
607 |
s->pci0_slot_device_present |= (1U << slot);
|
608 |
return 0; |
609 |
} |
610 |
|
611 |
if (state == PCI_HOTPLUG_ENABLED) {
|
612 |
enable_device(s, slot); |
613 |
} else {
|
614 |
disable_device(s, slot); |
615 |
} |
616 |
|
617 |
pm_update_sci(s); |
618 |
|
619 |
return 0; |
620 |
} |