root / hw / hpet.c @ a1bc20df
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/*
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* High Precisition Event Timer emulation
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*
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* Copyright (c) 2007 Alexander Graf
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* Copyright (c) 2008 IBM Corporation
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*
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* Authors: Beth Kon <bkon@us.ibm.com>
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*
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* *****************************************************************
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*
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* This driver attempts to emulate an HPET device in software.
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*/
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#include "hw.h" |
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#include "pc.h" |
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#include "console.h" |
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#include "qemu-timer.h" |
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#include "hpet_emul.h" |
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#include "sysbus.h" |
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#include "mc146818rtc.h" |
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#include "i8254.h" |
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//#define HPET_DEBUG
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#ifdef HPET_DEBUG
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#define DPRINTF printf
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#else
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#define DPRINTF(...)
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#endif
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#define HPET_MSI_SUPPORT 0 |
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struct HPETState;
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typedef struct HPETTimer { /* timers */ |
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uint8_t tn; /*timer number*/
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QEMUTimer *qemu_timer; |
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struct HPETState *state;
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/* Memory-mapped, software visible timer registers */
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uint64_t config; /* configuration/cap */
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uint64_t cmp; /* comparator */
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uint64_t fsb; /* FSB route */
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/* Hidden register state */
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uint64_t period; /* Last value written to comparator */
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uint8_t wrap_flag; /* timer pop will indicate wrap for one-shot 32-bit
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* mode. Next pop will be actual timer expiration.
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*/
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} HPETTimer; |
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typedef struct HPETState { |
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SysBusDevice busdev; |
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MemoryRegion iomem; |
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uint64_t hpet_offset; |
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qemu_irq irqs[HPET_NUM_IRQ_ROUTES]; |
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uint32_t flags; |
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uint8_t rtc_irq_level; |
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qemu_irq pit_enabled; |
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uint8_t num_timers; |
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HPETTimer timer[HPET_MAX_TIMERS]; |
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/* Memory-mapped, software visible registers */
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uint64_t capability; /* capabilities */
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uint64_t config; /* configuration */
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uint64_t isr; /* interrupt status reg */
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uint64_t hpet_counter; /* main counter */
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uint8_t hpet_id; /* instance id */
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} HPETState; |
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static uint32_t hpet_in_legacy_mode(HPETState *s)
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{ |
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return s->config & HPET_CFG_LEGACY;
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} |
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static uint32_t timer_int_route(struct HPETTimer *timer) |
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{ |
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return (timer->config & HPET_TN_INT_ROUTE_MASK) >> HPET_TN_INT_ROUTE_SHIFT;
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} |
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static uint32_t timer_fsb_route(HPETTimer *t)
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{ |
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return t->config & HPET_TN_FSB_ENABLE;
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} |
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static uint32_t hpet_enabled(HPETState *s)
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{ |
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return s->config & HPET_CFG_ENABLE;
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} |
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static uint32_t timer_is_periodic(HPETTimer *t)
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{ |
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return t->config & HPET_TN_PERIODIC;
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} |
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static uint32_t timer_enabled(HPETTimer *t)
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{ |
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return t->config & HPET_TN_ENABLE;
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} |
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static uint32_t hpet_time_after(uint64_t a, uint64_t b)
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{ |
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return ((int32_t)(b) - (int32_t)(a) < 0); |
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} |
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static uint32_t hpet_time_after64(uint64_t a, uint64_t b)
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{ |
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return ((int64_t)(b) - (int64_t)(a) < 0); |
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} |
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static uint64_t ticks_to_ns(uint64_t value)
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{ |
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return (muldiv64(value, HPET_CLK_PERIOD, FS_PER_NS));
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} |
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static uint64_t ns_to_ticks(uint64_t value)
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{ |
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return (muldiv64(value, FS_PER_NS, HPET_CLK_PERIOD));
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} |
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static uint64_t hpet_fixup_reg(uint64_t new, uint64_t old, uint64_t mask)
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{ |
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new &= mask; |
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new |= old & ~mask; |
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return new;
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} |
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static int activating_bit(uint64_t old, uint64_t new, uint64_t mask) |
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{ |
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return (!(old & mask) && (new & mask));
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} |
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static int deactivating_bit(uint64_t old, uint64_t new, uint64_t mask) |
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{ |
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return ((old & mask) && !(new & mask));
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} |
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static uint64_t hpet_get_ticks(HPETState *s)
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{ |
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return ns_to_ticks(qemu_get_clock_ns(vm_clock) + s->hpet_offset);
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} |
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/*
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* calculate diff between comparator value and current ticks
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*/
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static inline uint64_t hpet_calculate_diff(HPETTimer *t, uint64_t current) |
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{ |
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if (t->config & HPET_TN_32BIT) {
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uint32_t diff, cmp; |
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cmp = (uint32_t)t->cmp; |
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diff = cmp - (uint32_t)current; |
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diff = (int32_t)diff > 0 ? diff : (uint32_t)1; |
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return (uint64_t)diff;
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} else {
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uint64_t diff, cmp; |
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cmp = t->cmp; |
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diff = cmp - current; |
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diff = (int64_t)diff > 0 ? diff : (uint64_t)1; |
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return diff;
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} |
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} |
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static void update_irq(struct HPETTimer *timer, int set) |
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{ |
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uint64_t mask; |
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HPETState *s; |
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int route;
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if (timer->tn <= 1 && hpet_in_legacy_mode(timer->state)) { |
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/* if LegacyReplacementRoute bit is set, HPET specification requires
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* timer0 be routed to IRQ0 in NON-APIC or IRQ2 in the I/O APIC,
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* timer1 be routed to IRQ8 in NON-APIC or IRQ8 in the I/O APIC.
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*/
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route = (timer->tn == 0) ? 0 : RTC_ISA_IRQ; |
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} else {
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route = timer_int_route(timer); |
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} |
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s = timer->state; |
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mask = 1 << timer->tn;
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if (!set || !timer_enabled(timer) || !hpet_enabled(timer->state)) {
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s->isr &= ~mask; |
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if (!timer_fsb_route(timer)) {
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qemu_irq_lower(s->irqs[route]); |
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} |
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} else if (timer_fsb_route(timer)) { |
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stl_le_phys(timer->fsb >> 32, timer->fsb & 0xffffffff); |
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} else if (timer->config & HPET_TN_TYPE_LEVEL) { |
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s->isr |= mask; |
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qemu_irq_raise(s->irqs[route]); |
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} else {
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s->isr &= ~mask; |
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qemu_irq_pulse(s->irqs[route]); |
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} |
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} |
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static void hpet_pre_save(void *opaque) |
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{ |
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HPETState *s = opaque; |
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/* save current counter value */
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s->hpet_counter = hpet_get_ticks(s); |
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} |
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static int hpet_pre_load(void *opaque) |
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{ |
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HPETState *s = opaque; |
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/* version 1 only supports 3, later versions will load the actual value */
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s->num_timers = HPET_MIN_TIMERS; |
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return 0; |
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} |
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static int hpet_post_load(void *opaque, int version_id) |
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{ |
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HPETState *s = opaque; |
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/* Recalculate the offset between the main counter and guest time */
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s->hpet_offset = ticks_to_ns(s->hpet_counter) - qemu_get_clock_ns(vm_clock); |
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/* Push number of timers into capability returned via HPET_ID */
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s->capability &= ~HPET_ID_NUM_TIM_MASK; |
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s->capability |= (s->num_timers - 1) << HPET_ID_NUM_TIM_SHIFT;
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hpet_cfg.hpet[s->hpet_id].event_timer_block_id = (uint32_t)s->capability; |
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/* Derive HPET_MSI_SUPPORT from the capability of the first timer. */
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s->flags &= ~(1 << HPET_MSI_SUPPORT);
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if (s->timer[0].config & HPET_TN_FSB_CAP) { |
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s->flags |= 1 << HPET_MSI_SUPPORT;
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} |
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return 0; |
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} |
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static bool hpet_rtc_irq_level_needed(void *opaque) |
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{ |
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HPETState *s = opaque; |
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return s->rtc_irq_level != 0; |
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} |
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static const VMStateDescription vmstate_hpet_rtc_irq_level = { |
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.name = "hpet/rtc_irq_level",
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.version_id = 1,
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.minimum_version_id = 1,
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.minimum_version_id_old = 1,
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.fields = (VMStateField[]) { |
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VMSTATE_UINT8(rtc_irq_level, HPETState), |
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VMSTATE_END_OF_LIST() |
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} |
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}; |
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static const VMStateDescription vmstate_hpet_timer = { |
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.name = "hpet_timer",
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.version_id = 1,
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.minimum_version_id = 1,
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.minimum_version_id_old = 1,
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.fields = (VMStateField []) { |
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VMSTATE_UINT8(tn, HPETTimer), |
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VMSTATE_UINT64(config, HPETTimer), |
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VMSTATE_UINT64(cmp, HPETTimer), |
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VMSTATE_UINT64(fsb, HPETTimer), |
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VMSTATE_UINT64(period, HPETTimer), |
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VMSTATE_UINT8(wrap_flag, HPETTimer), |
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VMSTATE_TIMER(qemu_timer, HPETTimer), |
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VMSTATE_END_OF_LIST() |
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} |
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}; |
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static const VMStateDescription vmstate_hpet = { |
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.name = "hpet",
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.version_id = 2,
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.minimum_version_id = 1,
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.minimum_version_id_old = 1,
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.pre_save = hpet_pre_save, |
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.pre_load = hpet_pre_load, |
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.post_load = hpet_post_load, |
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.fields = (VMStateField []) { |
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VMSTATE_UINT64(config, HPETState), |
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VMSTATE_UINT64(isr, HPETState), |
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VMSTATE_UINT64(hpet_counter, HPETState), |
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VMSTATE_UINT8_V(num_timers, HPETState, 2),
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VMSTATE_STRUCT_VARRAY_UINT8(timer, HPETState, num_timers, 0,
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vmstate_hpet_timer, HPETTimer), |
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VMSTATE_END_OF_LIST() |
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}, |
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.subsections = (VMStateSubsection[]) { |
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{ |
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.vmsd = &vmstate_hpet_rtc_irq_level, |
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.needed = hpet_rtc_irq_level_needed, |
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}, { |
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/* empty */
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} |
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} |
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}; |
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/*
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* timer expiration callback
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*/
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static void hpet_timer(void *opaque) |
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{ |
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HPETTimer *t = opaque; |
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uint64_t diff; |
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uint64_t period = t->period; |
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uint64_t cur_tick = hpet_get_ticks(t->state); |
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if (timer_is_periodic(t) && period != 0) { |
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if (t->config & HPET_TN_32BIT) {
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while (hpet_time_after(cur_tick, t->cmp)) {
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t->cmp = (uint32_t)(t->cmp + t->period); |
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} |
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} else {
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while (hpet_time_after64(cur_tick, t->cmp)) {
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t->cmp += period; |
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} |
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} |
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diff = hpet_calculate_diff(t, cur_tick); |
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qemu_mod_timer(t->qemu_timer, |
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qemu_get_clock_ns(vm_clock) + (int64_t)ticks_to_ns(diff)); |
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} else if (t->config & HPET_TN_32BIT && !timer_is_periodic(t)) { |
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if (t->wrap_flag) {
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diff = hpet_calculate_diff(t, cur_tick); |
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qemu_mod_timer(t->qemu_timer, qemu_get_clock_ns(vm_clock) + |
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(int64_t)ticks_to_ns(diff)); |
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t->wrap_flag = 0;
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} |
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} |
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update_irq(t, 1);
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} |
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static void hpet_set_timer(HPETTimer *t) |
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{ |
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uint64_t diff; |
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uint32_t wrap_diff; /* how many ticks until we wrap? */
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uint64_t cur_tick = hpet_get_ticks(t->state); |
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/* whenever new timer is being set up, make sure wrap_flag is 0 */
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t->wrap_flag = 0;
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diff = hpet_calculate_diff(t, cur_tick); |
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/* hpet spec says in one-shot 32-bit mode, generate an interrupt when
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* counter wraps in addition to an interrupt with comparator match.
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*/
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if (t->config & HPET_TN_32BIT && !timer_is_periodic(t)) {
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wrap_diff = 0xffffffff - (uint32_t)cur_tick;
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if (wrap_diff < (uint32_t)diff) {
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diff = wrap_diff; |
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t->wrap_flag = 1;
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} |
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} |
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qemu_mod_timer(t->qemu_timer, |
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qemu_get_clock_ns(vm_clock) + (int64_t)ticks_to_ns(diff)); |
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} |
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|
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static void hpet_del_timer(HPETTimer *t) |
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{ |
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qemu_del_timer(t->qemu_timer); |
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update_irq(t, 0);
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} |
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#ifdef HPET_DEBUG
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static uint32_t hpet_ram_readb(void *opaque, hwaddr addr) |
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{ |
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printf("qemu: hpet_read b at %" PRIx64 "\n", addr); |
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return 0; |
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} |
378 |
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static uint32_t hpet_ram_readw(void *opaque, hwaddr addr) |
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{ |
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printf("qemu: hpet_read w at %" PRIx64 "\n", addr); |
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return 0; |
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} |
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#endif
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static uint64_t hpet_ram_read(void *opaque, hwaddr addr, |
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unsigned size)
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{ |
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HPETState *s = opaque; |
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uint64_t cur_tick, index; |
391 |
|
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DPRINTF("qemu: Enter hpet_ram_readl at %" PRIx64 "\n", addr); |
393 |
index = addr; |
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/*address range of all TN regs*/
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if (index >= 0x100 && index <= 0x3ff) { |
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uint8_t timer_id = (addr - 0x100) / 0x20; |
397 |
HPETTimer *timer = &s->timer[timer_id]; |
398 |
|
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if (timer_id > s->num_timers) {
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DPRINTF("qemu: timer id out of range\n");
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return 0; |
402 |
} |
403 |
|
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switch ((addr - 0x100) % 0x20) { |
405 |
case HPET_TN_CFG:
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return timer->config;
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case HPET_TN_CFG + 4: // Interrupt capabilities |
408 |
return timer->config >> 32; |
409 |
case HPET_TN_CMP: // comparator register |
410 |
return timer->cmp;
|
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case HPET_TN_CMP + 4: |
412 |
return timer->cmp >> 32; |
413 |
case HPET_TN_ROUTE:
|
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return timer->fsb;
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case HPET_TN_ROUTE + 4: |
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return timer->fsb >> 32; |
417 |
default:
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418 |
DPRINTF("qemu: invalid hpet_ram_readl\n");
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419 |
break;
|
420 |
} |
421 |
} else {
|
422 |
switch (index) {
|
423 |
case HPET_ID:
|
424 |
return s->capability;
|
425 |
case HPET_PERIOD:
|
426 |
return s->capability >> 32; |
427 |
case HPET_CFG:
|
428 |
return s->config;
|
429 |
case HPET_CFG + 4: |
430 |
DPRINTF("qemu: invalid HPET_CFG + 4 hpet_ram_readl\n");
|
431 |
return 0; |
432 |
case HPET_COUNTER:
|
433 |
if (hpet_enabled(s)) {
|
434 |
cur_tick = hpet_get_ticks(s); |
435 |
} else {
|
436 |
cur_tick = s->hpet_counter; |
437 |
} |
438 |
DPRINTF("qemu: reading counter = %" PRIx64 "\n", cur_tick); |
439 |
return cur_tick;
|
440 |
case HPET_COUNTER + 4: |
441 |
if (hpet_enabled(s)) {
|
442 |
cur_tick = hpet_get_ticks(s); |
443 |
} else {
|
444 |
cur_tick = s->hpet_counter; |
445 |
} |
446 |
DPRINTF("qemu: reading counter + 4 = %" PRIx64 "\n", cur_tick); |
447 |
return cur_tick >> 32; |
448 |
case HPET_STATUS:
|
449 |
return s->isr;
|
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default:
|
451 |
DPRINTF("qemu: invalid hpet_ram_readl\n");
|
452 |
break;
|
453 |
} |
454 |
} |
455 |
return 0; |
456 |
} |
457 |
|
458 |
static void hpet_ram_write(void *opaque, hwaddr addr, |
459 |
uint64_t value, unsigned size)
|
460 |
{ |
461 |
int i;
|
462 |
HPETState *s = opaque; |
463 |
uint64_t old_val, new_val, val, index; |
464 |
|
465 |
DPRINTF("qemu: Enter hpet_ram_writel at %" PRIx64 " = %#x\n", addr, value); |
466 |
index = addr; |
467 |
old_val = hpet_ram_read(opaque, addr, 4);
|
468 |
new_val = value; |
469 |
|
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/*address range of all TN regs*/
|
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if (index >= 0x100 && index <= 0x3ff) { |
472 |
uint8_t timer_id = (addr - 0x100) / 0x20; |
473 |
HPETTimer *timer = &s->timer[timer_id]; |
474 |
|
475 |
DPRINTF("qemu: hpet_ram_writel timer_id = %#x\n", timer_id);
|
476 |
if (timer_id > s->num_timers) {
|
477 |
DPRINTF("qemu: timer id out of range\n");
|
478 |
return;
|
479 |
} |
480 |
switch ((addr - 0x100) % 0x20) { |
481 |
case HPET_TN_CFG:
|
482 |
DPRINTF("qemu: hpet_ram_writel HPET_TN_CFG\n");
|
483 |
if (activating_bit(old_val, new_val, HPET_TN_FSB_ENABLE)) {
|
484 |
update_irq(timer, 0);
|
485 |
} |
486 |
val = hpet_fixup_reg(new_val, old_val, HPET_TN_CFG_WRITE_MASK); |
487 |
timer->config = (timer->config & 0xffffffff00000000ULL) | val;
|
488 |
if (new_val & HPET_TN_32BIT) {
|
489 |
timer->cmp = (uint32_t)timer->cmp; |
490 |
timer->period = (uint32_t)timer->period; |
491 |
} |
492 |
if (activating_bit(old_val, new_val, HPET_TN_ENABLE)) {
|
493 |
hpet_set_timer(timer); |
494 |
} else if (deactivating_bit(old_val, new_val, HPET_TN_ENABLE)) { |
495 |
hpet_del_timer(timer); |
496 |
} |
497 |
break;
|
498 |
case HPET_TN_CFG + 4: // Interrupt capabilities |
499 |
DPRINTF("qemu: invalid HPET_TN_CFG+4 write\n");
|
500 |
break;
|
501 |
case HPET_TN_CMP: // comparator register |
502 |
DPRINTF("qemu: hpet_ram_writel HPET_TN_CMP\n");
|
503 |
if (timer->config & HPET_TN_32BIT) {
|
504 |
new_val = (uint32_t)new_val; |
505 |
} |
506 |
if (!timer_is_periodic(timer)
|
507 |
|| (timer->config & HPET_TN_SETVAL)) { |
508 |
timer->cmp = (timer->cmp & 0xffffffff00000000ULL) | new_val;
|
509 |
} |
510 |
if (timer_is_periodic(timer)) {
|
511 |
/*
|
512 |
* FIXME: Clamp period to reasonable min value?
|
513 |
* Clamp period to reasonable max value
|
514 |
*/
|
515 |
new_val &= (timer->config & HPET_TN_32BIT ? ~0u : ~0ull) >> 1; |
516 |
timer->period = |
517 |
(timer->period & 0xffffffff00000000ULL) | new_val;
|
518 |
} |
519 |
timer->config &= ~HPET_TN_SETVAL; |
520 |
if (hpet_enabled(s)) {
|
521 |
hpet_set_timer(timer); |
522 |
} |
523 |
break;
|
524 |
case HPET_TN_CMP + 4: // comparator register high order |
525 |
DPRINTF("qemu: hpet_ram_writel HPET_TN_CMP + 4\n");
|
526 |
if (!timer_is_periodic(timer)
|
527 |
|| (timer->config & HPET_TN_SETVAL)) { |
528 |
timer->cmp = (timer->cmp & 0xffffffffULL) | new_val << 32; |
529 |
} else {
|
530 |
/*
|
531 |
* FIXME: Clamp period to reasonable min value?
|
532 |
* Clamp period to reasonable max value
|
533 |
*/
|
534 |
new_val &= (timer->config & HPET_TN_32BIT ? ~0u : ~0ull) >> 1; |
535 |
timer->period = |
536 |
(timer->period & 0xffffffffULL) | new_val << 32; |
537 |
} |
538 |
timer->config &= ~HPET_TN_SETVAL; |
539 |
if (hpet_enabled(s)) {
|
540 |
hpet_set_timer(timer); |
541 |
} |
542 |
break;
|
543 |
case HPET_TN_ROUTE:
|
544 |
timer->fsb = (timer->fsb & 0xffffffff00000000ULL) | new_val;
|
545 |
break;
|
546 |
case HPET_TN_ROUTE + 4: |
547 |
timer->fsb = (new_val << 32) | (timer->fsb & 0xffffffff); |
548 |
break;
|
549 |
default:
|
550 |
DPRINTF("qemu: invalid hpet_ram_writel\n");
|
551 |
break;
|
552 |
} |
553 |
return;
|
554 |
} else {
|
555 |
switch (index) {
|
556 |
case HPET_ID:
|
557 |
return;
|
558 |
case HPET_CFG:
|
559 |
val = hpet_fixup_reg(new_val, old_val, HPET_CFG_WRITE_MASK); |
560 |
s->config = (s->config & 0xffffffff00000000ULL) | val;
|
561 |
if (activating_bit(old_val, new_val, HPET_CFG_ENABLE)) {
|
562 |
/* Enable main counter and interrupt generation. */
|
563 |
s->hpet_offset = |
564 |
ticks_to_ns(s->hpet_counter) - qemu_get_clock_ns(vm_clock); |
565 |
for (i = 0; i < s->num_timers; i++) { |
566 |
if ((&s->timer[i])->cmp != ~0ULL) { |
567 |
hpet_set_timer(&s->timer[i]); |
568 |
} |
569 |
} |
570 |
} else if (deactivating_bit(old_val, new_val, HPET_CFG_ENABLE)) { |
571 |
/* Halt main counter and disable interrupt generation. */
|
572 |
s->hpet_counter = hpet_get_ticks(s); |
573 |
for (i = 0; i < s->num_timers; i++) { |
574 |
hpet_del_timer(&s->timer[i]); |
575 |
} |
576 |
} |
577 |
/* i8254 and RTC output pins are disabled
|
578 |
* when HPET is in legacy mode */
|
579 |
if (activating_bit(old_val, new_val, HPET_CFG_LEGACY)) {
|
580 |
qemu_set_irq(s->pit_enabled, 0);
|
581 |
qemu_irq_lower(s->irqs[0]);
|
582 |
qemu_irq_lower(s->irqs[RTC_ISA_IRQ]); |
583 |
} else if (deactivating_bit(old_val, new_val, HPET_CFG_LEGACY)) { |
584 |
qemu_irq_lower(s->irqs[0]);
|
585 |
qemu_set_irq(s->pit_enabled, 1);
|
586 |
qemu_set_irq(s->irqs[RTC_ISA_IRQ], s->rtc_irq_level); |
587 |
} |
588 |
break;
|
589 |
case HPET_CFG + 4: |
590 |
DPRINTF("qemu: invalid HPET_CFG+4 write\n");
|
591 |
break;
|
592 |
case HPET_STATUS:
|
593 |
val = new_val & s->isr; |
594 |
for (i = 0; i < s->num_timers; i++) { |
595 |
if (val & (1 << i)) { |
596 |
update_irq(&s->timer[i], 0);
|
597 |
} |
598 |
} |
599 |
break;
|
600 |
case HPET_COUNTER:
|
601 |
if (hpet_enabled(s)) {
|
602 |
DPRINTF("qemu: Writing counter while HPET enabled!\n");
|
603 |
} |
604 |
s->hpet_counter = |
605 |
(s->hpet_counter & 0xffffffff00000000ULL) | value;
|
606 |
DPRINTF("qemu: HPET counter written. ctr = %#x -> %" PRIx64 "\n", |
607 |
value, s->hpet_counter); |
608 |
break;
|
609 |
case HPET_COUNTER + 4: |
610 |
if (hpet_enabled(s)) {
|
611 |
DPRINTF("qemu: Writing counter while HPET enabled!\n");
|
612 |
} |
613 |
s->hpet_counter = |
614 |
(s->hpet_counter & 0xffffffffULL) | (((uint64_t)value) << 32); |
615 |
DPRINTF("qemu: HPET counter + 4 written. ctr = %#x -> %" PRIx64 "\n", |
616 |
value, s->hpet_counter); |
617 |
break;
|
618 |
default:
|
619 |
DPRINTF("qemu: invalid hpet_ram_writel\n");
|
620 |
break;
|
621 |
} |
622 |
} |
623 |
} |
624 |
|
625 |
static const MemoryRegionOps hpet_ram_ops = { |
626 |
.read = hpet_ram_read, |
627 |
.write = hpet_ram_write, |
628 |
.valid = { |
629 |
.min_access_size = 4,
|
630 |
.max_access_size = 4,
|
631 |
}, |
632 |
.endianness = DEVICE_NATIVE_ENDIAN, |
633 |
}; |
634 |
|
635 |
static void hpet_reset(DeviceState *d) |
636 |
{ |
637 |
HPETState *s = FROM_SYSBUS(HPETState, sysbus_from_qdev(d)); |
638 |
int i;
|
639 |
|
640 |
for (i = 0; i < s->num_timers; i++) { |
641 |
HPETTimer *timer = &s->timer[i]; |
642 |
|
643 |
hpet_del_timer(timer); |
644 |
timer->cmp = ~0ULL;
|
645 |
timer->config = HPET_TN_PERIODIC_CAP | HPET_TN_SIZE_CAP; |
646 |
if (s->flags & (1 << HPET_MSI_SUPPORT)) { |
647 |
timer->config |= HPET_TN_FSB_CAP; |
648 |
} |
649 |
/* advertise availability of ioapic inti2 */
|
650 |
timer->config |= 0x00000004ULL << 32; |
651 |
timer->period = 0ULL;
|
652 |
timer->wrap_flag = 0;
|
653 |
} |
654 |
|
655 |
qemu_set_irq(s->pit_enabled, 1);
|
656 |
s->hpet_counter = 0ULL;
|
657 |
s->hpet_offset = 0ULL;
|
658 |
s->config = 0ULL;
|
659 |
hpet_cfg.hpet[s->hpet_id].event_timer_block_id = (uint32_t)s->capability; |
660 |
hpet_cfg.hpet[s->hpet_id].address = sysbus_from_qdev(d)->mmio[0].addr;
|
661 |
|
662 |
/* to document that the RTC lowers its output on reset as well */
|
663 |
s->rtc_irq_level = 0;
|
664 |
} |
665 |
|
666 |
static void hpet_handle_legacy_irq(void *opaque, int n, int level) |
667 |
{ |
668 |
HPETState *s = FROM_SYSBUS(HPETState, opaque); |
669 |
|
670 |
if (n == HPET_LEGACY_PIT_INT) {
|
671 |
if (!hpet_in_legacy_mode(s)) {
|
672 |
qemu_set_irq(s->irqs[0], level);
|
673 |
} |
674 |
} else {
|
675 |
s->rtc_irq_level = level; |
676 |
if (!hpet_in_legacy_mode(s)) {
|
677 |
qemu_set_irq(s->irqs[RTC_ISA_IRQ], level); |
678 |
} |
679 |
} |
680 |
} |
681 |
|
682 |
static int hpet_init(SysBusDevice *dev) |
683 |
{ |
684 |
HPETState *s = FROM_SYSBUS(HPETState, dev); |
685 |
int i;
|
686 |
HPETTimer *timer; |
687 |
|
688 |
if (hpet_cfg.count == UINT8_MAX) {
|
689 |
/* first instance */
|
690 |
hpet_cfg.count = 0;
|
691 |
} |
692 |
|
693 |
if (hpet_cfg.count == 8) { |
694 |
fprintf(stderr, "Only 8 instances of HPET is allowed\n");
|
695 |
return -1; |
696 |
} |
697 |
|
698 |
s->hpet_id = hpet_cfg.count++; |
699 |
|
700 |
for (i = 0; i < HPET_NUM_IRQ_ROUTES; i++) { |
701 |
sysbus_init_irq(dev, &s->irqs[i]); |
702 |
} |
703 |
|
704 |
if (s->num_timers < HPET_MIN_TIMERS) {
|
705 |
s->num_timers = HPET_MIN_TIMERS; |
706 |
} else if (s->num_timers > HPET_MAX_TIMERS) { |
707 |
s->num_timers = HPET_MAX_TIMERS; |
708 |
} |
709 |
for (i = 0; i < HPET_MAX_TIMERS; i++) { |
710 |
timer = &s->timer[i]; |
711 |
timer->qemu_timer = qemu_new_timer_ns(vm_clock, hpet_timer, timer); |
712 |
timer->tn = i; |
713 |
timer->state = s; |
714 |
} |
715 |
|
716 |
/* 64-bit main counter; LegacyReplacementRoute. */
|
717 |
s->capability = 0x8086a001ULL;
|
718 |
s->capability |= (s->num_timers - 1) << HPET_ID_NUM_TIM_SHIFT;
|
719 |
s->capability |= ((HPET_CLK_PERIOD) << 32);
|
720 |
|
721 |
qdev_init_gpio_in(&dev->qdev, hpet_handle_legacy_irq, 2);
|
722 |
qdev_init_gpio_out(&dev->qdev, &s->pit_enabled, 1);
|
723 |
|
724 |
/* HPET Area */
|
725 |
memory_region_init_io(&s->iomem, &hpet_ram_ops, s, "hpet", 0x400); |
726 |
sysbus_init_mmio(dev, &s->iomem); |
727 |
return 0; |
728 |
} |
729 |
|
730 |
static Property hpet_device_properties[] = {
|
731 |
DEFINE_PROP_UINT8("timers", HPETState, num_timers, HPET_MIN_TIMERS),
|
732 |
DEFINE_PROP_BIT("msi", HPETState, flags, HPET_MSI_SUPPORT, false), |
733 |
DEFINE_PROP_END_OF_LIST(), |
734 |
}; |
735 |
|
736 |
static void hpet_device_class_init(ObjectClass *klass, void *data) |
737 |
{ |
738 |
DeviceClass *dc = DEVICE_CLASS(klass); |
739 |
SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); |
740 |
|
741 |
k->init = hpet_init; |
742 |
dc->no_user = 1;
|
743 |
dc->reset = hpet_reset; |
744 |
dc->vmsd = &vmstate_hpet; |
745 |
dc->props = hpet_device_properties; |
746 |
} |
747 |
|
748 |
static TypeInfo hpet_device_info = {
|
749 |
.name = "hpet",
|
750 |
.parent = TYPE_SYS_BUS_DEVICE, |
751 |
.instance_size = sizeof(HPETState),
|
752 |
.class_init = hpet_device_class_init, |
753 |
}; |
754 |
|
755 |
static void hpet_register_types(void) |
756 |
{ |
757 |
type_register_static(&hpet_device_info); |
758 |
} |
759 |
|
760 |
type_init(hpet_register_types) |