root / hw / arm_gic_common.c @ a1e47211
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1 | 1e8cae4d | Peter Maydell | /*
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2 | 1e8cae4d | Peter Maydell | * ARM GIC support - common bits of emulated and KVM kernel model
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3 | 1e8cae4d | Peter Maydell | *
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4 | 1e8cae4d | Peter Maydell | * Copyright (c) 2012 Linaro Limited
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5 | 1e8cae4d | Peter Maydell | * Written by Peter Maydell
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6 | 1e8cae4d | Peter Maydell | *
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7 | 1e8cae4d | Peter Maydell | * This program is free software; you can redistribute it and/or modify
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8 | 1e8cae4d | Peter Maydell | * it under the terms of the GNU General Public License as published by
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9 | 1e8cae4d | Peter Maydell | * the Free Software Foundation, either version 2 of the License, or
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10 | 1e8cae4d | Peter Maydell | * (at your option) any later version.
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11 | 1e8cae4d | Peter Maydell | *
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12 | 1e8cae4d | Peter Maydell | * This program is distributed in the hope that it will be useful,
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13 | 1e8cae4d | Peter Maydell | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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14 | 1e8cae4d | Peter Maydell | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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15 | 1e8cae4d | Peter Maydell | * GNU General Public License for more details.
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16 | 1e8cae4d | Peter Maydell | *
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17 | 1e8cae4d | Peter Maydell | * You should have received a copy of the GNU General Public License along
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18 | 1e8cae4d | Peter Maydell | * with this program; if not, see <http://www.gnu.org/licenses/>.
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19 | 1e8cae4d | Peter Maydell | */
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20 | 1e8cae4d | Peter Maydell | |
21 | 1e8cae4d | Peter Maydell | #include "arm_gic_internal.h" |
22 | 1e8cae4d | Peter Maydell | |
23 | 1e8cae4d | Peter Maydell | static void gic_save(QEMUFile *f, void *opaque) |
24 | 1e8cae4d | Peter Maydell | { |
25 | 1e8cae4d | Peter Maydell | gic_state *s = (gic_state *)opaque; |
26 | 1e8cae4d | Peter Maydell | int i;
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27 | 1e8cae4d | Peter Maydell | int j;
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28 | 1e8cae4d | Peter Maydell | |
29 | 1e8cae4d | Peter Maydell | qemu_put_be32(f, s->enabled); |
30 | 1e8cae4d | Peter Maydell | for (i = 0; i < s->num_cpu; i++) { |
31 | 1e8cae4d | Peter Maydell | qemu_put_be32(f, s->cpu_enabled[i]); |
32 | 1e8cae4d | Peter Maydell | for (j = 0; j < GIC_INTERNAL; j++) { |
33 | 1e8cae4d | Peter Maydell | qemu_put_be32(f, s->priority1[j][i]); |
34 | 1e8cae4d | Peter Maydell | } |
35 | 1e8cae4d | Peter Maydell | for (j = 0; j < s->num_irq; j++) { |
36 | 1e8cae4d | Peter Maydell | qemu_put_be32(f, s->last_active[j][i]); |
37 | 1e8cae4d | Peter Maydell | } |
38 | 1e8cae4d | Peter Maydell | qemu_put_be32(f, s->priority_mask[i]); |
39 | 1e8cae4d | Peter Maydell | qemu_put_be32(f, s->running_irq[i]); |
40 | 1e8cae4d | Peter Maydell | qemu_put_be32(f, s->running_priority[i]); |
41 | 1e8cae4d | Peter Maydell | qemu_put_be32(f, s->current_pending[i]); |
42 | 1e8cae4d | Peter Maydell | } |
43 | 1e8cae4d | Peter Maydell | for (i = 0; i < s->num_irq - GIC_INTERNAL; i++) { |
44 | 1e8cae4d | Peter Maydell | qemu_put_be32(f, s->priority2[i]); |
45 | 1e8cae4d | Peter Maydell | } |
46 | 1e8cae4d | Peter Maydell | for (i = 0; i < s->num_irq; i++) { |
47 | 1e8cae4d | Peter Maydell | qemu_put_be32(f, s->irq_target[i]); |
48 | 1e8cae4d | Peter Maydell | qemu_put_byte(f, s->irq_state[i].enabled); |
49 | 1e8cae4d | Peter Maydell | qemu_put_byte(f, s->irq_state[i].pending); |
50 | 1e8cae4d | Peter Maydell | qemu_put_byte(f, s->irq_state[i].active); |
51 | 1e8cae4d | Peter Maydell | qemu_put_byte(f, s->irq_state[i].level); |
52 | 1e8cae4d | Peter Maydell | qemu_put_byte(f, s->irq_state[i].model); |
53 | 1e8cae4d | Peter Maydell | qemu_put_byte(f, s->irq_state[i].trigger); |
54 | 1e8cae4d | Peter Maydell | } |
55 | 1e8cae4d | Peter Maydell | } |
56 | 1e8cae4d | Peter Maydell | |
57 | 1e8cae4d | Peter Maydell | static int gic_load(QEMUFile *f, void *opaque, int version_id) |
58 | 1e8cae4d | Peter Maydell | { |
59 | 1e8cae4d | Peter Maydell | gic_state *s = (gic_state *)opaque; |
60 | 1e8cae4d | Peter Maydell | int i;
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61 | 1e8cae4d | Peter Maydell | int j;
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62 | 1e8cae4d | Peter Maydell | |
63 | 1e8cae4d | Peter Maydell | if (version_id != 3) { |
64 | 1e8cae4d | Peter Maydell | return -EINVAL;
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65 | 1e8cae4d | Peter Maydell | } |
66 | 1e8cae4d | Peter Maydell | |
67 | 1e8cae4d | Peter Maydell | s->enabled = qemu_get_be32(f); |
68 | 1e8cae4d | Peter Maydell | for (i = 0; i < s->num_cpu; i++) { |
69 | 1e8cae4d | Peter Maydell | s->cpu_enabled[i] = qemu_get_be32(f); |
70 | 1e8cae4d | Peter Maydell | for (j = 0; j < GIC_INTERNAL; j++) { |
71 | 1e8cae4d | Peter Maydell | s->priority1[j][i] = qemu_get_be32(f); |
72 | 1e8cae4d | Peter Maydell | } |
73 | 1e8cae4d | Peter Maydell | for (j = 0; j < s->num_irq; j++) { |
74 | 1e8cae4d | Peter Maydell | s->last_active[j][i] = qemu_get_be32(f); |
75 | 1e8cae4d | Peter Maydell | } |
76 | 1e8cae4d | Peter Maydell | s->priority_mask[i] = qemu_get_be32(f); |
77 | 1e8cae4d | Peter Maydell | s->running_irq[i] = qemu_get_be32(f); |
78 | 1e8cae4d | Peter Maydell | s->running_priority[i] = qemu_get_be32(f); |
79 | 1e8cae4d | Peter Maydell | s->current_pending[i] = qemu_get_be32(f); |
80 | 1e8cae4d | Peter Maydell | } |
81 | 1e8cae4d | Peter Maydell | for (i = 0; i < s->num_irq - GIC_INTERNAL; i++) { |
82 | 1e8cae4d | Peter Maydell | s->priority2[i] = qemu_get_be32(f); |
83 | 1e8cae4d | Peter Maydell | } |
84 | 1e8cae4d | Peter Maydell | for (i = 0; i < s->num_irq; i++) { |
85 | 1e8cae4d | Peter Maydell | s->irq_target[i] = qemu_get_be32(f); |
86 | 1e8cae4d | Peter Maydell | s->irq_state[i].enabled = qemu_get_byte(f); |
87 | 1e8cae4d | Peter Maydell | s->irq_state[i].pending = qemu_get_byte(f); |
88 | 1e8cae4d | Peter Maydell | s->irq_state[i].active = qemu_get_byte(f); |
89 | 1e8cae4d | Peter Maydell | s->irq_state[i].level = qemu_get_byte(f); |
90 | 1e8cae4d | Peter Maydell | s->irq_state[i].model = qemu_get_byte(f); |
91 | 1e8cae4d | Peter Maydell | s->irq_state[i].trigger = qemu_get_byte(f); |
92 | 1e8cae4d | Peter Maydell | } |
93 | 1e8cae4d | Peter Maydell | |
94 | 1e8cae4d | Peter Maydell | return 0; |
95 | 1e8cae4d | Peter Maydell | } |
96 | 1e8cae4d | Peter Maydell | |
97 | 1e8cae4d | Peter Maydell | static int arm_gic_common_init(SysBusDevice *dev) |
98 | 1e8cae4d | Peter Maydell | { |
99 | 1e8cae4d | Peter Maydell | gic_state *s = FROM_SYSBUS(gic_state, dev); |
100 | 1e8cae4d | Peter Maydell | int num_irq = s->num_irq;
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101 | 1e8cae4d | Peter Maydell | |
102 | 1e8cae4d | Peter Maydell | if (s->num_cpu > NCPU) {
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103 | 1e8cae4d | Peter Maydell | hw_error("requested %u CPUs exceeds GIC maximum %d\n",
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104 | 1e8cae4d | Peter Maydell | s->num_cpu, NCPU); |
105 | 1e8cae4d | Peter Maydell | } |
106 | 1e8cae4d | Peter Maydell | s->num_irq += GIC_BASE_IRQ; |
107 | 1e8cae4d | Peter Maydell | if (s->num_irq > GIC_MAXIRQ) {
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108 | 1e8cae4d | Peter Maydell | hw_error("requested %u interrupt lines exceeds GIC maximum %d\n",
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109 | 1e8cae4d | Peter Maydell | num_irq, GIC_MAXIRQ); |
110 | 1e8cae4d | Peter Maydell | } |
111 | 1e8cae4d | Peter Maydell | /* ITLinesNumber is represented as (N / 32) - 1 (see
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112 | 1e8cae4d | Peter Maydell | * gic_dist_readb) so this is an implementation imposed
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113 | 1e8cae4d | Peter Maydell | * restriction, not an architectural one:
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114 | 1e8cae4d | Peter Maydell | */
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115 | 1e8cae4d | Peter Maydell | if (s->num_irq < 32 || (s->num_irq % 32)) { |
116 | 1e8cae4d | Peter Maydell | hw_error("%d interrupt lines unsupported: not divisible by 32\n",
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117 | 1e8cae4d | Peter Maydell | num_irq); |
118 | 1e8cae4d | Peter Maydell | } |
119 | 1e8cae4d | Peter Maydell | |
120 | 1e8cae4d | Peter Maydell | register_savevm(NULL, "arm_gic", -1, 3, gic_save, gic_load, s); |
121 | 1e8cae4d | Peter Maydell | return 0; |
122 | 1e8cae4d | Peter Maydell | } |
123 | 1e8cae4d | Peter Maydell | |
124 | 1e8cae4d | Peter Maydell | static void arm_gic_common_reset(DeviceState *dev) |
125 | 1e8cae4d | Peter Maydell | { |
126 | 1e8cae4d | Peter Maydell | gic_state *s = FROM_SYSBUS(gic_state, sysbus_from_qdev(dev)); |
127 | 1e8cae4d | Peter Maydell | int i;
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128 | 1e8cae4d | Peter Maydell | memset(s->irq_state, 0, GIC_MAXIRQ * sizeof(gic_irq_state)); |
129 | 1e8cae4d | Peter Maydell | for (i = 0 ; i < s->num_cpu; i++) { |
130 | 1e8cae4d | Peter Maydell | s->priority_mask[i] = 0xf0;
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131 | 1e8cae4d | Peter Maydell | s->current_pending[i] = 1023;
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132 | 1e8cae4d | Peter Maydell | s->running_irq[i] = 1023;
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133 | 1e8cae4d | Peter Maydell | s->running_priority[i] = 0x100;
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134 | 1e8cae4d | Peter Maydell | s->cpu_enabled[i] = 0;
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135 | 1e8cae4d | Peter Maydell | } |
136 | 1e8cae4d | Peter Maydell | for (i = 0; i < 16; i++) { |
137 | 1e8cae4d | Peter Maydell | GIC_SET_ENABLED(i, ALL_CPU_MASK); |
138 | 1e8cae4d | Peter Maydell | GIC_SET_TRIGGER(i); |
139 | 1e8cae4d | Peter Maydell | } |
140 | 1e8cae4d | Peter Maydell | if (s->num_cpu == 1) { |
141 | 1e8cae4d | Peter Maydell | /* For uniprocessor GICs all interrupts always target the sole CPU */
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142 | 1e8cae4d | Peter Maydell | for (i = 0; i < GIC_MAXIRQ; i++) { |
143 | 1e8cae4d | Peter Maydell | s->irq_target[i] = 1;
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144 | 1e8cae4d | Peter Maydell | } |
145 | 1e8cae4d | Peter Maydell | } |
146 | 1e8cae4d | Peter Maydell | s->enabled = 0;
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147 | 1e8cae4d | Peter Maydell | } |
148 | 1e8cae4d | Peter Maydell | |
149 | 1e8cae4d | Peter Maydell | static Property arm_gic_common_properties[] = {
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150 | 1e8cae4d | Peter Maydell | DEFINE_PROP_UINT32("num-cpu", gic_state, num_cpu, 1), |
151 | 1e8cae4d | Peter Maydell | DEFINE_PROP_UINT32("num-irq", gic_state, num_irq, 32), |
152 | 1e8cae4d | Peter Maydell | /* Revision can be 1 or 2 for GIC architecture specification
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153 | 1e8cae4d | Peter Maydell | * versions 1 or 2, or 0 to indicate the legacy 11MPCore GIC.
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154 | 1e8cae4d | Peter Maydell | * (Internally, 0xffffffff also indicates "not a GIC but an NVIC".)
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155 | 1e8cae4d | Peter Maydell | */
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156 | 1e8cae4d | Peter Maydell | DEFINE_PROP_UINT32("revision", gic_state, revision, 1), |
157 | 1e8cae4d | Peter Maydell | DEFINE_PROP_END_OF_LIST(), |
158 | 1e8cae4d | Peter Maydell | }; |
159 | 1e8cae4d | Peter Maydell | |
160 | 1e8cae4d | Peter Maydell | static void arm_gic_common_class_init(ObjectClass *klass, void *data) |
161 | 1e8cae4d | Peter Maydell | { |
162 | 1e8cae4d | Peter Maydell | SysBusDeviceClass *sc = SYS_BUS_DEVICE_CLASS(klass); |
163 | 1e8cae4d | Peter Maydell | DeviceClass *dc = DEVICE_CLASS(klass); |
164 | 1e8cae4d | Peter Maydell | dc->reset = arm_gic_common_reset; |
165 | 1e8cae4d | Peter Maydell | dc->props = arm_gic_common_properties; |
166 | 1e8cae4d | Peter Maydell | dc->no_user = 1;
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167 | 1e8cae4d | Peter Maydell | sc->init = arm_gic_common_init; |
168 | 1e8cae4d | Peter Maydell | } |
169 | 1e8cae4d | Peter Maydell | |
170 | 1e8cae4d | Peter Maydell | static TypeInfo arm_gic_common_type = {
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171 | 1e8cae4d | Peter Maydell | .name = TYPE_ARM_GIC_COMMON, |
172 | 1e8cae4d | Peter Maydell | .parent = TYPE_SYS_BUS_DEVICE, |
173 | 1e8cae4d | Peter Maydell | .instance_size = sizeof(gic_state),
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174 | 1e8cae4d | Peter Maydell | .class_size = sizeof(ARMGICCommonClass),
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175 | 1e8cae4d | Peter Maydell | .class_init = arm_gic_common_class_init, |
176 | 1e8cae4d | Peter Maydell | .abstract = true,
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177 | 1e8cae4d | Peter Maydell | }; |
178 | 1e8cae4d | Peter Maydell | |
179 | 1e8cae4d | Peter Maydell | static void register_types(void) |
180 | 1e8cae4d | Peter Maydell | { |
181 | 1e8cae4d | Peter Maydell | type_register_static(&arm_gic_common_type); |
182 | 1e8cae4d | Peter Maydell | } |
183 | 1e8cae4d | Peter Maydell | |
184 | 1e8cae4d | Peter Maydell | type_init(register_types) |