Revision a1f6684d target-mips/translate.c
b/target-mips/translate.c | ||
---|---|---|
1772 | 1772 |
static void gen_HILO (DisasContext *ctx, uint32_t opc, int reg) |
1773 | 1773 |
{ |
1774 | 1774 |
const char *opn = "hilo"; |
1775 |
TCGv t0 = tcg_temp_local_new(); |
|
1776 | 1775 |
|
1777 | 1776 |
if (reg == 0 && (opc == OPC_MFHI || opc == OPC_MFLO)) { |
1778 | 1777 |
/* Treat as NOP. */ |
1779 | 1778 |
MIPS_DEBUG("NOP"); |
1780 |
goto out;
|
|
1779 |
return;
|
|
1781 | 1780 |
} |
1782 | 1781 |
switch (opc) { |
1783 | 1782 |
case OPC_MFHI: |
1784 |
tcg_gen_mov_tl(t0, cpu_HI[0]); |
|
1785 |
gen_store_gpr(t0, reg); |
|
1783 |
tcg_gen_mov_tl(cpu_gpr[reg], cpu_HI[0]); |
|
1786 | 1784 |
opn = "mfhi"; |
1787 | 1785 |
break; |
1788 | 1786 |
case OPC_MFLO: |
1789 |
tcg_gen_mov_tl(t0, cpu_LO[0]); |
|
1790 |
gen_store_gpr(t0, reg); |
|
1787 |
tcg_gen_mov_tl(cpu_gpr[reg], cpu_LO[0]); |
|
1791 | 1788 |
opn = "mflo"; |
1792 | 1789 |
break; |
1793 | 1790 |
case OPC_MTHI: |
1794 |
gen_load_gpr(t0, reg); |
|
1795 |
tcg_gen_mov_tl(cpu_HI[0], t0); |
|
1791 |
if (reg != 0) |
|
1792 |
tcg_gen_mov_tl(cpu_HI[0], cpu_gpr[reg]); |
|
1793 |
else |
|
1794 |
tcg_gen_movi_tl(cpu_HI[0], 0); |
|
1796 | 1795 |
opn = "mthi"; |
1797 | 1796 |
break; |
1798 | 1797 |
case OPC_MTLO: |
1799 |
gen_load_gpr(t0, reg); |
|
1800 |
tcg_gen_mov_tl(cpu_LO[0], t0); |
|
1798 |
if (reg != 0) |
|
1799 |
tcg_gen_mov_tl(cpu_LO[0], cpu_gpr[reg]); |
|
1800 |
else |
|
1801 |
tcg_gen_movi_tl(cpu_LO[0], 0); |
|
1801 | 1802 |
opn = "mtlo"; |
1802 | 1803 |
break; |
1803 | 1804 |
default: |
1804 | 1805 |
MIPS_INVAL(opn); |
1805 | 1806 |
generate_exception(ctx, EXCP_RI); |
1806 |
goto out;
|
|
1807 |
return;
|
|
1807 | 1808 |
} |
1808 | 1809 |
MIPS_DEBUG("%s %s", opn, regnames[reg]); |
1809 |
out: |
|
1810 |
tcg_temp_free(t0); |
|
1811 | 1810 |
} |
1812 | 1811 |
|
1813 | 1812 |
static void gen_muldiv (DisasContext *ctx, uint32_t opc, |
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