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1 | bb36d470 | bellard | /*
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2 | bb36d470 | bellard | * USB UHCI controller emulation
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3 | 5fafdf24 | ths | *
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4 | bb36d470 | bellard | * Copyright (c) 2005 Fabrice Bellard
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5 | 5fafdf24 | ths | *
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6 | bb36d470 | bellard | * Permission is hereby granted, free of charge, to any person obtaining a copy
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7 | bb36d470 | bellard | * of this software and associated documentation files (the "Software"), to deal
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8 | bb36d470 | bellard | * in the Software without restriction, including without limitation the rights
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9 | bb36d470 | bellard | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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10 | bb36d470 | bellard | * copies of the Software, and to permit persons to whom the Software is
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11 | bb36d470 | bellard | * furnished to do so, subject to the following conditions:
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12 | bb36d470 | bellard | *
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13 | bb36d470 | bellard | * The above copyright notice and this permission notice shall be included in
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14 | bb36d470 | bellard | * all copies or substantial portions of the Software.
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15 | bb36d470 | bellard | *
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16 | bb36d470 | bellard | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 | bb36d470 | bellard | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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18 | bb36d470 | bellard | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 | bb36d470 | bellard | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 | bb36d470 | bellard | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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21 | bb36d470 | bellard | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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22 | bb36d470 | bellard | * THE SOFTWARE.
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23 | bb36d470 | bellard | */
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24 | 87ecb68b | pbrook | #include "hw.h" |
25 | 87ecb68b | pbrook | #include "usb.h" |
26 | 87ecb68b | pbrook | #include "pci.h" |
27 | 87ecb68b | pbrook | #include "qemu-timer.h" |
28 | bb36d470 | bellard | |
29 | bb36d470 | bellard | //#define DEBUG
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30 | bb36d470 | bellard | //#define DEBUG_PACKET
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31 | b9dc033c | balrog | //#define DEBUG_ISOCH
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32 | bb36d470 | bellard | |
33 | 96217e31 | ths | #define UHCI_CMD_FGR (1 << 4) |
34 | 96217e31 | ths | #define UHCI_CMD_EGSM (1 << 3) |
35 | bb36d470 | bellard | #define UHCI_CMD_GRESET (1 << 2) |
36 | bb36d470 | bellard | #define UHCI_CMD_HCRESET (1 << 1) |
37 | bb36d470 | bellard | #define UHCI_CMD_RS (1 << 0) |
38 | bb36d470 | bellard | |
39 | bb36d470 | bellard | #define UHCI_STS_HCHALTED (1 << 5) |
40 | bb36d470 | bellard | #define UHCI_STS_HCPERR (1 << 4) |
41 | bb36d470 | bellard | #define UHCI_STS_HSERR (1 << 3) |
42 | bb36d470 | bellard | #define UHCI_STS_RD (1 << 2) |
43 | bb36d470 | bellard | #define UHCI_STS_USBERR (1 << 1) |
44 | bb36d470 | bellard | #define UHCI_STS_USBINT (1 << 0) |
45 | bb36d470 | bellard | |
46 | bb36d470 | bellard | #define TD_CTRL_SPD (1 << 29) |
47 | bb36d470 | bellard | #define TD_CTRL_ERROR_SHIFT 27 |
48 | bb36d470 | bellard | #define TD_CTRL_IOS (1 << 25) |
49 | bb36d470 | bellard | #define TD_CTRL_IOC (1 << 24) |
50 | bb36d470 | bellard | #define TD_CTRL_ACTIVE (1 << 23) |
51 | bb36d470 | bellard | #define TD_CTRL_STALL (1 << 22) |
52 | bb36d470 | bellard | #define TD_CTRL_BABBLE (1 << 20) |
53 | bb36d470 | bellard | #define TD_CTRL_NAK (1 << 19) |
54 | bb36d470 | bellard | #define TD_CTRL_TIMEOUT (1 << 18) |
55 | bb36d470 | bellard | |
56 | bb36d470 | bellard | #define UHCI_PORT_RESET (1 << 9) |
57 | bb36d470 | bellard | #define UHCI_PORT_LSDA (1 << 8) |
58 | bb36d470 | bellard | #define UHCI_PORT_ENC (1 << 3) |
59 | bb36d470 | bellard | #define UHCI_PORT_EN (1 << 2) |
60 | bb36d470 | bellard | #define UHCI_PORT_CSC (1 << 1) |
61 | bb36d470 | bellard | #define UHCI_PORT_CCS (1 << 0) |
62 | bb36d470 | bellard | |
63 | bb36d470 | bellard | #define FRAME_TIMER_FREQ 1000 |
64 | bb36d470 | bellard | |
65 | bb36d470 | bellard | #define FRAME_MAX_LOOPS 100 |
66 | bb36d470 | bellard | |
67 | bb36d470 | bellard | #define NB_PORTS 2 |
68 | bb36d470 | bellard | |
69 | bb36d470 | bellard | typedef struct UHCIPort { |
70 | bb36d470 | bellard | USBPort port; |
71 | bb36d470 | bellard | uint16_t ctrl; |
72 | bb36d470 | bellard | } UHCIPort; |
73 | bb36d470 | bellard | |
74 | bb36d470 | bellard | typedef struct UHCIState { |
75 | bb36d470 | bellard | PCIDevice dev; |
76 | bb36d470 | bellard | uint16_t cmd; /* cmd register */
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77 | bb36d470 | bellard | uint16_t status; |
78 | bb36d470 | bellard | uint16_t intr; /* interrupt enable register */
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79 | bb36d470 | bellard | uint16_t frnum; /* frame number */
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80 | bb36d470 | bellard | uint32_t fl_base_addr; /* frame list base address */
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81 | bb36d470 | bellard | uint8_t sof_timing; |
82 | bb36d470 | bellard | uint8_t status2; /* bit 0 and 1 are used to generate UHCI_STS_USBINT */
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83 | bb36d470 | bellard | QEMUTimer *frame_timer; |
84 | bb36d470 | bellard | UHCIPort ports[NB_PORTS]; |
85 | 4d611c9a | pbrook | |
86 | 4d611c9a | pbrook | /* Interrupts that should be raised at the end of the current frame. */
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87 | 4d611c9a | pbrook | uint32_t pending_int_mask; |
88 | 4d611c9a | pbrook | /* For simplicity of implementation we only allow a single pending USB
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89 | 4d611c9a | pbrook | request. This means all usb traffic on this controller is effectively
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90 | 4d611c9a | pbrook | suspended until that transfer completes. When the transfer completes
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91 | 5fafdf24 | ths | the next transfer from that queue will be processed. However
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92 | 4d611c9a | pbrook | other queues will not be processed until the next frame. The solution
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93 | 4d611c9a | pbrook | is to allow multiple pending requests. */
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94 | 4d611c9a | pbrook | uint32_t async_qh; |
95 | b9dc033c | balrog | uint32_t async_frame_addr; |
96 | 4d611c9a | pbrook | USBPacket usb_packet; |
97 | 81822663 | ths | uint8_t usb_buf[2048];
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98 | bb36d470 | bellard | } UHCIState; |
99 | bb36d470 | bellard | |
100 | bb36d470 | bellard | typedef struct UHCI_TD { |
101 | bb36d470 | bellard | uint32_t link; |
102 | bb36d470 | bellard | uint32_t ctrl; /* see TD_CTRL_xxx */
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103 | bb36d470 | bellard | uint32_t token; |
104 | bb36d470 | bellard | uint32_t buffer; |
105 | bb36d470 | bellard | } UHCI_TD; |
106 | bb36d470 | bellard | |
107 | bb36d470 | bellard | typedef struct UHCI_QH { |
108 | bb36d470 | bellard | uint32_t link; |
109 | bb36d470 | bellard | uint32_t el_link; |
110 | bb36d470 | bellard | } UHCI_QH; |
111 | bb36d470 | bellard | |
112 | bb36d470 | bellard | static void uhci_attach(USBPort *port1, USBDevice *dev); |
113 | bb36d470 | bellard | |
114 | bb36d470 | bellard | static void uhci_update_irq(UHCIState *s) |
115 | bb36d470 | bellard | { |
116 | bb36d470 | bellard | int level;
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117 | bb36d470 | bellard | if (((s->status2 & 1) && (s->intr & (1 << 2))) || |
118 | bb36d470 | bellard | ((s->status2 & 2) && (s->intr & (1 << 3))) || |
119 | bb36d470 | bellard | ((s->status & UHCI_STS_USBERR) && (s->intr & (1 << 0))) || |
120 | bb36d470 | bellard | ((s->status & UHCI_STS_RD) && (s->intr & (1 << 1))) || |
121 | bb36d470 | bellard | (s->status & UHCI_STS_HSERR) || |
122 | bb36d470 | bellard | (s->status & UHCI_STS_HCPERR)) { |
123 | bb36d470 | bellard | level = 1;
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124 | bb36d470 | bellard | } else {
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125 | bb36d470 | bellard | level = 0;
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126 | bb36d470 | bellard | } |
127 | d537cf6c | pbrook | qemu_set_irq(s->dev.irq[3], level);
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128 | bb36d470 | bellard | } |
129 | bb36d470 | bellard | |
130 | bb36d470 | bellard | static void uhci_reset(UHCIState *s) |
131 | bb36d470 | bellard | { |
132 | bb36d470 | bellard | uint8_t *pci_conf; |
133 | bb36d470 | bellard | int i;
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134 | bb36d470 | bellard | UHCIPort *port; |
135 | bb36d470 | bellard | |
136 | bb36d470 | bellard | pci_conf = s->dev.config; |
137 | bb36d470 | bellard | |
138 | bb36d470 | bellard | pci_conf[0x6a] = 0x01; /* usb clock */ |
139 | bb36d470 | bellard | pci_conf[0x6b] = 0x00; |
140 | bb36d470 | bellard | s->cmd = 0;
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141 | bb36d470 | bellard | s->status = 0;
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142 | bb36d470 | bellard | s->status2 = 0;
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143 | bb36d470 | bellard | s->intr = 0;
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144 | bb36d470 | bellard | s->fl_base_addr = 0;
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145 | bb36d470 | bellard | s->sof_timing = 64;
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146 | bb36d470 | bellard | for(i = 0; i < NB_PORTS; i++) { |
147 | bb36d470 | bellard | port = &s->ports[i]; |
148 | bb36d470 | bellard | port->ctrl = 0x0080;
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149 | a594cfbf | bellard | if (port->port.dev)
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150 | a594cfbf | bellard | uhci_attach(&port->port, port->port.dev); |
151 | bb36d470 | bellard | } |
152 | bb36d470 | bellard | } |
153 | bb36d470 | bellard | |
154 | 1e414679 | bellard | #if 0
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155 | b9dc033c | balrog | static void uhci_save(QEMUFile *f, void *opaque)
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156 | b9dc033c | balrog | {
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157 | b9dc033c | balrog | UHCIState *s = opaque;
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158 | b9dc033c | balrog | uint8_t num_ports = NB_PORTS;
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159 | b9dc033c | balrog | int i;
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160 | b9dc033c | balrog | |
161 | b9dc033c | balrog | pci_device_save(&s->dev, f);
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162 | b9dc033c | balrog | |
163 | b9dc033c | balrog | qemu_put_8s(f, &num_ports);
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164 | b9dc033c | balrog | for (i = 0; i < num_ports; ++i)
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165 | b9dc033c | balrog | qemu_put_be16s(f, &s->ports[i].ctrl);
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166 | b9dc033c | balrog | qemu_put_be16s(f, &s->cmd);
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167 | b9dc033c | balrog | qemu_put_be16s(f, &s->status);
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168 | b9dc033c | balrog | qemu_put_be16s(f, &s->intr);
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169 | b9dc033c | balrog | qemu_put_be16s(f, &s->frnum);
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170 | b9dc033c | balrog | qemu_put_be32s(f, &s->fl_base_addr);
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171 | b9dc033c | balrog | qemu_put_8s(f, &s->sof_timing);
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172 | b9dc033c | balrog | qemu_put_8s(f, &s->status2);
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173 | b9dc033c | balrog | qemu_put_timer(f, s->frame_timer);
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174 | b9dc033c | balrog | }
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175 | b9dc033c | balrog | |
176 | b9dc033c | balrog | static int uhci_load(QEMUFile *f, void *opaque, int version_id)
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177 | b9dc033c | balrog | {
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178 | b9dc033c | balrog | UHCIState *s = opaque;
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179 | b9dc033c | balrog | uint8_t num_ports;
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180 | b9dc033c | balrog | int i, ret;
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181 | b9dc033c | balrog | |
182 | b9dc033c | balrog | if (version_id > 1)
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183 | b9dc033c | balrog | return -EINVAL;
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184 | b9dc033c | balrog | |
185 | b9dc033c | balrog | ret = pci_device_load(&s->dev, f);
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186 | b9dc033c | balrog | if (ret < 0)
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187 | b9dc033c | balrog | return ret;
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188 | b9dc033c | balrog | |
189 | b9dc033c | balrog | qemu_get_8s(f, &num_ports);
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190 | b9dc033c | balrog | if (num_ports != NB_PORTS)
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191 | b9dc033c | balrog | return -EINVAL;
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192 | b9dc033c | balrog | |
193 | b9dc033c | balrog | for (i = 0; i < num_ports; ++i)
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194 | b9dc033c | balrog | qemu_get_be16s(f, &s->ports[i].ctrl);
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195 | b9dc033c | balrog | qemu_get_be16s(f, &s->cmd);
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196 | b9dc033c | balrog | qemu_get_be16s(f, &s->status);
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197 | b9dc033c | balrog | qemu_get_be16s(f, &s->intr);
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198 | b9dc033c | balrog | qemu_get_be16s(f, &s->frnum);
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199 | b9dc033c | balrog | qemu_get_be32s(f, &s->fl_base_addr);
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200 | b9dc033c | balrog | qemu_get_8s(f, &s->sof_timing);
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201 | b9dc033c | balrog | qemu_get_8s(f, &s->status2);
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202 | b9dc033c | balrog | qemu_get_timer(f, s->frame_timer);
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203 | b9dc033c | balrog | |
204 | b9dc033c | balrog | return 0;
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205 | b9dc033c | balrog | }
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206 | 1e414679 | bellard | #endif
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207 | b9dc033c | balrog | |
208 | bb36d470 | bellard | static void uhci_ioport_writeb(void *opaque, uint32_t addr, uint32_t val) |
209 | bb36d470 | bellard | { |
210 | bb36d470 | bellard | UHCIState *s = opaque; |
211 | 3b46e624 | ths | |
212 | bb36d470 | bellard | addr &= 0x1f;
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213 | bb36d470 | bellard | switch(addr) {
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214 | bb36d470 | bellard | case 0x0c: |
215 | bb36d470 | bellard | s->sof_timing = val; |
216 | bb36d470 | bellard | break;
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217 | bb36d470 | bellard | } |
218 | bb36d470 | bellard | } |
219 | bb36d470 | bellard | |
220 | bb36d470 | bellard | static uint32_t uhci_ioport_readb(void *opaque, uint32_t addr) |
221 | bb36d470 | bellard | { |
222 | bb36d470 | bellard | UHCIState *s = opaque; |
223 | bb36d470 | bellard | uint32_t val; |
224 | bb36d470 | bellard | |
225 | bb36d470 | bellard | addr &= 0x1f;
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226 | bb36d470 | bellard | switch(addr) {
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227 | bb36d470 | bellard | case 0x0c: |
228 | bb36d470 | bellard | val = s->sof_timing; |
229 | d80cfb3f | pbrook | break;
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230 | bb36d470 | bellard | default:
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231 | bb36d470 | bellard | val = 0xff;
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232 | bb36d470 | bellard | break;
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233 | bb36d470 | bellard | } |
234 | bb36d470 | bellard | return val;
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235 | bb36d470 | bellard | } |
236 | bb36d470 | bellard | |
237 | bb36d470 | bellard | static void uhci_ioport_writew(void *opaque, uint32_t addr, uint32_t val) |
238 | bb36d470 | bellard | { |
239 | bb36d470 | bellard | UHCIState *s = opaque; |
240 | 3b46e624 | ths | |
241 | bb36d470 | bellard | addr &= 0x1f;
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242 | bb36d470 | bellard | #ifdef DEBUG
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243 | bb36d470 | bellard | printf("uhci writew port=0x%04x val=0x%04x\n", addr, val);
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244 | bb36d470 | bellard | #endif
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245 | bb36d470 | bellard | switch(addr) {
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246 | bb36d470 | bellard | case 0x00: |
247 | bb36d470 | bellard | if ((val & UHCI_CMD_RS) && !(s->cmd & UHCI_CMD_RS)) {
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248 | bb36d470 | bellard | /* start frame processing */
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249 | bb36d470 | bellard | qemu_mod_timer(s->frame_timer, qemu_get_clock(vm_clock)); |
250 | 52328140 | bellard | s->status &= ~UHCI_STS_HCHALTED; |
251 | 467d409f | bellard | } else if (!(val & UHCI_CMD_RS)) { |
252 | 52328140 | bellard | s->status |= UHCI_STS_HCHALTED; |
253 | bb36d470 | bellard | } |
254 | bb36d470 | bellard | if (val & UHCI_CMD_GRESET) {
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255 | bb36d470 | bellard | UHCIPort *port; |
256 | bb36d470 | bellard | USBDevice *dev; |
257 | bb36d470 | bellard | int i;
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258 | bb36d470 | bellard | |
259 | bb36d470 | bellard | /* send reset on the USB bus */
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260 | bb36d470 | bellard | for(i = 0; i < NB_PORTS; i++) { |
261 | bb36d470 | bellard | port = &s->ports[i]; |
262 | a594cfbf | bellard | dev = port->port.dev; |
263 | bb36d470 | bellard | if (dev) {
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264 | 4d611c9a | pbrook | usb_send_msg(dev, USB_MSG_RESET); |
265 | bb36d470 | bellard | } |
266 | bb36d470 | bellard | } |
267 | bb36d470 | bellard | uhci_reset(s); |
268 | bb36d470 | bellard | return;
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269 | bb36d470 | bellard | } |
270 | 5e9ab4c4 | bellard | if (val & UHCI_CMD_HCRESET) {
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271 | bb36d470 | bellard | uhci_reset(s); |
272 | bb36d470 | bellard | return;
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273 | bb36d470 | bellard | } |
274 | bb36d470 | bellard | s->cmd = val; |
275 | bb36d470 | bellard | break;
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276 | bb36d470 | bellard | case 0x02: |
277 | bb36d470 | bellard | s->status &= ~val; |
278 | bb36d470 | bellard | /* XXX: the chip spec is not coherent, so we add a hidden
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279 | bb36d470 | bellard | register to distinguish between IOC and SPD */
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280 | bb36d470 | bellard | if (val & UHCI_STS_USBINT)
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281 | bb36d470 | bellard | s->status2 = 0;
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282 | bb36d470 | bellard | uhci_update_irq(s); |
283 | bb36d470 | bellard | break;
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284 | bb36d470 | bellard | case 0x04: |
285 | bb36d470 | bellard | s->intr = val; |
286 | bb36d470 | bellard | uhci_update_irq(s); |
287 | bb36d470 | bellard | break;
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288 | bb36d470 | bellard | case 0x06: |
289 | bb36d470 | bellard | if (s->status & UHCI_STS_HCHALTED)
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290 | bb36d470 | bellard | s->frnum = val & 0x7ff;
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291 | bb36d470 | bellard | break;
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292 | bb36d470 | bellard | case 0x10 ... 0x1f: |
293 | bb36d470 | bellard | { |
294 | bb36d470 | bellard | UHCIPort *port; |
295 | bb36d470 | bellard | USBDevice *dev; |
296 | bb36d470 | bellard | int n;
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297 | bb36d470 | bellard | |
298 | bb36d470 | bellard | n = (addr >> 1) & 7; |
299 | bb36d470 | bellard | if (n >= NB_PORTS)
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300 | bb36d470 | bellard | return;
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301 | bb36d470 | bellard | port = &s->ports[n]; |
302 | a594cfbf | bellard | dev = port->port.dev; |
303 | bb36d470 | bellard | if (dev) {
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304 | bb36d470 | bellard | /* port reset */
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305 | 5fafdf24 | ths | if ( (val & UHCI_PORT_RESET) &&
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306 | bb36d470 | bellard | !(port->ctrl & UHCI_PORT_RESET) ) { |
307 | 4d611c9a | pbrook | usb_send_msg(dev, USB_MSG_RESET); |
308 | bb36d470 | bellard | } |
309 | bb36d470 | bellard | } |
310 | bb36d470 | bellard | port->ctrl = (port->ctrl & 0x01fb) | (val & ~0x01fb); |
311 | bb36d470 | bellard | /* some bits are reset when a '1' is written to them */
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312 | bb36d470 | bellard | port->ctrl &= ~(val & 0x000a);
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313 | bb36d470 | bellard | } |
314 | bb36d470 | bellard | break;
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315 | bb36d470 | bellard | } |
316 | bb36d470 | bellard | } |
317 | bb36d470 | bellard | |
318 | bb36d470 | bellard | static uint32_t uhci_ioport_readw(void *opaque, uint32_t addr) |
319 | bb36d470 | bellard | { |
320 | bb36d470 | bellard | UHCIState *s = opaque; |
321 | bb36d470 | bellard | uint32_t val; |
322 | bb36d470 | bellard | |
323 | bb36d470 | bellard | addr &= 0x1f;
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324 | bb36d470 | bellard | switch(addr) {
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325 | bb36d470 | bellard | case 0x00: |
326 | bb36d470 | bellard | val = s->cmd; |
327 | bb36d470 | bellard | break;
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328 | bb36d470 | bellard | case 0x02: |
329 | bb36d470 | bellard | val = s->status; |
330 | bb36d470 | bellard | break;
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331 | bb36d470 | bellard | case 0x04: |
332 | bb36d470 | bellard | val = s->intr; |
333 | bb36d470 | bellard | break;
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334 | bb36d470 | bellard | case 0x06: |
335 | bb36d470 | bellard | val = s->frnum; |
336 | bb36d470 | bellard | break;
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337 | bb36d470 | bellard | case 0x10 ... 0x1f: |
338 | bb36d470 | bellard | { |
339 | bb36d470 | bellard | UHCIPort *port; |
340 | bb36d470 | bellard | int n;
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341 | bb36d470 | bellard | n = (addr >> 1) & 7; |
342 | 5fafdf24 | ths | if (n >= NB_PORTS)
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343 | bb36d470 | bellard | goto read_default;
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344 | bb36d470 | bellard | port = &s->ports[n]; |
345 | bb36d470 | bellard | val = port->ctrl; |
346 | bb36d470 | bellard | } |
347 | bb36d470 | bellard | break;
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348 | bb36d470 | bellard | default:
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349 | bb36d470 | bellard | read_default:
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350 | bb36d470 | bellard | val = 0xff7f; /* disabled port */ |
351 | bb36d470 | bellard | break;
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352 | bb36d470 | bellard | } |
353 | bb36d470 | bellard | #ifdef DEBUG
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354 | bb36d470 | bellard | printf("uhci readw port=0x%04x val=0x%04x\n", addr, val);
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355 | bb36d470 | bellard | #endif
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356 | bb36d470 | bellard | return val;
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357 | bb36d470 | bellard | } |
358 | bb36d470 | bellard | |
359 | bb36d470 | bellard | static void uhci_ioport_writel(void *opaque, uint32_t addr, uint32_t val) |
360 | bb36d470 | bellard | { |
361 | bb36d470 | bellard | UHCIState *s = opaque; |
362 | bb36d470 | bellard | |
363 | bb36d470 | bellard | addr &= 0x1f;
|
364 | bb36d470 | bellard | #ifdef DEBUG
|
365 | bb36d470 | bellard | printf("uhci writel port=0x%04x val=0x%08x\n", addr, val);
|
366 | bb36d470 | bellard | #endif
|
367 | bb36d470 | bellard | switch(addr) {
|
368 | bb36d470 | bellard | case 0x08: |
369 | bb36d470 | bellard | s->fl_base_addr = val & ~0xfff;
|
370 | bb36d470 | bellard | break;
|
371 | bb36d470 | bellard | } |
372 | bb36d470 | bellard | } |
373 | bb36d470 | bellard | |
374 | bb36d470 | bellard | static uint32_t uhci_ioport_readl(void *opaque, uint32_t addr) |
375 | bb36d470 | bellard | { |
376 | bb36d470 | bellard | UHCIState *s = opaque; |
377 | bb36d470 | bellard | uint32_t val; |
378 | bb36d470 | bellard | |
379 | bb36d470 | bellard | addr &= 0x1f;
|
380 | bb36d470 | bellard | switch(addr) {
|
381 | bb36d470 | bellard | case 0x08: |
382 | bb36d470 | bellard | val = s->fl_base_addr; |
383 | bb36d470 | bellard | break;
|
384 | bb36d470 | bellard | default:
|
385 | bb36d470 | bellard | val = 0xffffffff;
|
386 | bb36d470 | bellard | break;
|
387 | bb36d470 | bellard | } |
388 | bb36d470 | bellard | return val;
|
389 | bb36d470 | bellard | } |
390 | bb36d470 | bellard | |
391 | 96217e31 | ths | /* signal resume if controller suspended */
|
392 | 96217e31 | ths | static void uhci_resume (void *opaque) |
393 | 96217e31 | ths | { |
394 | 96217e31 | ths | UHCIState *s = (UHCIState *)opaque; |
395 | 96217e31 | ths | |
396 | 96217e31 | ths | if (!s)
|
397 | 96217e31 | ths | return;
|
398 | 96217e31 | ths | |
399 | 96217e31 | ths | if (s->cmd & UHCI_CMD_EGSM) {
|
400 | 96217e31 | ths | s->cmd |= UHCI_CMD_FGR; |
401 | 96217e31 | ths | s->status |= UHCI_STS_RD; |
402 | 96217e31 | ths | uhci_update_irq(s); |
403 | 96217e31 | ths | } |
404 | 96217e31 | ths | } |
405 | 96217e31 | ths | |
406 | bb36d470 | bellard | static void uhci_attach(USBPort *port1, USBDevice *dev) |
407 | bb36d470 | bellard | { |
408 | bb36d470 | bellard | UHCIState *s = port1->opaque; |
409 | bb36d470 | bellard | UHCIPort *port = &s->ports[port1->index]; |
410 | bb36d470 | bellard | |
411 | bb36d470 | bellard | if (dev) {
|
412 | a594cfbf | bellard | if (port->port.dev) {
|
413 | bb36d470 | bellard | usb_attach(port1, NULL);
|
414 | bb36d470 | bellard | } |
415 | bb36d470 | bellard | /* set connect status */
|
416 | 61064870 | pbrook | port->ctrl |= UHCI_PORT_CCS | UHCI_PORT_CSC; |
417 | 61064870 | pbrook | |
418 | bb36d470 | bellard | /* update speed */
|
419 | bb36d470 | bellard | if (dev->speed == USB_SPEED_LOW)
|
420 | bb36d470 | bellard | port->ctrl |= UHCI_PORT_LSDA; |
421 | bb36d470 | bellard | else
|
422 | bb36d470 | bellard | port->ctrl &= ~UHCI_PORT_LSDA; |
423 | 96217e31 | ths | |
424 | 96217e31 | ths | uhci_resume(s); |
425 | 96217e31 | ths | |
426 | a594cfbf | bellard | port->port.dev = dev; |
427 | bb36d470 | bellard | /* send the attach message */
|
428 | 4d611c9a | pbrook | usb_send_msg(dev, USB_MSG_ATTACH); |
429 | bb36d470 | bellard | } else {
|
430 | bb36d470 | bellard | /* set connect status */
|
431 | 61064870 | pbrook | if (port->ctrl & UHCI_PORT_CCS) {
|
432 | 61064870 | pbrook | port->ctrl &= ~UHCI_PORT_CCS; |
433 | 61064870 | pbrook | port->ctrl |= UHCI_PORT_CSC; |
434 | bb36d470 | bellard | } |
435 | bb36d470 | bellard | /* disable port */
|
436 | bb36d470 | bellard | if (port->ctrl & UHCI_PORT_EN) {
|
437 | bb36d470 | bellard | port->ctrl &= ~UHCI_PORT_EN; |
438 | bb36d470 | bellard | port->ctrl |= UHCI_PORT_ENC; |
439 | bb36d470 | bellard | } |
440 | 96217e31 | ths | |
441 | 96217e31 | ths | uhci_resume(s); |
442 | 96217e31 | ths | |
443 | a594cfbf | bellard | dev = port->port.dev; |
444 | bb36d470 | bellard | if (dev) {
|
445 | bb36d470 | bellard | /* send the detach message */
|
446 | 4d611c9a | pbrook | usb_send_msg(dev, USB_MSG_DETACH); |
447 | bb36d470 | bellard | } |
448 | a594cfbf | bellard | port->port.dev = NULL;
|
449 | bb36d470 | bellard | } |
450 | bb36d470 | bellard | } |
451 | bb36d470 | bellard | |
452 | 4d611c9a | pbrook | static int uhci_broadcast_packet(UHCIState *s, USBPacket *p) |
453 | bb36d470 | bellard | { |
454 | bb36d470 | bellard | UHCIPort *port; |
455 | bb36d470 | bellard | USBDevice *dev; |
456 | bb36d470 | bellard | int i, ret;
|
457 | bb36d470 | bellard | |
458 | bb36d470 | bellard | #ifdef DEBUG_PACKET
|
459 | bb36d470 | bellard | { |
460 | bb36d470 | bellard | const char *pidstr; |
461 | 4d611c9a | pbrook | switch(p->pid) {
|
462 | bb36d470 | bellard | case USB_TOKEN_SETUP: pidstr = "SETUP"; break; |
463 | bb36d470 | bellard | case USB_TOKEN_IN: pidstr = "IN"; break; |
464 | bb36d470 | bellard | case USB_TOKEN_OUT: pidstr = "OUT"; break; |
465 | bb36d470 | bellard | default: pidstr = "?"; break; |
466 | bb36d470 | bellard | } |
467 | bb36d470 | bellard | printf("frame %d: pid=%s addr=0x%02x ep=%d len=%d\n",
|
468 | 4d611c9a | pbrook | s->frnum, pidstr, p->devaddr, p->devep, p->len); |
469 | 4d611c9a | pbrook | if (p->pid != USB_TOKEN_IN) {
|
470 | bb36d470 | bellard | printf(" data_out=");
|
471 | 4d611c9a | pbrook | for(i = 0; i < p->len; i++) { |
472 | 4d611c9a | pbrook | printf(" %02x", p->data[i]);
|
473 | bb36d470 | bellard | } |
474 | bb36d470 | bellard | printf("\n");
|
475 | bb36d470 | bellard | } |
476 | bb36d470 | bellard | } |
477 | bb36d470 | bellard | #endif
|
478 | bb36d470 | bellard | for(i = 0; i < NB_PORTS; i++) { |
479 | bb36d470 | bellard | port = &s->ports[i]; |
480 | a594cfbf | bellard | dev = port->port.dev; |
481 | bb36d470 | bellard | if (dev && (port->ctrl & UHCI_PORT_EN)) {
|
482 | 4d611c9a | pbrook | ret = dev->handle_packet(dev, p); |
483 | bb36d470 | bellard | if (ret != USB_RET_NODEV) {
|
484 | bb36d470 | bellard | #ifdef DEBUG_PACKET
|
485 | 4d611c9a | pbrook | if (ret == USB_RET_ASYNC) {
|
486 | 4d611c9a | pbrook | printf("usb-uhci: Async packet\n");
|
487 | 4d611c9a | pbrook | } else {
|
488 | bb36d470 | bellard | printf(" ret=%d ", ret);
|
489 | 4d611c9a | pbrook | if (p->pid == USB_TOKEN_IN && ret > 0) { |
490 | bb36d470 | bellard | printf("data_in=");
|
491 | bb36d470 | bellard | for(i = 0; i < ret; i++) { |
492 | 4d611c9a | pbrook | printf(" %02x", p->data[i]);
|
493 | bb36d470 | bellard | } |
494 | bb36d470 | bellard | } |
495 | bb36d470 | bellard | printf("\n");
|
496 | bb36d470 | bellard | } |
497 | bb36d470 | bellard | #endif
|
498 | bb36d470 | bellard | return ret;
|
499 | bb36d470 | bellard | } |
500 | bb36d470 | bellard | } |
501 | bb36d470 | bellard | } |
502 | bb36d470 | bellard | return USB_RET_NODEV;
|
503 | bb36d470 | bellard | } |
504 | bb36d470 | bellard | |
505 | 4d611c9a | pbrook | static void uhci_async_complete_packet(USBPacket * packet, void *opaque); |
506 | 4d611c9a | pbrook | |
507 | bb36d470 | bellard | /* return -1 if fatal error (frame must be stopped)
|
508 | bb36d470 | bellard | 0 if TD successful
|
509 | bb36d470 | bellard | 1 if TD unsuccessful or inactive
|
510 | bb36d470 | bellard | */
|
511 | 60fe76f3 | ths | static int uhci_handle_td(UHCIState *s, UHCI_TD *td, uint32_t *int_mask, |
512 | b9dc033c | balrog | int completion)
|
513 | bb36d470 | bellard | { |
514 | bb36d470 | bellard | uint8_t pid; |
515 | b9dc033c | balrog | int len = 0, max_len, err, ret = 0; |
516 | bb36d470 | bellard | |
517 | 4d611c9a | pbrook | /* ??? This is wrong for async completion. */
|
518 | bb36d470 | bellard | if (td->ctrl & TD_CTRL_IOC) {
|
519 | bb36d470 | bellard | *int_mask |= 0x01;
|
520 | bb36d470 | bellard | } |
521 | 3b46e624 | ths | |
522 | bb36d470 | bellard | if (!(td->ctrl & TD_CTRL_ACTIVE))
|
523 | bb36d470 | bellard | return 1; |
524 | bb36d470 | bellard | |
525 | bb36d470 | bellard | /* TD is active */
|
526 | bb36d470 | bellard | max_len = ((td->token >> 21) + 1) & 0x7ff; |
527 | bb36d470 | bellard | pid = td->token & 0xff;
|
528 | b9dc033c | balrog | |
529 | b9dc033c | balrog | if (completion && (s->async_qh || s->async_frame_addr)) {
|
530 | 4d611c9a | pbrook | ret = s->usb_packet.len; |
531 | bb36d470 | bellard | if (ret >= 0) { |
532 | bb36d470 | bellard | len = ret; |
533 | bb36d470 | bellard | if (len > max_len) {
|
534 | bb36d470 | bellard | len = max_len; |
535 | bb36d470 | bellard | ret = USB_RET_BABBLE; |
536 | bb36d470 | bellard | } |
537 | bb36d470 | bellard | if (len > 0) { |
538 | bb36d470 | bellard | /* write the data back */
|
539 | 4d611c9a | pbrook | cpu_physical_memory_write(td->buffer, s->usb_buf, len); |
540 | bb36d470 | bellard | } |
541 | bb36d470 | bellard | } else {
|
542 | bb36d470 | bellard | len = 0;
|
543 | bb36d470 | bellard | } |
544 | 4d611c9a | pbrook | s->async_qh = 0;
|
545 | b9dc033c | balrog | s->async_frame_addr = 0;
|
546 | b9dc033c | balrog | } else if (!completion) { |
547 | 4d611c9a | pbrook | s->usb_packet.pid = pid; |
548 | 4d611c9a | pbrook | s->usb_packet.devaddr = (td->token >> 8) & 0x7f; |
549 | 4d611c9a | pbrook | s->usb_packet.devep = (td->token >> 15) & 0xf; |
550 | 4d611c9a | pbrook | s->usb_packet.data = s->usb_buf; |
551 | 4d611c9a | pbrook | s->usb_packet.len = max_len; |
552 | 4d611c9a | pbrook | s->usb_packet.complete_cb = uhci_async_complete_packet; |
553 | 4d611c9a | pbrook | s->usb_packet.complete_opaque = s; |
554 | 4d611c9a | pbrook | switch(pid) {
|
555 | 4d611c9a | pbrook | case USB_TOKEN_OUT:
|
556 | 4d611c9a | pbrook | case USB_TOKEN_SETUP:
|
557 | 4d611c9a | pbrook | cpu_physical_memory_read(td->buffer, s->usb_buf, max_len); |
558 | 4d611c9a | pbrook | ret = uhci_broadcast_packet(s, &s->usb_packet); |
559 | 4d611c9a | pbrook | len = max_len; |
560 | 4d611c9a | pbrook | break;
|
561 | 4d611c9a | pbrook | case USB_TOKEN_IN:
|
562 | 4d611c9a | pbrook | ret = uhci_broadcast_packet(s, &s->usb_packet); |
563 | 4d611c9a | pbrook | if (ret >= 0) { |
564 | 4d611c9a | pbrook | len = ret; |
565 | 4d611c9a | pbrook | if (len > max_len) {
|
566 | 4d611c9a | pbrook | len = max_len; |
567 | 4d611c9a | pbrook | ret = USB_RET_BABBLE; |
568 | 4d611c9a | pbrook | } |
569 | 4d611c9a | pbrook | if (len > 0) { |
570 | 4d611c9a | pbrook | /* write the data back */
|
571 | 4d611c9a | pbrook | cpu_physical_memory_write(td->buffer, s->usb_buf, len); |
572 | 4d611c9a | pbrook | } |
573 | 4d611c9a | pbrook | } else {
|
574 | 4d611c9a | pbrook | len = 0;
|
575 | 4d611c9a | pbrook | } |
576 | 4d611c9a | pbrook | break;
|
577 | 4d611c9a | pbrook | default:
|
578 | 4d611c9a | pbrook | /* invalid pid : frame interrupted */
|
579 | 4d611c9a | pbrook | s->status |= UHCI_STS_HCPERR; |
580 | 4d611c9a | pbrook | uhci_update_irq(s); |
581 | 4d611c9a | pbrook | return -1; |
582 | 4d611c9a | pbrook | } |
583 | 4d611c9a | pbrook | } |
584 | b9dc033c | balrog | |
585 | 4d611c9a | pbrook | if (ret == USB_RET_ASYNC) {
|
586 | 4d611c9a | pbrook | return 2; |
587 | bb36d470 | bellard | } |
588 | bb36d470 | bellard | if (td->ctrl & TD_CTRL_IOS)
|
589 | bb36d470 | bellard | td->ctrl &= ~TD_CTRL_ACTIVE; |
590 | bb36d470 | bellard | if (ret >= 0) { |
591 | bb36d470 | bellard | td->ctrl = (td->ctrl & ~0x7ff) | ((len - 1) & 0x7ff); |
592 | 117b3ae6 | pbrook | /* The NAK bit may have been set by a previous frame, so clear it
|
593 | 117b3ae6 | pbrook | here. The docs are somewhat unclear, but win2k relies on this
|
594 | 117b3ae6 | pbrook | behavior. */
|
595 | 117b3ae6 | pbrook | td->ctrl &= ~(TD_CTRL_ACTIVE | TD_CTRL_NAK); |
596 | 5fafdf24 | ths | if (pid == USB_TOKEN_IN &&
|
597 | bb36d470 | bellard | (td->ctrl & TD_CTRL_SPD) && |
598 | bb36d470 | bellard | len < max_len) { |
599 | bb36d470 | bellard | *int_mask |= 0x02;
|
600 | bb36d470 | bellard | /* short packet: do not update QH */
|
601 | bb36d470 | bellard | return 1; |
602 | bb36d470 | bellard | } else {
|
603 | bb36d470 | bellard | /* success */
|
604 | bb36d470 | bellard | return 0; |
605 | bb36d470 | bellard | } |
606 | bb36d470 | bellard | } else {
|
607 | bb36d470 | bellard | switch(ret) {
|
608 | bb36d470 | bellard | default:
|
609 | bb36d470 | bellard | case USB_RET_NODEV:
|
610 | bb36d470 | bellard | do_timeout:
|
611 | bb36d470 | bellard | td->ctrl |= TD_CTRL_TIMEOUT; |
612 | bb36d470 | bellard | err = (td->ctrl >> TD_CTRL_ERROR_SHIFT) & 3;
|
613 | bb36d470 | bellard | if (err != 0) { |
614 | bb36d470 | bellard | err--; |
615 | bb36d470 | bellard | if (err == 0) { |
616 | bb36d470 | bellard | td->ctrl &= ~TD_CTRL_ACTIVE; |
617 | bb36d470 | bellard | s->status |= UHCI_STS_USBERR; |
618 | bb36d470 | bellard | uhci_update_irq(s); |
619 | bb36d470 | bellard | } |
620 | bb36d470 | bellard | } |
621 | 5fafdf24 | ths | td->ctrl = (td->ctrl & ~(3 << TD_CTRL_ERROR_SHIFT)) |
|
622 | bb36d470 | bellard | (err << TD_CTRL_ERROR_SHIFT); |
623 | bb36d470 | bellard | return 1; |
624 | bb36d470 | bellard | case USB_RET_NAK:
|
625 | bb36d470 | bellard | td->ctrl |= TD_CTRL_NAK; |
626 | bb36d470 | bellard | if (pid == USB_TOKEN_SETUP)
|
627 | bb36d470 | bellard | goto do_timeout;
|
628 | bb36d470 | bellard | return 1; |
629 | bb36d470 | bellard | case USB_RET_STALL:
|
630 | bb36d470 | bellard | td->ctrl |= TD_CTRL_STALL; |
631 | bb36d470 | bellard | td->ctrl &= ~TD_CTRL_ACTIVE; |
632 | bb36d470 | bellard | return 1; |
633 | bb36d470 | bellard | case USB_RET_BABBLE:
|
634 | bb36d470 | bellard | td->ctrl |= TD_CTRL_BABBLE | TD_CTRL_STALL; |
635 | bb36d470 | bellard | td->ctrl &= ~TD_CTRL_ACTIVE; |
636 | bb36d470 | bellard | /* frame interrupted */
|
637 | bb36d470 | bellard | return -1; |
638 | bb36d470 | bellard | } |
639 | bb36d470 | bellard | } |
640 | bb36d470 | bellard | } |
641 | bb36d470 | bellard | |
642 | 4d611c9a | pbrook | static void uhci_async_complete_packet(USBPacket * packet, void *opaque) |
643 | 4d611c9a | pbrook | { |
644 | 4d611c9a | pbrook | UHCIState *s = opaque; |
645 | 4d611c9a | pbrook | UHCI_QH qh; |
646 | 4d611c9a | pbrook | UHCI_TD td; |
647 | 4d611c9a | pbrook | uint32_t link; |
648 | 4d611c9a | pbrook | uint32_t old_td_ctrl; |
649 | 4d611c9a | pbrook | uint32_t val; |
650 | b9dc033c | balrog | uint32_t frame_addr; |
651 | 4d611c9a | pbrook | int ret;
|
652 | 4d611c9a | pbrook | |
653 | b9dc033c | balrog | /* Handle async isochronous packet completion */
|
654 | b9dc033c | balrog | frame_addr = s->async_frame_addr; |
655 | b9dc033c | balrog | if (frame_addr) {
|
656 | b9dc033c | balrog | cpu_physical_memory_read(frame_addr, (uint8_t *)&link, 4);
|
657 | b9dc033c | balrog | le32_to_cpus(&link); |
658 | b9dc033c | balrog | |
659 | b9dc033c | balrog | cpu_physical_memory_read(link & ~0xf, (uint8_t *)&td, sizeof(td)); |
660 | b9dc033c | balrog | le32_to_cpus(&td.link); |
661 | b9dc033c | balrog | le32_to_cpus(&td.ctrl); |
662 | b9dc033c | balrog | le32_to_cpus(&td.token); |
663 | b9dc033c | balrog | le32_to_cpus(&td.buffer); |
664 | b9dc033c | balrog | old_td_ctrl = td.ctrl; |
665 | b9dc033c | balrog | ret = uhci_handle_td(s, &td, &s->pending_int_mask, 1);
|
666 | b9dc033c | balrog | |
667 | b9dc033c | balrog | /* update the status bits of the TD */
|
668 | b9dc033c | balrog | if (old_td_ctrl != td.ctrl) {
|
669 | b9dc033c | balrog | val = cpu_to_le32(td.ctrl); |
670 | b9dc033c | balrog | cpu_physical_memory_write((link & ~0xf) + 4, |
671 | b9dc033c | balrog | (const uint8_t *)&val,
|
672 | b9dc033c | balrog | sizeof(val));
|
673 | b9dc033c | balrog | } |
674 | b9dc033c | balrog | if (ret == 2) { |
675 | b9dc033c | balrog | s->async_frame_addr = frame_addr; |
676 | b9dc033c | balrog | } else if (ret == 0) { |
677 | b9dc033c | balrog | /* update qh element link */
|
678 | b9dc033c | balrog | val = cpu_to_le32(td.link); |
679 | b9dc033c | balrog | cpu_physical_memory_write(frame_addr, |
680 | b9dc033c | balrog | (const uint8_t *)&val,
|
681 | b9dc033c | balrog | sizeof(val));
|
682 | b9dc033c | balrog | } |
683 | b9dc033c | balrog | return;
|
684 | b9dc033c | balrog | } |
685 | b9dc033c | balrog | |
686 | 4d611c9a | pbrook | link = s->async_qh; |
687 | 4d611c9a | pbrook | if (!link) {
|
688 | 4d611c9a | pbrook | /* This should never happen. It means a TD somehow got removed
|
689 | 4d611c9a | pbrook | without cancelling the associated async IO request. */
|
690 | 4d611c9a | pbrook | return;
|
691 | 4d611c9a | pbrook | } |
692 | 4d611c9a | pbrook | cpu_physical_memory_read(link & ~0xf, (uint8_t *)&qh, sizeof(qh)); |
693 | 4d611c9a | pbrook | le32_to_cpus(&qh.link); |
694 | 4d611c9a | pbrook | le32_to_cpus(&qh.el_link); |
695 | 4d611c9a | pbrook | /* Re-process the queue containing the async packet. */
|
696 | 4d611c9a | pbrook | while (1) { |
697 | 5fafdf24 | ths | cpu_physical_memory_read(qh.el_link & ~0xf,
|
698 | 4d611c9a | pbrook | (uint8_t *)&td, sizeof(td));
|
699 | 4d611c9a | pbrook | le32_to_cpus(&td.link); |
700 | 4d611c9a | pbrook | le32_to_cpus(&td.ctrl); |
701 | 4d611c9a | pbrook | le32_to_cpus(&td.token); |
702 | 4d611c9a | pbrook | le32_to_cpus(&td.buffer); |
703 | 4d611c9a | pbrook | old_td_ctrl = td.ctrl; |
704 | b9dc033c | balrog | ret = uhci_handle_td(s, &td, &s->pending_int_mask, 1);
|
705 | b9dc033c | balrog | |
706 | 4d611c9a | pbrook | /* update the status bits of the TD */
|
707 | 4d611c9a | pbrook | if (old_td_ctrl != td.ctrl) {
|
708 | 4d611c9a | pbrook | val = cpu_to_le32(td.ctrl); |
709 | 5fafdf24 | ths | cpu_physical_memory_write((qh.el_link & ~0xf) + 4, |
710 | 5fafdf24 | ths | (const uint8_t *)&val,
|
711 | 4d611c9a | pbrook | sizeof(val));
|
712 | 4d611c9a | pbrook | } |
713 | 4d611c9a | pbrook | if (ret < 0) |
714 | 4d611c9a | pbrook | break; /* interrupted frame */ |
715 | 4d611c9a | pbrook | if (ret == 2) { |
716 | 4d611c9a | pbrook | s->async_qh = link; |
717 | 4d611c9a | pbrook | break;
|
718 | 4d611c9a | pbrook | } else if (ret == 0) { |
719 | 4d611c9a | pbrook | /* update qh element link */
|
720 | 4d611c9a | pbrook | qh.el_link = td.link; |
721 | 4d611c9a | pbrook | val = cpu_to_le32(qh.el_link); |
722 | 5fafdf24 | ths | cpu_physical_memory_write((link & ~0xf) + 4, |
723 | 5fafdf24 | ths | (const uint8_t *)&val,
|
724 | 4d611c9a | pbrook | sizeof(val));
|
725 | 4d611c9a | pbrook | if (!(qh.el_link & 4)) |
726 | 4d611c9a | pbrook | break;
|
727 | 4d611c9a | pbrook | } |
728 | 4d611c9a | pbrook | break;
|
729 | 4d611c9a | pbrook | } |
730 | 4d611c9a | pbrook | } |
731 | 4d611c9a | pbrook | |
732 | bb36d470 | bellard | static void uhci_frame_timer(void *opaque) |
733 | bb36d470 | bellard | { |
734 | bb36d470 | bellard | UHCIState *s = opaque; |
735 | bb36d470 | bellard | int64_t expire_time; |
736 | 60fe76f3 | ths | uint32_t frame_addr, link, old_td_ctrl, val, int_mask; |
737 | 60fe76f3 | ths | int cnt, ret;
|
738 | bb36d470 | bellard | UHCI_TD td; |
739 | bb36d470 | bellard | UHCI_QH qh; |
740 | 4d611c9a | pbrook | uint32_t old_async_qh; |
741 | bb36d470 | bellard | |
742 | bb36d470 | bellard | if (!(s->cmd & UHCI_CMD_RS)) {
|
743 | bb36d470 | bellard | qemu_del_timer(s->frame_timer); |
744 | 52328140 | bellard | /* set hchalted bit in status - UHCI11D 2.1.2 */
|
745 | 52328140 | bellard | s->status |= UHCI_STS_HCHALTED; |
746 | bb36d470 | bellard | return;
|
747 | bb36d470 | bellard | } |
748 | 4d611c9a | pbrook | /* Complete the previous frame. */
|
749 | 4d611c9a | pbrook | s->frnum = (s->frnum + 1) & 0x7ff; |
750 | 4d611c9a | pbrook | if (s->pending_int_mask) {
|
751 | 4d611c9a | pbrook | s->status2 |= s->pending_int_mask; |
752 | 4d611c9a | pbrook | s->status |= UHCI_STS_USBINT; |
753 | 4d611c9a | pbrook | uhci_update_irq(s); |
754 | 4d611c9a | pbrook | } |
755 | 4d611c9a | pbrook | old_async_qh = s->async_qh; |
756 | bb36d470 | bellard | frame_addr = s->fl_base_addr + ((s->frnum & 0x3ff) << 2); |
757 | bb36d470 | bellard | cpu_physical_memory_read(frame_addr, (uint8_t *)&link, 4);
|
758 | bb36d470 | bellard | le32_to_cpus(&link); |
759 | bb36d470 | bellard | int_mask = 0;
|
760 | bb36d470 | bellard | cnt = FRAME_MAX_LOOPS; |
761 | bb36d470 | bellard | while ((link & 1) == 0) { |
762 | bb36d470 | bellard | if (--cnt == 0) |
763 | bb36d470 | bellard | break;
|
764 | bb36d470 | bellard | /* valid frame */
|
765 | bb36d470 | bellard | if (link & 2) { |
766 | bb36d470 | bellard | /* QH */
|
767 | 4d611c9a | pbrook | if (link == s->async_qh) {
|
768 | 4d611c9a | pbrook | /* We've found a previously issues packet.
|
769 | 4d611c9a | pbrook | Nothing else to do. */
|
770 | 4d611c9a | pbrook | old_async_qh = 0;
|
771 | 4d611c9a | pbrook | break;
|
772 | 4d611c9a | pbrook | } |
773 | bb36d470 | bellard | cpu_physical_memory_read(link & ~0xf, (uint8_t *)&qh, sizeof(qh)); |
774 | bb36d470 | bellard | le32_to_cpus(&qh.link); |
775 | bb36d470 | bellard | le32_to_cpus(&qh.el_link); |
776 | bb36d470 | bellard | depth_first:
|
777 | bb36d470 | bellard | if (qh.el_link & 1) { |
778 | bb36d470 | bellard | /* no element : go to next entry */
|
779 | bb36d470 | bellard | link = qh.link; |
780 | bb36d470 | bellard | } else if (qh.el_link & 2) { |
781 | bb36d470 | bellard | /* QH */
|
782 | bb36d470 | bellard | link = qh.el_link; |
783 | 4d611c9a | pbrook | } else if (s->async_qh) { |
784 | 4d611c9a | pbrook | /* We can only cope with one pending packet. Keep looking
|
785 | 4d611c9a | pbrook | for the previously issued packet. */
|
786 | 4d611c9a | pbrook | link = qh.link; |
787 | bb36d470 | bellard | } else {
|
788 | bb36d470 | bellard | /* TD */
|
789 | bb36d470 | bellard | if (--cnt == 0) |
790 | bb36d470 | bellard | break;
|
791 | 5fafdf24 | ths | cpu_physical_memory_read(qh.el_link & ~0xf,
|
792 | bb36d470 | bellard | (uint8_t *)&td, sizeof(td));
|
793 | bb36d470 | bellard | le32_to_cpus(&td.link); |
794 | bb36d470 | bellard | le32_to_cpus(&td.ctrl); |
795 | bb36d470 | bellard | le32_to_cpus(&td.token); |
796 | bb36d470 | bellard | le32_to_cpus(&td.buffer); |
797 | bb36d470 | bellard | old_td_ctrl = td.ctrl; |
798 | b9dc033c | balrog | ret = uhci_handle_td(s, &td, &int_mask, 0);
|
799 | b9dc033c | balrog | |
800 | bb36d470 | bellard | /* update the status bits of the TD */
|
801 | bb36d470 | bellard | if (old_td_ctrl != td.ctrl) {
|
802 | bb36d470 | bellard | val = cpu_to_le32(td.ctrl); |
803 | 5fafdf24 | ths | cpu_physical_memory_write((qh.el_link & ~0xf) + 4, |
804 | 5fafdf24 | ths | (const uint8_t *)&val,
|
805 | bb36d470 | bellard | sizeof(val));
|
806 | bb36d470 | bellard | } |
807 | bb36d470 | bellard | if (ret < 0) |
808 | bb36d470 | bellard | break; /* interrupted frame */ |
809 | 4d611c9a | pbrook | if (ret == 2) { |
810 | 4d611c9a | pbrook | s->async_qh = link; |
811 | 4d611c9a | pbrook | } else if (ret == 0) { |
812 | bb36d470 | bellard | /* update qh element link */
|
813 | bb36d470 | bellard | qh.el_link = td.link; |
814 | bb36d470 | bellard | val = cpu_to_le32(qh.el_link); |
815 | 5fafdf24 | ths | cpu_physical_memory_write((link & ~0xf) + 4, |
816 | 5fafdf24 | ths | (const uint8_t *)&val,
|
817 | bb36d470 | bellard | sizeof(val));
|
818 | bb36d470 | bellard | if (qh.el_link & 4) { |
819 | bb36d470 | bellard | /* depth first */
|
820 | bb36d470 | bellard | goto depth_first;
|
821 | bb36d470 | bellard | } |
822 | bb36d470 | bellard | } |
823 | bb36d470 | bellard | /* go to next entry */
|
824 | bb36d470 | bellard | link = qh.link; |
825 | bb36d470 | bellard | } |
826 | bb36d470 | bellard | } else {
|
827 | bb36d470 | bellard | /* TD */
|
828 | bb36d470 | bellard | cpu_physical_memory_read(link & ~0xf, (uint8_t *)&td, sizeof(td)); |
829 | bb36d470 | bellard | le32_to_cpus(&td.link); |
830 | bb36d470 | bellard | le32_to_cpus(&td.ctrl); |
831 | bb36d470 | bellard | le32_to_cpus(&td.token); |
832 | bb36d470 | bellard | le32_to_cpus(&td.buffer); |
833 | b9dc033c | balrog | |
834 | b9dc033c | balrog | /* Handle isochonous transfer. */
|
835 | b9dc033c | balrog | /* FIXME: might be more than one isoc in frame */
|
836 | b9dc033c | balrog | old_td_ctrl = td.ctrl; |
837 | b9dc033c | balrog | ret = uhci_handle_td(s, &td, &int_mask, 0);
|
838 | b9dc033c | balrog | |
839 | b9dc033c | balrog | /* update the status bits of the TD */
|
840 | b9dc033c | balrog | if (old_td_ctrl != td.ctrl) {
|
841 | b9dc033c | balrog | val = cpu_to_le32(td.ctrl); |
842 | b9dc033c | balrog | cpu_physical_memory_write((link & ~0xf) + 4, |
843 | b9dc033c | balrog | (const uint8_t *)&val,
|
844 | b9dc033c | balrog | sizeof(val));
|
845 | b9dc033c | balrog | } |
846 | b9dc033c | balrog | if (ret < 0) |
847 | b9dc033c | balrog | break; /* interrupted frame */ |
848 | b9dc033c | balrog | if (ret == 2) { |
849 | b9dc033c | balrog | s->async_frame_addr = frame_addr; |
850 | bb36d470 | bellard | } |
851 | bb36d470 | bellard | link = td.link; |
852 | bb36d470 | bellard | } |
853 | bb36d470 | bellard | } |
854 | 4d611c9a | pbrook | s->pending_int_mask = int_mask; |
855 | 4d611c9a | pbrook | if (old_async_qh) {
|
856 | 4d611c9a | pbrook | /* A previously started transfer has disappeared from the transfer
|
857 | 4d611c9a | pbrook | list. There's nothing useful we can do with it now, so just
|
858 | 4d611c9a | pbrook | discard the packet and hope it wasn't too important. */
|
859 | 4d611c9a | pbrook | #ifdef DEBUG
|
860 | 4d611c9a | pbrook | printf("Discarding USB packet\n");
|
861 | 4d611c9a | pbrook | #endif
|
862 | 4d611c9a | pbrook | usb_cancel_packet(&s->usb_packet); |
863 | 4d611c9a | pbrook | s->async_qh = 0;
|
864 | bb36d470 | bellard | } |
865 | b9dc033c | balrog | |
866 | bb36d470 | bellard | /* prepare the timer for the next frame */
|
867 | 5fafdf24 | ths | expire_time = qemu_get_clock(vm_clock) + |
868 | bb36d470 | bellard | (ticks_per_sec / FRAME_TIMER_FREQ); |
869 | bb36d470 | bellard | qemu_mod_timer(s->frame_timer, expire_time); |
870 | bb36d470 | bellard | } |
871 | bb36d470 | bellard | |
872 | 5fafdf24 | ths | static void uhci_map(PCIDevice *pci_dev, int region_num, |
873 | bb36d470 | bellard | uint32_t addr, uint32_t size, int type)
|
874 | bb36d470 | bellard | { |
875 | bb36d470 | bellard | UHCIState *s = (UHCIState *)pci_dev; |
876 | bb36d470 | bellard | |
877 | bb36d470 | bellard | register_ioport_write(addr, 32, 2, uhci_ioport_writew, s); |
878 | bb36d470 | bellard | register_ioport_read(addr, 32, 2, uhci_ioport_readw, s); |
879 | bb36d470 | bellard | register_ioport_write(addr, 32, 4, uhci_ioport_writel, s); |
880 | bb36d470 | bellard | register_ioport_read(addr, 32, 4, uhci_ioport_readl, s); |
881 | bb36d470 | bellard | register_ioport_write(addr, 32, 1, uhci_ioport_writeb, s); |
882 | bb36d470 | bellard | register_ioport_read(addr, 32, 1, uhci_ioport_readb, s); |
883 | bb36d470 | bellard | } |
884 | bb36d470 | bellard | |
885 | afcc3cdf | ths | void usb_uhci_piix3_init(PCIBus *bus, int devfn) |
886 | bb36d470 | bellard | { |
887 | bb36d470 | bellard | UHCIState *s; |
888 | bb36d470 | bellard | uint8_t *pci_conf; |
889 | bb36d470 | bellard | int i;
|
890 | bb36d470 | bellard | |
891 | bb36d470 | bellard | s = (UHCIState *)pci_register_device(bus, |
892 | bb36d470 | bellard | "USB-UHCI", sizeof(UHCIState), |
893 | 502a5395 | pbrook | devfn, NULL, NULL); |
894 | bb36d470 | bellard | pci_conf = s->dev.config; |
895 | bb36d470 | bellard | pci_conf[0x00] = 0x86; |
896 | bb36d470 | bellard | pci_conf[0x01] = 0x80; |
897 | bb36d470 | bellard | pci_conf[0x02] = 0x20; |
898 | bb36d470 | bellard | pci_conf[0x03] = 0x70; |
899 | bb36d470 | bellard | pci_conf[0x08] = 0x01; // revision number |
900 | bb36d470 | bellard | pci_conf[0x09] = 0x00; |
901 | bb36d470 | bellard | pci_conf[0x0a] = 0x03; |
902 | bb36d470 | bellard | pci_conf[0x0b] = 0x0c; |
903 | bb36d470 | bellard | pci_conf[0x0e] = 0x00; // header_type |
904 | f04308e4 | bellard | pci_conf[0x3d] = 4; // interrupt pin 3 |
905 | 38ca0f6d | pbrook | pci_conf[0x60] = 0x10; // release number |
906 | 3b46e624 | ths | |
907 | bb36d470 | bellard | for(i = 0; i < NB_PORTS; i++) { |
908 | 0d92ed30 | pbrook | qemu_register_usb_port(&s->ports[i].port, s, i, uhci_attach); |
909 | bb36d470 | bellard | } |
910 | bb36d470 | bellard | s->frame_timer = qemu_new_timer(vm_clock, uhci_frame_timer, s); |
911 | bb36d470 | bellard | |
912 | bb36d470 | bellard | uhci_reset(s); |
913 | bb36d470 | bellard | |
914 | 38ca0f6d | pbrook | /* Use region 4 for consistency with real hardware. BSD guests seem
|
915 | 38ca0f6d | pbrook | to rely on this. */
|
916 | 5fafdf24 | ths | pci_register_io_region(&s->dev, 4, 0x20, |
917 | bb36d470 | bellard | PCI_ADDRESS_SPACE_IO, uhci_map); |
918 | bb36d470 | bellard | } |
919 | afcc3cdf | ths | |
920 | afcc3cdf | ths | void usb_uhci_piix4_init(PCIBus *bus, int devfn) |
921 | afcc3cdf | ths | { |
922 | afcc3cdf | ths | UHCIState *s; |
923 | afcc3cdf | ths | uint8_t *pci_conf; |
924 | afcc3cdf | ths | int i;
|
925 | afcc3cdf | ths | |
926 | afcc3cdf | ths | s = (UHCIState *)pci_register_device(bus, |
927 | afcc3cdf | ths | "USB-UHCI", sizeof(UHCIState), |
928 | afcc3cdf | ths | devfn, NULL, NULL); |
929 | afcc3cdf | ths | pci_conf = s->dev.config; |
930 | afcc3cdf | ths | pci_conf[0x00] = 0x86; |
931 | afcc3cdf | ths | pci_conf[0x01] = 0x80; |
932 | afcc3cdf | ths | pci_conf[0x02] = 0x12; |
933 | afcc3cdf | ths | pci_conf[0x03] = 0x71; |
934 | afcc3cdf | ths | pci_conf[0x08] = 0x01; // revision number |
935 | afcc3cdf | ths | pci_conf[0x09] = 0x00; |
936 | afcc3cdf | ths | pci_conf[0x0a] = 0x03; |
937 | afcc3cdf | ths | pci_conf[0x0b] = 0x0c; |
938 | afcc3cdf | ths | pci_conf[0x0e] = 0x00; // header_type |
939 | afcc3cdf | ths | pci_conf[0x3d] = 4; // interrupt pin 3 |
940 | afcc3cdf | ths | pci_conf[0x60] = 0x10; // release number |
941 | afcc3cdf | ths | |
942 | afcc3cdf | ths | for(i = 0; i < NB_PORTS; i++) { |
943 | afcc3cdf | ths | qemu_register_usb_port(&s->ports[i].port, s, i, uhci_attach); |
944 | afcc3cdf | ths | } |
945 | afcc3cdf | ths | s->frame_timer = qemu_new_timer(vm_clock, uhci_frame_timer, s); |
946 | afcc3cdf | ths | |
947 | afcc3cdf | ths | uhci_reset(s); |
948 | afcc3cdf | ths | |
949 | afcc3cdf | ths | /* Use region 4 for consistency with real hardware. BSD guests seem
|
950 | afcc3cdf | ths | to rely on this. */
|
951 | afcc3cdf | ths | pci_register_io_region(&s->dev, 4, 0x20, |
952 | afcc3cdf | ths | PCI_ADDRESS_SPACE_IO, uhci_map); |
953 | afcc3cdf | ths | } |