root / docs / specs / ivshmem_device_spec.txt @ a22f123c
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2 | b6828931 | Cam Macdonell | Device Specification for Inter-VM shared memory device |
3 | b6828931 | Cam Macdonell | ------------------------------------------------------ |
4 | b6828931 | Cam Macdonell | |
5 | b6828931 | Cam Macdonell | The Inter-VM shared memory device is designed to share a region of memory to |
6 | b6828931 | Cam Macdonell | userspace in multiple virtual guests. The memory region does not belong to any |
7 | b6828931 | Cam Macdonell | guest, but is a POSIX memory object on the host. Optionally, the device may |
8 | b6828931 | Cam Macdonell | support sending interrupts to other guests sharing the same memory region. |
9 | b6828931 | Cam Macdonell | |
10 | b6828931 | Cam Macdonell | |
11 | b6828931 | Cam Macdonell | The Inter-VM PCI device |
12 | b6828931 | Cam Macdonell | ----------------------- |
13 | b6828931 | Cam Macdonell | |
14 | b6828931 | Cam Macdonell | *BARs* |
15 | b6828931 | Cam Macdonell | |
16 | b6828931 | Cam Macdonell | The device supports three BARs. BAR0 is a 1 Kbyte MMIO region to support |
17 | b6828931 | Cam Macdonell | registers. BAR1 is used for MSI-X when it is enabled in the device. BAR2 is |
18 | b6828931 | Cam Macdonell | used to map the shared memory object from the host. The size of BAR2 is |
19 | b6828931 | Cam Macdonell | specified when the guest is started and must be a power of 2 in size. |
20 | b6828931 | Cam Macdonell | |
21 | b6828931 | Cam Macdonell | *Registers* |
22 | b6828931 | Cam Macdonell | |
23 | b6828931 | Cam Macdonell | The device currently supports 4 registers of 32-bits each. Registers |
24 | b6828931 | Cam Macdonell | are used for synchronization between guests sharing the same memory object when |
25 | b6828931 | Cam Macdonell | interrupts are supported (this requires using the shared memory server). |
26 | b6828931 | Cam Macdonell | |
27 | b6828931 | Cam Macdonell | The server assigns each VM an ID number and sends this ID number to the Qemu |
28 | b6828931 | Cam Macdonell | process when the guest starts. |
29 | b6828931 | Cam Macdonell | |
30 | b6828931 | Cam Macdonell | enum ivshmem_registers { |
31 | b6828931 | Cam Macdonell | IntrMask = 0, |
32 | b6828931 | Cam Macdonell | IntrStatus = 4, |
33 | b6828931 | Cam Macdonell | IVPosition = 8, |
34 | b6828931 | Cam Macdonell | Doorbell = 12 |
35 | b6828931 | Cam Macdonell | }; |
36 | b6828931 | Cam Macdonell | |
37 | b6828931 | Cam Macdonell | The first two registers are the interrupt mask and status registers. Mask and |
38 | b6828931 | Cam Macdonell | status are only used with pin-based interrupts. They are unused with MSI |
39 | b6828931 | Cam Macdonell | interrupts. |
40 | b6828931 | Cam Macdonell | |
41 | b6828931 | Cam Macdonell | Status Register: The status register is set to 1 when an interrupt occurs. |
42 | b6828931 | Cam Macdonell | |
43 | b6828931 | Cam Macdonell | Mask Register: The mask register is bitwise ANDed with the interrupt status |
44 | b6828931 | Cam Macdonell | and the result will raise an interrupt if it is non-zero. However, since 1 is |
45 | b6828931 | Cam Macdonell | the only value the status will be set to, it is only the first bit of the mask |
46 | b6828931 | Cam Macdonell | that has any effect. Therefore interrupts can be masked by setting the first |
47 | b6828931 | Cam Macdonell | bit to 0 and unmasked by setting the first bit to 1. |
48 | b6828931 | Cam Macdonell | |
49 | b6828931 | Cam Macdonell | IVPosition Register: The IVPosition register is read-only and reports the |
50 | b6828931 | Cam Macdonell | guest's ID number. The guest IDs are non-negative integers. When using the |
51 | b6828931 | Cam Macdonell | server, since the server is a separate process, the VM ID will only be set when |
52 | b6828931 | Cam Macdonell | the device is ready (shared memory is received from the server and accessible via |
53 | b6828931 | Cam Macdonell | the device). If the device is not ready, the IVPosition will return -1. |
54 | b6828931 | Cam Macdonell | Applications should ensure that they have a valid VM ID before accessing the |
55 | b6828931 | Cam Macdonell | shared memory. |
56 | b6828931 | Cam Macdonell | |
57 | b6828931 | Cam Macdonell | Doorbell Register: To interrupt another guest, a guest must write to the |
58 | b6828931 | Cam Macdonell | Doorbell register. The doorbell register is 32-bits, logically divided into |
59 | b6828931 | Cam Macdonell | two 16-bit fields. The high 16-bits are the guest ID to interrupt and the low |
60 | b6828931 | Cam Macdonell | 16-bits are the interrupt vector to trigger. The semantics of the value |
61 | b6828931 | Cam Macdonell | written to the doorbell depends on whether the device is using MSI or a regular |
62 | b6828931 | Cam Macdonell | pin-based interrupt. In short, MSI uses vectors while regular interrupts set the |
63 | b6828931 | Cam Macdonell | status register. |
64 | b6828931 | Cam Macdonell | |
65 | b6828931 | Cam Macdonell | Regular Interrupts |
66 | b6828931 | Cam Macdonell | |
67 | b6828931 | Cam Macdonell | If regular interrupts are used (due to either a guest not supporting MSI or the |
68 | b6828931 | Cam Macdonell | user specifying not to use them on startup) then the value written to the lower |
69 | b6828931 | Cam Macdonell | 16-bits of the Doorbell register results is arbitrary and will trigger an |
70 | b6828931 | Cam Macdonell | interrupt in the destination guest. |
71 | b6828931 | Cam Macdonell | |
72 | b6828931 | Cam Macdonell | Message Signalled Interrupts |
73 | b6828931 | Cam Macdonell | |
74 | b6828931 | Cam Macdonell | A ivshmem device may support multiple MSI vectors. If so, the lower 16-bits |
75 | b6828931 | Cam Macdonell | written to the Doorbell register must be between 0 and the maximum number of |
76 | b6828931 | Cam Macdonell | vectors the guest supports. The lower 16 bits written to the doorbell is the |
77 | b6828931 | Cam Macdonell | MSI vector that will be raised in the destination guest. The number of MSI |
78 | b6828931 | Cam Macdonell | vectors is configurable but it is set when the VM is started. |
79 | b6828931 | Cam Macdonell | |
80 | b6828931 | Cam Macdonell | The important thing to remember with MSI is that it is only a signal, no status |
81 | b6828931 | Cam Macdonell | is set (since MSI interrupts are not shared). All information other than the |
82 | b6828931 | Cam Macdonell | interrupt itself should be communicated via the shared memory region. Devices |
83 | b6828931 | Cam Macdonell | supporting multiple MSI vectors can use different vectors to indicate different |
84 | b6828931 | Cam Macdonell | events have occurred. The semantics of interrupt vectors are left to the |
85 | b6828931 | Cam Macdonell | user's discretion. |
86 | b6828931 | Cam Macdonell | |
87 | b6828931 | Cam Macdonell | |
88 | b6828931 | Cam Macdonell | Usage in the Guest |
89 | b6828931 | Cam Macdonell | ------------------ |
90 | b6828931 | Cam Macdonell | |
91 | b6828931 | Cam Macdonell | The shared memory device is intended to be used with the provided UIO driver. |
92 | b6828931 | Cam Macdonell | Very little configuration is needed. The guest should map BAR0 to access the |
93 | b6828931 | Cam Macdonell | registers (an array of 32-bit ints allows simple writing) and map BAR2 to |
94 | b6828931 | Cam Macdonell | access the shared memory region itself. The size of the shared memory region |
95 | b6828931 | Cam Macdonell | is specified when the guest (or shared memory server) is started. A guest may |
96 | b6828931 | Cam Macdonell | map the whole shared memory region or only part of it. |