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1 | 27503323 | bellard | /*
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2 | 27503323 | bellard | * QEMU DMA emulation
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3 | 85571bc7 | bellard | *
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4 | 85571bc7 | bellard | * Copyright (c) 2003-2004 Vassili Karpov (malc)
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5 | 85571bc7 | bellard | *
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6 | 27503323 | bellard | * Permission is hereby granted, free of charge, to any person obtaining a copy
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7 | 27503323 | bellard | * of this software and associated documentation files (the "Software"), to deal
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8 | 27503323 | bellard | * in the Software without restriction, including without limitation the rights
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9 | 27503323 | bellard | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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10 | 27503323 | bellard | * copies of the Software, and to permit persons to whom the Software is
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11 | 27503323 | bellard | * furnished to do so, subject to the following conditions:
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12 | 27503323 | bellard | *
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13 | 27503323 | bellard | * The above copyright notice and this permission notice shall be included in
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14 | 27503323 | bellard | * all copies or substantial portions of the Software.
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15 | 27503323 | bellard | *
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16 | 27503323 | bellard | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 | 27503323 | bellard | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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18 | 27503323 | bellard | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 | 27503323 | bellard | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 | 27503323 | bellard | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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21 | 27503323 | bellard | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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22 | 27503323 | bellard | * THE SOFTWARE.
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23 | 27503323 | bellard | */
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24 | 87ecb68b | pbrook | #include "hw.h" |
25 | 87ecb68b | pbrook | #include "isa.h" |
26 | 27503323 | bellard | |
27 | 85571bc7 | bellard | /* #define DEBUG_DMA */
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28 | 7ebb5e41 | bellard | |
29 | 85571bc7 | bellard | #define dolog(...) fprintf (stderr, "dma: " __VA_ARGS__) |
30 | 27503323 | bellard | #ifdef DEBUG_DMA
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31 | 27503323 | bellard | #define lwarn(...) fprintf (stderr, "dma: " __VA_ARGS__) |
32 | 27503323 | bellard | #define linfo(...) fprintf (stderr, "dma: " __VA_ARGS__) |
33 | 27503323 | bellard | #define ldebug(...) fprintf (stderr, "dma: " __VA_ARGS__) |
34 | 27503323 | bellard | #else
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35 | 27503323 | bellard | #define lwarn(...)
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36 | 27503323 | bellard | #define linfo(...)
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37 | 27503323 | bellard | #define ldebug(...)
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38 | 27503323 | bellard | #endif
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39 | 27503323 | bellard | |
40 | 27503323 | bellard | #define LENOFA(a) ((int) (sizeof(a)/sizeof(a[0]))) |
41 | 27503323 | bellard | |
42 | 27503323 | bellard | struct dma_regs {
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43 | 27503323 | bellard | int now[2]; |
44 | 27503323 | bellard | uint16_t base[2];
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45 | 27503323 | bellard | uint8_t mode; |
46 | 27503323 | bellard | uint8_t page; |
47 | b0bda528 | bellard | uint8_t pageh; |
48 | 27503323 | bellard | uint8_t dack; |
49 | 27503323 | bellard | uint8_t eop; |
50 | 16f62432 | bellard | DMA_transfer_handler transfer_handler; |
51 | 16f62432 | bellard | void *opaque;
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52 | 27503323 | bellard | }; |
53 | 27503323 | bellard | |
54 | 27503323 | bellard | #define ADDR 0 |
55 | 27503323 | bellard | #define COUNT 1 |
56 | 27503323 | bellard | |
57 | 27503323 | bellard | static struct dma_cont { |
58 | 27503323 | bellard | uint8_t status; |
59 | 27503323 | bellard | uint8_t command; |
60 | 27503323 | bellard | uint8_t mask; |
61 | 27503323 | bellard | uint8_t flip_flop; |
62 | 9eb153f1 | bellard | int dshift;
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63 | 27503323 | bellard | struct dma_regs regs[4]; |
64 | 27503323 | bellard | } dma_controllers[2];
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65 | 27503323 | bellard | |
66 | 27503323 | bellard | enum {
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67 | e875c40a | bellard | CMD_MEMORY_TO_MEMORY = 0x01,
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68 | e875c40a | bellard | CMD_FIXED_ADDRESS = 0x02,
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69 | e875c40a | bellard | CMD_BLOCK_CONTROLLER = 0x04,
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70 | e875c40a | bellard | CMD_COMPRESSED_TIME = 0x08,
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71 | e875c40a | bellard | CMD_CYCLIC_PRIORITY = 0x10,
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72 | e875c40a | bellard | CMD_EXTENDED_WRITE = 0x20,
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73 | e875c40a | bellard | CMD_LOW_DREQ = 0x40,
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74 | e875c40a | bellard | CMD_LOW_DACK = 0x80,
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75 | e875c40a | bellard | CMD_NOT_SUPPORTED = CMD_MEMORY_TO_MEMORY | CMD_FIXED_ADDRESS |
76 | e875c40a | bellard | | CMD_COMPRESSED_TIME | CMD_CYCLIC_PRIORITY | CMD_EXTENDED_WRITE |
77 | e875c40a | bellard | | CMD_LOW_DREQ | CMD_LOW_DACK |
78 | 27503323 | bellard | |
79 | 27503323 | bellard | }; |
80 | 27503323 | bellard | |
81 | 9eb153f1 | bellard | static int channels[8] = {-1, 2, 3, 1, -1, -1, -1, 0}; |
82 | 9eb153f1 | bellard | |
83 | 7d977de7 | bellard | static void write_page (void *opaque, uint32_t nport, uint32_t data) |
84 | 27503323 | bellard | { |
85 | 9eb153f1 | bellard | struct dma_cont *d = opaque;
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86 | 27503323 | bellard | int ichan;
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87 | 27503323 | bellard | |
88 | 9eb153f1 | bellard | ichan = channels[nport & 7];
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89 | 27503323 | bellard | if (-1 == ichan) { |
90 | 85571bc7 | bellard | dolog ("invalid channel %#x %#x\n", nport, data);
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91 | 27503323 | bellard | return;
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92 | 27503323 | bellard | } |
93 | 9eb153f1 | bellard | d->regs[ichan].page = data; |
94 | 9eb153f1 | bellard | } |
95 | 9eb153f1 | bellard | |
96 | b0bda528 | bellard | static void write_pageh (void *opaque, uint32_t nport, uint32_t data) |
97 | 9eb153f1 | bellard | { |
98 | 9eb153f1 | bellard | struct dma_cont *d = opaque;
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99 | 9eb153f1 | bellard | int ichan;
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100 | 27503323 | bellard | |
101 | 9eb153f1 | bellard | ichan = channels[nport & 7];
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102 | b0bda528 | bellard | if (-1 == ichan) { |
103 | 85571bc7 | bellard | dolog ("invalid channel %#x %#x\n", nport, data);
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104 | b0bda528 | bellard | return;
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105 | b0bda528 | bellard | } |
106 | b0bda528 | bellard | d->regs[ichan].pageh = data; |
107 | b0bda528 | bellard | } |
108 | 9eb153f1 | bellard | |
109 | b0bda528 | bellard | static uint32_t read_page (void *opaque, uint32_t nport) |
110 | b0bda528 | bellard | { |
111 | b0bda528 | bellard | struct dma_cont *d = opaque;
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112 | b0bda528 | bellard | int ichan;
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113 | b0bda528 | bellard | |
114 | b0bda528 | bellard | ichan = channels[nport & 7];
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115 | 9eb153f1 | bellard | if (-1 == ichan) { |
116 | 85571bc7 | bellard | dolog ("invalid channel read %#x\n", nport);
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117 | 9eb153f1 | bellard | return 0; |
118 | 9eb153f1 | bellard | } |
119 | 9eb153f1 | bellard | return d->regs[ichan].page;
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120 | 27503323 | bellard | } |
121 | 27503323 | bellard | |
122 | b0bda528 | bellard | static uint32_t read_pageh (void *opaque, uint32_t nport) |
123 | b0bda528 | bellard | { |
124 | b0bda528 | bellard | struct dma_cont *d = opaque;
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125 | b0bda528 | bellard | int ichan;
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126 | b0bda528 | bellard | |
127 | b0bda528 | bellard | ichan = channels[nport & 7];
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128 | b0bda528 | bellard | if (-1 == ichan) { |
129 | 85571bc7 | bellard | dolog ("invalid channel read %#x\n", nport);
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130 | b0bda528 | bellard | return 0; |
131 | b0bda528 | bellard | } |
132 | b0bda528 | bellard | return d->regs[ichan].pageh;
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133 | b0bda528 | bellard | } |
134 | b0bda528 | bellard | |
135 | 9eb153f1 | bellard | static inline void init_chan (struct dma_cont *d, int ichan) |
136 | 27503323 | bellard | { |
137 | 27503323 | bellard | struct dma_regs *r;
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138 | 27503323 | bellard | |
139 | 9eb153f1 | bellard | r = d->regs + ichan; |
140 | 85571bc7 | bellard | r->now[ADDR] = r->base[ADDR] << d->dshift; |
141 | 27503323 | bellard | r->now[COUNT] = 0;
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142 | 27503323 | bellard | } |
143 | 27503323 | bellard | |
144 | 9eb153f1 | bellard | static inline int getff (struct dma_cont *d) |
145 | 27503323 | bellard | { |
146 | 27503323 | bellard | int ff;
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147 | 27503323 | bellard | |
148 | 9eb153f1 | bellard | ff = d->flip_flop; |
149 | 9eb153f1 | bellard | d->flip_flop = !ff; |
150 | 27503323 | bellard | return ff;
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151 | 27503323 | bellard | } |
152 | 27503323 | bellard | |
153 | 7d977de7 | bellard | static uint32_t read_chan (void *opaque, uint32_t nport) |
154 | 27503323 | bellard | { |
155 | 9eb153f1 | bellard | struct dma_cont *d = opaque;
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156 | 85571bc7 | bellard | int ichan, nreg, iport, ff, val, dir;
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157 | 27503323 | bellard | struct dma_regs *r;
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158 | 27503323 | bellard | |
159 | 9eb153f1 | bellard | iport = (nport >> d->dshift) & 0x0f;
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160 | 9eb153f1 | bellard | ichan = iport >> 1;
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161 | 9eb153f1 | bellard | nreg = iport & 1;
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162 | 9eb153f1 | bellard | r = d->regs + ichan; |
163 | 27503323 | bellard | |
164 | 85571bc7 | bellard | dir = ((r->mode >> 5) & 1) ? -1 : 1; |
165 | 9eb153f1 | bellard | ff = getff (d); |
166 | 27503323 | bellard | if (nreg)
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167 | 9eb153f1 | bellard | val = (r->base[COUNT] << d->dshift) - r->now[COUNT]; |
168 | 27503323 | bellard | else
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169 | 85571bc7 | bellard | val = r->now[ADDR] + r->now[COUNT] * dir; |
170 | 27503323 | bellard | |
171 | 85571bc7 | bellard | ldebug ("read_chan %#x -> %d\n", iport, val);
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172 | 9eb153f1 | bellard | return (val >> (d->dshift + (ff << 3))) & 0xff; |
173 | 27503323 | bellard | } |
174 | 27503323 | bellard | |
175 | 7d977de7 | bellard | static void write_chan (void *opaque, uint32_t nport, uint32_t data) |
176 | 27503323 | bellard | { |
177 | 9eb153f1 | bellard | struct dma_cont *d = opaque;
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178 | 9eb153f1 | bellard | int iport, ichan, nreg;
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179 | 27503323 | bellard | struct dma_regs *r;
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180 | 27503323 | bellard | |
181 | 9eb153f1 | bellard | iport = (nport >> d->dshift) & 0x0f;
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182 | 9eb153f1 | bellard | ichan = iport >> 1;
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183 | 9eb153f1 | bellard | nreg = iport & 1;
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184 | 9eb153f1 | bellard | r = d->regs + ichan; |
185 | 9eb153f1 | bellard | if (getff (d)) {
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186 | 3504fe17 | bellard | r->base[nreg] = (r->base[nreg] & 0xff) | ((data << 8) & 0xff00); |
187 | 9eb153f1 | bellard | init_chan (d, ichan); |
188 | 3504fe17 | bellard | } else {
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189 | 3504fe17 | bellard | r->base[nreg] = (r->base[nreg] & 0xff00) | (data & 0xff); |
190 | 27503323 | bellard | } |
191 | 27503323 | bellard | } |
192 | 27503323 | bellard | |
193 | 7d977de7 | bellard | static void write_cont (void *opaque, uint32_t nport, uint32_t data) |
194 | 27503323 | bellard | { |
195 | 9eb153f1 | bellard | struct dma_cont *d = opaque;
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196 | 85571bc7 | bellard | int iport, ichan = 0; |
197 | 27503323 | bellard | |
198 | 9eb153f1 | bellard | iport = (nport >> d->dshift) & 0x0f;
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199 | 27503323 | bellard | switch (iport) {
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200 | 85571bc7 | bellard | case 0x08: /* command */ |
201 | df475d18 | bellard | if ((data != 0) && (data & CMD_NOT_SUPPORTED)) { |
202 | 85571bc7 | bellard | dolog ("command %#x not supported\n", data);
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203 | df475d18 | bellard | return;
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204 | 27503323 | bellard | } |
205 | 27503323 | bellard | d->command = data; |
206 | 27503323 | bellard | break;
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207 | 27503323 | bellard | |
208 | 85571bc7 | bellard | case 0x09: |
209 | 27503323 | bellard | ichan = data & 3;
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210 | 27503323 | bellard | if (data & 4) { |
211 | 27503323 | bellard | d->status |= 1 << (ichan + 4); |
212 | 27503323 | bellard | } |
213 | 27503323 | bellard | else {
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214 | 27503323 | bellard | d->status &= ~(1 << (ichan + 4)); |
215 | 27503323 | bellard | } |
216 | 27503323 | bellard | d->status &= ~(1 << ichan);
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217 | 27503323 | bellard | break;
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218 | 27503323 | bellard | |
219 | 85571bc7 | bellard | case 0x0a: /* single mask */ |
220 | 27503323 | bellard | if (data & 4) |
221 | 27503323 | bellard | d->mask |= 1 << (data & 3); |
222 | 27503323 | bellard | else
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223 | 27503323 | bellard | d->mask &= ~(1 << (data & 3)); |
224 | 27503323 | bellard | break;
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225 | 27503323 | bellard | |
226 | 85571bc7 | bellard | case 0x0b: /* mode */ |
227 | 27503323 | bellard | { |
228 | 16d17fdb | bellard | ichan = data & 3;
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229 | 16d17fdb | bellard | #ifdef DEBUG_DMA
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230 | 85571bc7 | bellard | { |
231 | 85571bc7 | bellard | int op, ai, dir, opmode;
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232 | e875c40a | bellard | op = (data >> 2) & 3; |
233 | e875c40a | bellard | ai = (data >> 4) & 1; |
234 | e875c40a | bellard | dir = (data >> 5) & 1; |
235 | e875c40a | bellard | opmode = (data >> 6) & 3; |
236 | 27503323 | bellard | |
237 | e875c40a | bellard | linfo ("ichan %d, op %d, ai %d, dir %d, opmode %d\n",
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238 | e875c40a | bellard | ichan, op, ai, dir, opmode); |
239 | 85571bc7 | bellard | } |
240 | 27503323 | bellard | #endif
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241 | 27503323 | bellard | d->regs[ichan].mode = data; |
242 | 27503323 | bellard | break;
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243 | 27503323 | bellard | } |
244 | 27503323 | bellard | |
245 | 85571bc7 | bellard | case 0x0c: /* clear flip flop */ |
246 | 27503323 | bellard | d->flip_flop = 0;
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247 | 27503323 | bellard | break;
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248 | 27503323 | bellard | |
249 | 85571bc7 | bellard | case 0x0d: /* reset */ |
250 | 27503323 | bellard | d->flip_flop = 0;
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251 | 27503323 | bellard | d->mask = ~0;
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252 | 27503323 | bellard | d->status = 0;
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253 | 27503323 | bellard | d->command = 0;
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254 | 27503323 | bellard | break;
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255 | 27503323 | bellard | |
256 | 85571bc7 | bellard | case 0x0e: /* clear mask for all channels */ |
257 | 27503323 | bellard | d->mask = 0;
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258 | 27503323 | bellard | break;
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259 | 27503323 | bellard | |
260 | 85571bc7 | bellard | case 0x0f: /* write mask for all channels */ |
261 | 27503323 | bellard | d->mask = data; |
262 | 27503323 | bellard | break;
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263 | 27503323 | bellard | |
264 | 27503323 | bellard | default:
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265 | 85571bc7 | bellard | dolog ("unknown iport %#x\n", iport);
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266 | df475d18 | bellard | break;
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267 | 27503323 | bellard | } |
268 | 27503323 | bellard | |
269 | 16d17fdb | bellard | #ifdef DEBUG_DMA
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270 | 27503323 | bellard | if (0xc != iport) { |
271 | 85571bc7 | bellard | linfo ("write_cont: nport %#06x, ichan % 2d, val %#06x\n",
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272 | 9eb153f1 | bellard | nport, ichan, data); |
273 | 27503323 | bellard | } |
274 | 27503323 | bellard | #endif
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275 | 27503323 | bellard | } |
276 | 27503323 | bellard | |
277 | 9eb153f1 | bellard | static uint32_t read_cont (void *opaque, uint32_t nport) |
278 | 9eb153f1 | bellard | { |
279 | 9eb153f1 | bellard | struct dma_cont *d = opaque;
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280 | 9eb153f1 | bellard | int iport, val;
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281 | 85571bc7 | bellard | |
282 | 9eb153f1 | bellard | iport = (nport >> d->dshift) & 0x0f;
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283 | 9eb153f1 | bellard | switch (iport) {
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284 | 85571bc7 | bellard | case 0x08: /* status */ |
285 | 9eb153f1 | bellard | val = d->status; |
286 | 9eb153f1 | bellard | d->status &= 0xf0;
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287 | 9eb153f1 | bellard | break;
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288 | 85571bc7 | bellard | case 0x0f: /* mask */ |
289 | 9eb153f1 | bellard | val = d->mask; |
290 | 9eb153f1 | bellard | break;
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291 | 9eb153f1 | bellard | default:
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292 | 9eb153f1 | bellard | val = 0;
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293 | 9eb153f1 | bellard | break;
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294 | 9eb153f1 | bellard | } |
295 | 85571bc7 | bellard | |
296 | 85571bc7 | bellard | ldebug ("read_cont: nport %#06x, iport %#04x val %#x\n", nport, iport, val);
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297 | 9eb153f1 | bellard | return val;
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298 | 9eb153f1 | bellard | } |
299 | 9eb153f1 | bellard | |
300 | 27503323 | bellard | int DMA_get_channel_mode (int nchan) |
301 | 27503323 | bellard | { |
302 | 27503323 | bellard | return dma_controllers[nchan > 3].regs[nchan & 3].mode; |
303 | 27503323 | bellard | } |
304 | 27503323 | bellard | |
305 | 27503323 | bellard | void DMA_hold_DREQ (int nchan) |
306 | 27503323 | bellard | { |
307 | 27503323 | bellard | int ncont, ichan;
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308 | 27503323 | bellard | |
309 | 27503323 | bellard | ncont = nchan > 3;
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310 | 27503323 | bellard | ichan = nchan & 3;
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311 | 27503323 | bellard | linfo ("held cont=%d chan=%d\n", ncont, ichan);
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312 | 27503323 | bellard | dma_controllers[ncont].status |= 1 << (ichan + 4); |
313 | 27503323 | bellard | } |
314 | 27503323 | bellard | |
315 | 27503323 | bellard | void DMA_release_DREQ (int nchan) |
316 | 27503323 | bellard | { |
317 | 27503323 | bellard | int ncont, ichan;
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318 | 27503323 | bellard | |
319 | 27503323 | bellard | ncont = nchan > 3;
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320 | 27503323 | bellard | ichan = nchan & 3;
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321 | 27503323 | bellard | linfo ("released cont=%d chan=%d\n", ncont, ichan);
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322 | 27503323 | bellard | dma_controllers[ncont].status &= ~(1 << (ichan + 4)); |
323 | 27503323 | bellard | } |
324 | 27503323 | bellard | |
325 | 27503323 | bellard | static void channel_run (int ncont, int ichan) |
326 | 27503323 | bellard | { |
327 | 27503323 | bellard | int n;
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328 | 85571bc7 | bellard | struct dma_regs *r = &dma_controllers[ncont].regs[ichan];
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329 | 85571bc7 | bellard | #ifdef DEBUG_DMA
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330 | 85571bc7 | bellard | int dir, opmode;
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331 | 27503323 | bellard | |
332 | 85571bc7 | bellard | dir = (r->mode >> 5) & 1; |
333 | 85571bc7 | bellard | opmode = (r->mode >> 6) & 3; |
334 | 27503323 | bellard | |
335 | 85571bc7 | bellard | if (dir) {
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336 | 85571bc7 | bellard | dolog ("DMA in address decrement mode\n");
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337 | 85571bc7 | bellard | } |
338 | 85571bc7 | bellard | if (opmode != 1) { |
339 | 85571bc7 | bellard | dolog ("DMA not in single mode select %#x\n", opmode);
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340 | 85571bc7 | bellard | } |
341 | 85571bc7 | bellard | #endif
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342 | 27503323 | bellard | |
343 | 85571bc7 | bellard | r = dma_controllers[ncont].regs + ichan; |
344 | 85571bc7 | bellard | n = r->transfer_handler (r->opaque, ichan + (ncont << 2),
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345 | 85571bc7 | bellard | r->now[COUNT], (r->base[COUNT] + 1) << ncont);
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346 | 85571bc7 | bellard | r->now[COUNT] = n; |
347 | 85571bc7 | bellard | ldebug ("dma_pos %d size %d\n", n, (r->base[COUNT] + 1) << ncont); |
348 | 27503323 | bellard | } |
349 | 27503323 | bellard | |
350 | 27503323 | bellard | void DMA_run (void) |
351 | 27503323 | bellard | { |
352 | 27503323 | bellard | struct dma_cont *d;
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353 | 27503323 | bellard | int icont, ichan;
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354 | 27503323 | bellard | |
355 | 27503323 | bellard | d = dma_controllers; |
356 | 27503323 | bellard | |
357 | 27503323 | bellard | for (icont = 0; icont < 2; icont++, d++) { |
358 | 27503323 | bellard | for (ichan = 0; ichan < 4; ichan++) { |
359 | 27503323 | bellard | int mask;
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360 | 27503323 | bellard | |
361 | 27503323 | bellard | mask = 1 << ichan;
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362 | 27503323 | bellard | |
363 | 27503323 | bellard | if ((0 == (d->mask & mask)) && (0 != (d->status & (mask << 4)))) |
364 | 27503323 | bellard | channel_run (icont, ichan); |
365 | 27503323 | bellard | } |
366 | 27503323 | bellard | } |
367 | 27503323 | bellard | } |
368 | 27503323 | bellard | |
369 | 27503323 | bellard | void DMA_register_channel (int nchan, |
370 | 85571bc7 | bellard | DMA_transfer_handler transfer_handler, |
371 | 16f62432 | bellard | void *opaque)
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372 | 27503323 | bellard | { |
373 | 27503323 | bellard | struct dma_regs *r;
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374 | 27503323 | bellard | int ichan, ncont;
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375 | 27503323 | bellard | |
376 | 27503323 | bellard | ncont = nchan > 3;
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377 | 27503323 | bellard | ichan = nchan & 3;
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378 | 27503323 | bellard | |
379 | 27503323 | bellard | r = dma_controllers[ncont].regs + ichan; |
380 | 16f62432 | bellard | r->transfer_handler = transfer_handler; |
381 | 16f62432 | bellard | r->opaque = opaque; |
382 | 16f62432 | bellard | } |
383 | 16f62432 | bellard | |
384 | 85571bc7 | bellard | int DMA_read_memory (int nchan, void *buf, int pos, int len) |
385 | 85571bc7 | bellard | { |
386 | 85571bc7 | bellard | struct dma_regs *r = &dma_controllers[nchan > 3].regs[nchan & 3]; |
387 | 71db710f | blueswir1 | target_phys_addr_t addr = ((r->pageh & 0x7f) << 24) | (r->page << 16) | r->now[ADDR]; |
388 | 85571bc7 | bellard | |
389 | 85571bc7 | bellard | if (r->mode & 0x20) { |
390 | 85571bc7 | bellard | int i;
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391 | 85571bc7 | bellard | uint8_t *p = buf; |
392 | 85571bc7 | bellard | |
393 | 85571bc7 | bellard | cpu_physical_memory_read (addr - pos - len, buf, len); |
394 | 85571bc7 | bellard | /* What about 16bit transfers? */
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395 | 85571bc7 | bellard | for (i = 0; i < len >> 1; i++) { |
396 | 85571bc7 | bellard | uint8_t b = p[len - i - 1];
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397 | 85571bc7 | bellard | p[i] = b; |
398 | 85571bc7 | bellard | } |
399 | 85571bc7 | bellard | } |
400 | 85571bc7 | bellard | else
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401 | 85571bc7 | bellard | cpu_physical_memory_read (addr + pos, buf, len); |
402 | 85571bc7 | bellard | |
403 | 85571bc7 | bellard | return len;
|
404 | 85571bc7 | bellard | } |
405 | 85571bc7 | bellard | |
406 | 85571bc7 | bellard | int DMA_write_memory (int nchan, void *buf, int pos, int len) |
407 | 85571bc7 | bellard | { |
408 | 85571bc7 | bellard | struct dma_regs *r = &dma_controllers[nchan > 3].regs[nchan & 3]; |
409 | 71db710f | blueswir1 | target_phys_addr_t addr = ((r->pageh & 0x7f) << 24) | (r->page << 16) | r->now[ADDR]; |
410 | 85571bc7 | bellard | |
411 | 85571bc7 | bellard | if (r->mode & 0x20) { |
412 | 85571bc7 | bellard | int i;
|
413 | 85571bc7 | bellard | uint8_t *p = buf; |
414 | 85571bc7 | bellard | |
415 | 85571bc7 | bellard | cpu_physical_memory_write (addr - pos - len, buf, len); |
416 | 85571bc7 | bellard | /* What about 16bit transfers? */
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417 | 85571bc7 | bellard | for (i = 0; i < len; i++) { |
418 | 85571bc7 | bellard | uint8_t b = p[len - i - 1];
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419 | 85571bc7 | bellard | p[i] = b; |
420 | 85571bc7 | bellard | } |
421 | 85571bc7 | bellard | } |
422 | 85571bc7 | bellard | else
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423 | 85571bc7 | bellard | cpu_physical_memory_write (addr + pos, buf, len); |
424 | 85571bc7 | bellard | |
425 | 85571bc7 | bellard | return len;
|
426 | 85571bc7 | bellard | } |
427 | 85571bc7 | bellard | |
428 | 16f62432 | bellard | /* request the emulator to transfer a new DMA memory block ASAP */
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429 | 16f62432 | bellard | void DMA_schedule(int nchan) |
430 | 16f62432 | bellard | { |
431 | c68ea704 | bellard | CPUState *env = cpu_single_env; |
432 | c68ea704 | bellard | if (env)
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433 | c68ea704 | bellard | cpu_interrupt(env, CPU_INTERRUPT_EXIT); |
434 | 27503323 | bellard | } |
435 | 27503323 | bellard | |
436 | d7d02e3c | bellard | static void dma_reset(void *opaque) |
437 | d7d02e3c | bellard | { |
438 | d7d02e3c | bellard | struct dma_cont *d = opaque;
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439 | d7d02e3c | bellard | write_cont (d, (0x0d << d->dshift), 0); |
440 | d7d02e3c | bellard | } |
441 | d7d02e3c | bellard | |
442 | ca9cc28c | balrog | static int dma_phony_handler (void *opaque, int nchan, int dma_pos, int dma_len) |
443 | ca9cc28c | balrog | { |
444 | ca9cc28c | balrog | dolog ("unregistered DMA channel used nchan=%d dma_pos=%d dma_len=%d\n",
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445 | ca9cc28c | balrog | nchan, dma_pos, dma_len); |
446 | ca9cc28c | balrog | return dma_pos;
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447 | ca9cc28c | balrog | } |
448 | ca9cc28c | balrog | |
449 | 9eb153f1 | bellard | /* dshift = 0: 8 bit DMA, 1 = 16 bit DMA */
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450 | 85571bc7 | bellard | static void dma_init2(struct dma_cont *d, int base, int dshift, |
451 | b0bda528 | bellard | int page_base, int pageh_base) |
452 | 27503323 | bellard | { |
453 | d70040bc | pbrook | static const int page_port_list[] = { 0x1, 0x2, 0x3, 0x7 }; |
454 | 27503323 | bellard | int i;
|
455 | 27503323 | bellard | |
456 | 9eb153f1 | bellard | d->dshift = dshift; |
457 | 27503323 | bellard | for (i = 0; i < 8; i++) { |
458 | 9eb153f1 | bellard | register_ioport_write (base + (i << dshift), 1, 1, write_chan, d); |
459 | 9eb153f1 | bellard | register_ioport_read (base + (i << dshift), 1, 1, read_chan, d); |
460 | 27503323 | bellard | } |
461 | 27503323 | bellard | for (i = 0; i < LENOFA (page_port_list); i++) { |
462 | 85571bc7 | bellard | register_ioport_write (page_base + page_port_list[i], 1, 1, |
463 | 9eb153f1 | bellard | write_page, d); |
464 | 85571bc7 | bellard | register_ioport_read (page_base + page_port_list[i], 1, 1, |
465 | 9eb153f1 | bellard | read_page, d); |
466 | b0bda528 | bellard | if (pageh_base >= 0) { |
467 | 85571bc7 | bellard | register_ioport_write (pageh_base + page_port_list[i], 1, 1, |
468 | b0bda528 | bellard | write_pageh, d); |
469 | 85571bc7 | bellard | register_ioport_read (pageh_base + page_port_list[i], 1, 1, |
470 | b0bda528 | bellard | read_pageh, d); |
471 | b0bda528 | bellard | } |
472 | 27503323 | bellard | } |
473 | 27503323 | bellard | for (i = 0; i < 8; i++) { |
474 | 85571bc7 | bellard | register_ioport_write (base + ((i + 8) << dshift), 1, 1, |
475 | 9eb153f1 | bellard | write_cont, d); |
476 | 85571bc7 | bellard | register_ioport_read (base + ((i + 8) << dshift), 1, 1, |
477 | 9eb153f1 | bellard | read_cont, d); |
478 | 27503323 | bellard | } |
479 | d7d02e3c | bellard | qemu_register_reset(dma_reset, d); |
480 | d7d02e3c | bellard | dma_reset(d); |
481 | ca9cc28c | balrog | for (i = 0; i < LENOFA (d->regs); ++i) { |
482 | ca9cc28c | balrog | d->regs[i].transfer_handler = dma_phony_handler; |
483 | ca9cc28c | balrog | } |
484 | 9eb153f1 | bellard | } |
485 | 27503323 | bellard | |
486 | 85571bc7 | bellard | static void dma_save (QEMUFile *f, void *opaque) |
487 | 85571bc7 | bellard | { |
488 | 85571bc7 | bellard | struct dma_cont *d = opaque;
|
489 | 85571bc7 | bellard | int i;
|
490 | 85571bc7 | bellard | |
491 | 85571bc7 | bellard | /* qemu_put_8s (f, &d->status); */
|
492 | 85571bc7 | bellard | qemu_put_8s (f, &d->command); |
493 | 85571bc7 | bellard | qemu_put_8s (f, &d->mask); |
494 | 85571bc7 | bellard | qemu_put_8s (f, &d->flip_flop); |
495 | bee8d684 | ths | qemu_put_be32 (f, d->dshift); |
496 | 85571bc7 | bellard | |
497 | 85571bc7 | bellard | for (i = 0; i < 4; ++i) { |
498 | 85571bc7 | bellard | struct dma_regs *r = &d->regs[i];
|
499 | bee8d684 | ths | qemu_put_be32 (f, r->now[0]);
|
500 | bee8d684 | ths | qemu_put_be32 (f, r->now[1]);
|
501 | 85571bc7 | bellard | qemu_put_be16s (f, &r->base[0]);
|
502 | 85571bc7 | bellard | qemu_put_be16s (f, &r->base[1]);
|
503 | 85571bc7 | bellard | qemu_put_8s (f, &r->mode); |
504 | 85571bc7 | bellard | qemu_put_8s (f, &r->page); |
505 | 85571bc7 | bellard | qemu_put_8s (f, &r->pageh); |
506 | 85571bc7 | bellard | qemu_put_8s (f, &r->dack); |
507 | 85571bc7 | bellard | qemu_put_8s (f, &r->eop); |
508 | 85571bc7 | bellard | } |
509 | 85571bc7 | bellard | } |
510 | 85571bc7 | bellard | |
511 | 85571bc7 | bellard | static int dma_load (QEMUFile *f, void *opaque, int version_id) |
512 | 85571bc7 | bellard | { |
513 | 85571bc7 | bellard | struct dma_cont *d = opaque;
|
514 | 85571bc7 | bellard | int i;
|
515 | 85571bc7 | bellard | |
516 | 85571bc7 | bellard | if (version_id != 1) |
517 | 85571bc7 | bellard | return -EINVAL;
|
518 | 85571bc7 | bellard | |
519 | 85571bc7 | bellard | /* qemu_get_8s (f, &d->status); */
|
520 | 85571bc7 | bellard | qemu_get_8s (f, &d->command); |
521 | 85571bc7 | bellard | qemu_get_8s (f, &d->mask); |
522 | 85571bc7 | bellard | qemu_get_8s (f, &d->flip_flop); |
523 | bee8d684 | ths | d->dshift=qemu_get_be32 (f); |
524 | 85571bc7 | bellard | |
525 | 85571bc7 | bellard | for (i = 0; i < 4; ++i) { |
526 | 85571bc7 | bellard | struct dma_regs *r = &d->regs[i];
|
527 | bee8d684 | ths | r->now[0]=qemu_get_be32 (f);
|
528 | bee8d684 | ths | r->now[1]=qemu_get_be32 (f);
|
529 | 85571bc7 | bellard | qemu_get_be16s (f, &r->base[0]);
|
530 | 85571bc7 | bellard | qemu_get_be16s (f, &r->base[1]);
|
531 | 85571bc7 | bellard | qemu_get_8s (f, &r->mode); |
532 | 85571bc7 | bellard | qemu_get_8s (f, &r->page); |
533 | 85571bc7 | bellard | qemu_get_8s (f, &r->pageh); |
534 | 85571bc7 | bellard | qemu_get_8s (f, &r->dack); |
535 | 85571bc7 | bellard | qemu_get_8s (f, &r->eop); |
536 | 85571bc7 | bellard | } |
537 | 85571bc7 | bellard | return 0; |
538 | 85571bc7 | bellard | } |
539 | 85571bc7 | bellard | |
540 | b0bda528 | bellard | void DMA_init (int high_page_enable) |
541 | 9eb153f1 | bellard | { |
542 | 85571bc7 | bellard | dma_init2(&dma_controllers[0], 0x00, 0, 0x80, |
543 | b0bda528 | bellard | high_page_enable ? 0x480 : -1); |
544 | b0bda528 | bellard | dma_init2(&dma_controllers[1], 0xc0, 1, 0x88, |
545 | b0bda528 | bellard | high_page_enable ? 0x488 : -1); |
546 | 85571bc7 | bellard | register_savevm ("dma", 0, 1, dma_save, dma_load, &dma_controllers[0]); |
547 | 85571bc7 | bellard | register_savevm ("dma", 1, 1, dma_save, dma_load, &dma_controllers[1]); |
548 | 27503323 | bellard | } |