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1 | 6515b203 | bellard | /*
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2 | 6515b203 | bellard | * ACPI implementation
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3 | 6515b203 | bellard | *
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4 | 6515b203 | bellard | * Copyright (c) 2006 Fabrice Bellard
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5 | 6515b203 | bellard | *
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6 | 6515b203 | bellard | * This library is free software; you can redistribute it and/or
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7 | 6515b203 | bellard | * modify it under the terms of the GNU Lesser General Public
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8 | 6515b203 | bellard | * License version 2 as published by the Free Software Foundation.
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9 | 6515b203 | bellard | *
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10 | 6515b203 | bellard | * This library is distributed in the hope that it will be useful,
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11 | 6515b203 | bellard | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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12 | 6515b203 | bellard | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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13 | 6515b203 | bellard | * Lesser General Public License for more details.
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14 | 6515b203 | bellard | *
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15 | 6515b203 | bellard | * You should have received a copy of the GNU Lesser General Public
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16 | 6515b203 | bellard | * License along with this library; if not, write to the Free Software
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17 | 6515b203 | bellard | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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18 | 6515b203 | bellard | */
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19 | 6515b203 | bellard | #include "vl.h" |
20 | 6515b203 | bellard | |
21 | 6515b203 | bellard | //#define DEBUG
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22 | 6515b203 | bellard | |
23 | 6515b203 | bellard | /* i82731AB (PIIX4) compatible power management function */
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24 | 6515b203 | bellard | #define PM_FREQ 3579545 |
25 | 6515b203 | bellard | |
26 | 6515b203 | bellard | #define ACPI_DBG_IO_ADDR 0xb044 |
27 | 6515b203 | bellard | |
28 | 6515b203 | bellard | typedef struct PIIX4PMState { |
29 | 6515b203 | bellard | PCIDevice dev; |
30 | 6515b203 | bellard | uint16_t pmsts; |
31 | 6515b203 | bellard | uint16_t pmen; |
32 | 6515b203 | bellard | uint16_t pmcntrl; |
33 | ab1e34ad | bellard | uint8_t apmc; |
34 | ab1e34ad | bellard | uint8_t apms; |
35 | 6515b203 | bellard | QEMUTimer *tmr_timer; |
36 | 6515b203 | bellard | int64_t tmr_overflow_time; |
37 | 6515b203 | bellard | } PIIX4PMState; |
38 | 6515b203 | bellard | |
39 | 6515b203 | bellard | #define RTC_EN (1 << 10) |
40 | 6515b203 | bellard | #define PWRBTN_EN (1 << 8) |
41 | 6515b203 | bellard | #define GBL_EN (1 << 5) |
42 | 6515b203 | bellard | #define TMROF_EN (1 << 0) |
43 | 6515b203 | bellard | |
44 | 6515b203 | bellard | #define SCI_EN (1 << 0) |
45 | 6515b203 | bellard | |
46 | 6515b203 | bellard | #define SUS_EN (1 << 13) |
47 | 6515b203 | bellard | |
48 | 6515b203 | bellard | static uint32_t get_pmtmr(PIIX4PMState *s)
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49 | 6515b203 | bellard | { |
50 | 6515b203 | bellard | uint32_t d; |
51 | 6515b203 | bellard | d = muldiv64(qemu_get_clock(vm_clock), PM_FREQ, ticks_per_sec); |
52 | 6515b203 | bellard | return d & 0xffffff; |
53 | 6515b203 | bellard | } |
54 | 6515b203 | bellard | |
55 | 6515b203 | bellard | static int get_pmsts(PIIX4PMState *s) |
56 | 6515b203 | bellard | { |
57 | 6515b203 | bellard | int64_t d; |
58 | 6515b203 | bellard | int pmsts;
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59 | 6515b203 | bellard | pmsts = s->pmsts; |
60 | 6515b203 | bellard | d = muldiv64(qemu_get_clock(vm_clock), PM_FREQ, ticks_per_sec); |
61 | 6515b203 | bellard | if (d >= s->tmr_overflow_time)
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62 | 6515b203 | bellard | s->pmsts |= TMROF_EN; |
63 | 6515b203 | bellard | return pmsts;
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64 | 6515b203 | bellard | } |
65 | 6515b203 | bellard | |
66 | 6515b203 | bellard | static void pm_update_sci(PIIX4PMState *s) |
67 | 6515b203 | bellard | { |
68 | 6515b203 | bellard | int sci_level, pmsts;
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69 | 6515b203 | bellard | int64_t expire_time; |
70 | 6515b203 | bellard | |
71 | 6515b203 | bellard | pmsts = get_pmsts(s); |
72 | 6515b203 | bellard | sci_level = (((pmsts & s->pmen) & |
73 | 6515b203 | bellard | (RTC_EN | PWRBTN_EN | GBL_EN | TMROF_EN)) != 0);
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74 | 6515b203 | bellard | pci_set_irq(&s->dev, 0, sci_level);
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75 | 6515b203 | bellard | /* schedule a timer interruption if needed */
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76 | 6515b203 | bellard | if ((s->pmen & TMROF_EN) && !(pmsts & TMROF_EN)) {
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77 | 6515b203 | bellard | expire_time = muldiv64(s->tmr_overflow_time, ticks_per_sec, PM_FREQ); |
78 | 6515b203 | bellard | qemu_mod_timer(s->tmr_timer, expire_time); |
79 | 6515b203 | bellard | } else {
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80 | 6515b203 | bellard | qemu_del_timer(s->tmr_timer); |
81 | 6515b203 | bellard | } |
82 | 6515b203 | bellard | } |
83 | 6515b203 | bellard | |
84 | 6515b203 | bellard | static void pm_tmr_timer(void *opaque) |
85 | 6515b203 | bellard | { |
86 | 6515b203 | bellard | PIIX4PMState *s = opaque; |
87 | 6515b203 | bellard | pm_update_sci(s); |
88 | 6515b203 | bellard | } |
89 | 6515b203 | bellard | |
90 | 6515b203 | bellard | static void pm_ioport_writew(void *opaque, uint32_t addr, uint32_t val) |
91 | 6515b203 | bellard | { |
92 | 6515b203 | bellard | PIIX4PMState *s = opaque; |
93 | 6515b203 | bellard | addr &= 0x3f;
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94 | 6515b203 | bellard | switch(addr) {
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95 | 6515b203 | bellard | case 0x00: |
96 | 6515b203 | bellard | { |
97 | 6515b203 | bellard | int64_t d; |
98 | 6515b203 | bellard | int pmsts;
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99 | 6515b203 | bellard | pmsts = get_pmsts(s); |
100 | 6515b203 | bellard | if (pmsts & val & TMROF_EN) {
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101 | 6515b203 | bellard | /* if TMRSTS is reset, then compute the new overflow time */
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102 | 6515b203 | bellard | d = muldiv64(qemu_get_clock(vm_clock), PM_FREQ, ticks_per_sec); |
103 | 6515b203 | bellard | s->tmr_overflow_time = (d + 0x800000LL) & ~0x7fffffLL; |
104 | 6515b203 | bellard | } |
105 | 6515b203 | bellard | s->pmsts &= ~val; |
106 | 6515b203 | bellard | pm_update_sci(s); |
107 | 6515b203 | bellard | } |
108 | 6515b203 | bellard | break;
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109 | 6515b203 | bellard | case 0x02: |
110 | 6515b203 | bellard | s->pmen = val; |
111 | 6515b203 | bellard | pm_update_sci(s); |
112 | 6515b203 | bellard | break;
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113 | 6515b203 | bellard | case 0x04: |
114 | 6515b203 | bellard | { |
115 | 6515b203 | bellard | int sus_typ;
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116 | 6515b203 | bellard | s->pmcntrl = val & ~(SUS_EN); |
117 | 6515b203 | bellard | if (val & SUS_EN) {
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118 | 6515b203 | bellard | /* change suspend type */
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119 | 6515b203 | bellard | sus_typ = (val >> 10) & 3; |
120 | 6515b203 | bellard | switch(sus_typ) {
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121 | 6515b203 | bellard | case 0: /* soft power off */ |
122 | 6515b203 | bellard | qemu_system_shutdown_request(); |
123 | 6515b203 | bellard | break;
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124 | 6515b203 | bellard | default:
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125 | 6515b203 | bellard | break;
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126 | 6515b203 | bellard | } |
127 | 6515b203 | bellard | } |
128 | 6515b203 | bellard | } |
129 | 6515b203 | bellard | break;
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130 | 6515b203 | bellard | default:
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131 | 6515b203 | bellard | break;
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132 | 6515b203 | bellard | } |
133 | 6515b203 | bellard | #ifdef DEBUG
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134 | 6515b203 | bellard | printf("PM writew port=0x%04x val=0x%04x\n", addr, val);
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135 | 6515b203 | bellard | #endif
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136 | 6515b203 | bellard | } |
137 | 6515b203 | bellard | |
138 | 6515b203 | bellard | static uint32_t pm_ioport_readw(void *opaque, uint32_t addr) |
139 | 6515b203 | bellard | { |
140 | 6515b203 | bellard | PIIX4PMState *s = opaque; |
141 | 6515b203 | bellard | uint32_t val; |
142 | 6515b203 | bellard | |
143 | 6515b203 | bellard | addr &= 0x3f;
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144 | 6515b203 | bellard | switch(addr) {
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145 | 6515b203 | bellard | case 0x00: |
146 | 6515b203 | bellard | val = get_pmsts(s); |
147 | 6515b203 | bellard | break;
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148 | 6515b203 | bellard | case 0x02: |
149 | 6515b203 | bellard | val = s->pmen; |
150 | 6515b203 | bellard | break;
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151 | 6515b203 | bellard | case 0x04: |
152 | 6515b203 | bellard | val = s->pmcntrl; |
153 | 6515b203 | bellard | break;
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154 | 6515b203 | bellard | default:
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155 | 6515b203 | bellard | val = 0;
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156 | 6515b203 | bellard | break;
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157 | 6515b203 | bellard | } |
158 | 6515b203 | bellard | #ifdef DEBUG
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159 | 6515b203 | bellard | printf("PM readw port=0x%04x val=0x%04x\n", addr, val);
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160 | 6515b203 | bellard | #endif
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161 | 6515b203 | bellard | return val;
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162 | 6515b203 | bellard | } |
163 | 6515b203 | bellard | |
164 | 6515b203 | bellard | static void pm_ioport_writel(void *opaque, uint32_t addr, uint32_t val) |
165 | 6515b203 | bellard | { |
166 | 6515b203 | bellard | // PIIX4PMState *s = opaque;
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167 | 6515b203 | bellard | addr &= 0x3f;
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168 | 6515b203 | bellard | #ifdef DEBUG
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169 | 6515b203 | bellard | printf("PM writel port=0x%04x val=0x%08x\n", addr, val);
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170 | 6515b203 | bellard | #endif
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171 | 6515b203 | bellard | } |
172 | 6515b203 | bellard | |
173 | 6515b203 | bellard | static uint32_t pm_ioport_readl(void *opaque, uint32_t addr) |
174 | 6515b203 | bellard | { |
175 | 6515b203 | bellard | PIIX4PMState *s = opaque; |
176 | 6515b203 | bellard | uint32_t val; |
177 | 6515b203 | bellard | |
178 | 6515b203 | bellard | addr &= 0x3f;
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179 | 6515b203 | bellard | switch(addr) {
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180 | 6515b203 | bellard | case 0x08: |
181 | 6515b203 | bellard | val = get_pmtmr(s); |
182 | 6515b203 | bellard | break;
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183 | 6515b203 | bellard | default:
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184 | 6515b203 | bellard | val = 0;
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185 | 6515b203 | bellard | break;
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186 | 6515b203 | bellard | } |
187 | 6515b203 | bellard | #ifdef DEBUG
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188 | 6515b203 | bellard | printf("PM readl port=0x%04x val=0x%08x\n", addr, val);
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189 | 6515b203 | bellard | #endif
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190 | 6515b203 | bellard | return val;
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191 | 6515b203 | bellard | } |
192 | 6515b203 | bellard | |
193 | ab1e34ad | bellard | static void pm_smi_writeb(void *opaque, uint32_t addr, uint32_t val) |
194 | 6515b203 | bellard | { |
195 | 6515b203 | bellard | PIIX4PMState *s = opaque; |
196 | ab1e34ad | bellard | addr &= 1;
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197 | 6515b203 | bellard | #ifdef DEBUG
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198 | ab1e34ad | bellard | printf("pm_smi_writeb addr=0x%x val=0x%02x\n", addr, val);
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199 | 6515b203 | bellard | #endif
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200 | ab1e34ad | bellard | if (addr == 0) { |
201 | ab1e34ad | bellard | s->apmc = val; |
202 | 47d02f6d | bellard | if (s->dev.config[0x5b] & (1 << 1)) { |
203 | 47d02f6d | bellard | cpu_interrupt(first_cpu, CPU_INTERRUPT_SMI); |
204 | ab1e34ad | bellard | } |
205 | ab1e34ad | bellard | } else {
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206 | ab1e34ad | bellard | s->apms = val; |
207 | 6515b203 | bellard | } |
208 | 6515b203 | bellard | } |
209 | 6515b203 | bellard | |
210 | ab1e34ad | bellard | static uint32_t pm_smi_readb(void *opaque, uint32_t addr) |
211 | ab1e34ad | bellard | { |
212 | ab1e34ad | bellard | PIIX4PMState *s = opaque; |
213 | ab1e34ad | bellard | uint32_t val; |
214 | ab1e34ad | bellard | |
215 | ab1e34ad | bellard | addr &= 1;
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216 | ab1e34ad | bellard | if (addr == 0) { |
217 | ab1e34ad | bellard | val = s->apmc; |
218 | ab1e34ad | bellard | } else {
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219 | ab1e34ad | bellard | val = s->apms; |
220 | ab1e34ad | bellard | } |
221 | ab1e34ad | bellard | #ifdef DEBUG
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222 | ab1e34ad | bellard | printf("pm_smi_readb addr=0x%x val=0x%02x\n", addr, val);
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223 | ab1e34ad | bellard | #endif
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224 | ab1e34ad | bellard | return val;
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225 | ab1e34ad | bellard | } |
226 | ab1e34ad | bellard | |
227 | 6515b203 | bellard | static void acpi_dbg_writel(void *opaque, uint32_t addr, uint32_t val) |
228 | 6515b203 | bellard | { |
229 | 6515b203 | bellard | #if defined(DEBUG)
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230 | 6515b203 | bellard | printf("ACPI: DBG: 0x%08x\n", val);
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231 | 6515b203 | bellard | #endif
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232 | 6515b203 | bellard | } |
233 | 6515b203 | bellard | |
234 | ab1e34ad | bellard | static void pm_io_space_update(PIIX4PMState *s) |
235 | ab1e34ad | bellard | { |
236 | ab1e34ad | bellard | uint32_t pm_io_base; |
237 | ab1e34ad | bellard | |
238 | ab1e34ad | bellard | if (s->dev.config[0x80] & 1) { |
239 | ab1e34ad | bellard | pm_io_base = le32_to_cpu(*(uint32_t *)(s->dev.config + 0x40));
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240 | ab1e34ad | bellard | pm_io_base &= 0xfffe;
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241 | ab1e34ad | bellard | |
242 | ab1e34ad | bellard | /* XXX: need to improve memory and ioport allocation */
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243 | ab1e34ad | bellard | #if defined(DEBUG)
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244 | ab1e34ad | bellard | printf("PM: mapping to 0x%x\n", pm_io_base);
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245 | ab1e34ad | bellard | #endif
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246 | ab1e34ad | bellard | register_ioport_write(pm_io_base, 64, 2, pm_ioport_writew, s); |
247 | ab1e34ad | bellard | register_ioport_read(pm_io_base, 64, 2, pm_ioport_readw, s); |
248 | ab1e34ad | bellard | register_ioport_write(pm_io_base, 64, 4, pm_ioport_writel, s); |
249 | ab1e34ad | bellard | register_ioport_read(pm_io_base, 64, 4, pm_ioport_readl, s); |
250 | ab1e34ad | bellard | } |
251 | ab1e34ad | bellard | } |
252 | ab1e34ad | bellard | |
253 | ab1e34ad | bellard | static void pm_write_config(PCIDevice *d, |
254 | ab1e34ad | bellard | uint32_t address, uint32_t val, int len)
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255 | ab1e34ad | bellard | { |
256 | ab1e34ad | bellard | pci_default_write_config(d, address, val, len); |
257 | ab1e34ad | bellard | if (address == 0x80) |
258 | ab1e34ad | bellard | pm_io_space_update((PIIX4PMState *)d); |
259 | ab1e34ad | bellard | } |
260 | ab1e34ad | bellard | |
261 | ab1e34ad | bellard | static void pm_save(QEMUFile* f,void *opaque) |
262 | ab1e34ad | bellard | { |
263 | ab1e34ad | bellard | PIIX4PMState *s = opaque; |
264 | ab1e34ad | bellard | |
265 | ab1e34ad | bellard | pci_device_save(&s->dev, f); |
266 | ab1e34ad | bellard | |
267 | ab1e34ad | bellard | qemu_put_be16s(f, &s->pmsts); |
268 | ab1e34ad | bellard | qemu_put_be16s(f, &s->pmen); |
269 | ab1e34ad | bellard | qemu_put_be16s(f, &s->pmcntrl); |
270 | ab1e34ad | bellard | qemu_put_8s(f, &s->apmc); |
271 | ab1e34ad | bellard | qemu_put_8s(f, &s->apms); |
272 | ab1e34ad | bellard | qemu_put_timer(f, s->tmr_timer); |
273 | ab1e34ad | bellard | qemu_put_be64s(f, &s->tmr_overflow_time); |
274 | ab1e34ad | bellard | } |
275 | ab1e34ad | bellard | |
276 | ab1e34ad | bellard | static int pm_load(QEMUFile* f,void* opaque,int version_id) |
277 | ab1e34ad | bellard | { |
278 | ab1e34ad | bellard | PIIX4PMState *s = opaque; |
279 | ab1e34ad | bellard | int ret;
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280 | ab1e34ad | bellard | |
281 | ab1e34ad | bellard | if (version_id > 1) |
282 | ab1e34ad | bellard | return -EINVAL;
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283 | ab1e34ad | bellard | |
284 | ab1e34ad | bellard | ret = pci_device_load(&s->dev, f); |
285 | ab1e34ad | bellard | if (ret < 0) |
286 | ab1e34ad | bellard | return ret;
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287 | ab1e34ad | bellard | |
288 | ab1e34ad | bellard | qemu_get_be16s(f, &s->pmsts); |
289 | ab1e34ad | bellard | qemu_get_be16s(f, &s->pmen); |
290 | ab1e34ad | bellard | qemu_get_be16s(f, &s->pmcntrl); |
291 | ab1e34ad | bellard | qemu_get_8s(f, &s->apmc); |
292 | ab1e34ad | bellard | qemu_get_8s(f, &s->apms); |
293 | ab1e34ad | bellard | qemu_get_timer(f, s->tmr_timer); |
294 | ab1e34ad | bellard | qemu_get_be64s(f, &s->tmr_overflow_time); |
295 | ab1e34ad | bellard | |
296 | ab1e34ad | bellard | pm_io_space_update(s); |
297 | ab1e34ad | bellard | |
298 | ab1e34ad | bellard | return 0; |
299 | ab1e34ad | bellard | } |
300 | ab1e34ad | bellard | |
301 | 502a5395 | pbrook | void piix4_pm_init(PCIBus *bus, int devfn) |
302 | 6515b203 | bellard | { |
303 | 6515b203 | bellard | PIIX4PMState *s; |
304 | 6515b203 | bellard | uint8_t *pci_conf; |
305 | 6515b203 | bellard | |
306 | 6515b203 | bellard | s = (PIIX4PMState *)pci_register_device(bus, |
307 | 6515b203 | bellard | "PM", sizeof(PIIX4PMState), |
308 | ab1e34ad | bellard | devfn, NULL, pm_write_config);
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309 | 6515b203 | bellard | pci_conf = s->dev.config; |
310 | 6515b203 | bellard | pci_conf[0x00] = 0x86; |
311 | 6515b203 | bellard | pci_conf[0x01] = 0x80; |
312 | 6515b203 | bellard | pci_conf[0x02] = 0x13; |
313 | 7ef4da1c | bellard | pci_conf[0x03] = 0x71; |
314 | 6515b203 | bellard | pci_conf[0x08] = 0x00; // revision number |
315 | 6515b203 | bellard | pci_conf[0x09] = 0x00; |
316 | 6515b203 | bellard | pci_conf[0x0a] = 0x80; // other bridge device |
317 | 6515b203 | bellard | pci_conf[0x0b] = 0x06; // bridge device |
318 | 6515b203 | bellard | pci_conf[0x0e] = 0x00; // header_type |
319 | 6515b203 | bellard | pci_conf[0x3d] = 0x01; // interrupt pin 1 |
320 | 6515b203 | bellard | |
321 | ab1e34ad | bellard | pci_conf[0x40] = 0x01; /* PM io base read only bit */ |
322 | 6515b203 | bellard | |
323 | ab1e34ad | bellard | register_ioport_write(0xb2, 2, 1, pm_smi_writeb, s); |
324 | ab1e34ad | bellard | register_ioport_read(0xb2, 2, 1, pm_smi_readb, s); |
325 | ab1e34ad | bellard | |
326 | 6515b203 | bellard | register_ioport_write(ACPI_DBG_IO_ADDR, 4, 4, acpi_dbg_writel, s); |
327 | 6515b203 | bellard | |
328 | 1ce549ab | bellard | /* XXX: which specification is used ? The i82731AB has different
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329 | 1ce549ab | bellard | mappings */
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330 | 1ce549ab | bellard | pci_conf[0x5f] = (parallel_hds[0] != NULL ? 0x80 : 0) | 0x10; |
331 | 1ce549ab | bellard | pci_conf[0x63] = 0x60; |
332 | 1ce549ab | bellard | pci_conf[0x67] = (serial_hds[0] != NULL ? 0x08 : 0) | |
333 | 1ce549ab | bellard | (serial_hds[1] != NULL ? 0x90 : 0); |
334 | 1ce549ab | bellard | |
335 | 6515b203 | bellard | s->tmr_timer = qemu_new_timer(vm_clock, pm_tmr_timer, s); |
336 | 6515b203 | bellard | |
337 | ab1e34ad | bellard | register_savevm("piix4_pm", 0, 1, pm_save, pm_load, s); |
338 | 6515b203 | bellard | } |