Revision a316d335 target-sparc/cpu.h
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int exception_index; |
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int interrupt_index; |
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int interrupt_request; |
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struct TranslationBlock *current_tb; |
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void *opaque; |
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/* NOTE: we allow 8 more registers to handle wrapping */ |
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target_ulong regbase[NWINDOWS * 16 + 8]; |
| 173 | 171 |
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/* in order to avoid passing too many arguments to the memory |
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write helpers, we store some rarely used information in the CPU |
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context) */ |
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unsigned long mem_write_pc; /* host pc at which the memory was |
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written */ |
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target_ulong mem_write_vaddr; /* target virtual addr at which the |
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memory was written */ |
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/* 0 = kernel, 1 = user (may have 2 = kernel code, 3 = user code ?) */ |
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CPUTLBEntry tlb_read[2][CPU_TLB_SIZE]; |
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CPUTLBEntry tlb_write[2][CPU_TLB_SIZE]; |
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CPU_COMMON |
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/* MMU regs */ |
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#if defined(TARGET_SPARC64) |
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uint64_t lsu; |
| ... | ... | |
| 222 | 212 |
#if !defined(TARGET_SPARC64) && !defined(reg_T2) |
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target_ulong t2; |
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#endif |
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/* ice debug support */ |
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target_ulong breakpoints[MAX_BREAKPOINTS]; |
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int nb_breakpoints; |
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int singlestep_enabled; /* XXX: should use CPU single step mode instead */ |
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} CPUSPARCState; |
| 232 | 216 |
#if defined(TARGET_SPARC64) |
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#define GET_FSR32(env) (env->fsr & 0xcfc1ffff) |
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