root / hw / etraxfs_timer.c @ a350e694
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1 | 83fa1010 | ths | /*
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2 | e62b5b13 | edgar_igl | * QEMU ETRAX Timers
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3 | 83fa1010 | ths | *
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4 | 83fa1010 | ths | * Copyright (c) 2007 Edgar E. Iglesias, Axis Communications AB.
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5 | 83fa1010 | ths | *
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6 | 83fa1010 | ths | * Permission is hereby granted, free of charge, to any person obtaining a copy
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7 | 83fa1010 | ths | * of this software and associated documentation files (the "Software"), to deal
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8 | 83fa1010 | ths | * in the Software without restriction, including without limitation the rights
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9 | 83fa1010 | ths | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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10 | 83fa1010 | ths | * copies of the Software, and to permit persons to whom the Software is
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11 | 83fa1010 | ths | * furnished to do so, subject to the following conditions:
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12 | 83fa1010 | ths | *
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13 | 83fa1010 | ths | * The above copyright notice and this permission notice shall be included in
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14 | 83fa1010 | ths | * all copies or substantial portions of the Software.
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15 | 83fa1010 | ths | *
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16 | 83fa1010 | ths | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 | 83fa1010 | ths | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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18 | 83fa1010 | ths | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 | 83fa1010 | ths | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 | 83fa1010 | ths | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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21 | 83fa1010 | ths | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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22 | 83fa1010 | ths | * THE SOFTWARE.
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23 | 83fa1010 | ths | */
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24 | 83fa1010 | ths | #include <stdio.h> |
25 | 83fa1010 | ths | #include <sys/time.h> |
26 | 87ecb68b | pbrook | #include "hw.h" |
27 | 87ecb68b | pbrook | #include "qemu-timer.h" |
28 | 83fa1010 | ths | |
29 | bbaf29c7 | edgar_igl | #define D(x)
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30 | bbaf29c7 | edgar_igl | |
31 | ca87d03b | edgar_igl | #define RW_TMR0_DIV 0x00 |
32 | ca87d03b | edgar_igl | #define R_TMR0_DATA 0x04 |
33 | ca87d03b | edgar_igl | #define RW_TMR0_CTRL 0x08 |
34 | ca87d03b | edgar_igl | #define RW_TMR1_DIV 0x10 |
35 | ca87d03b | edgar_igl | #define R_TMR1_DATA 0x14 |
36 | ca87d03b | edgar_igl | #define RW_TMR1_CTRL 0x18 |
37 | ca87d03b | edgar_igl | #define R_TIME 0x38 |
38 | ca87d03b | edgar_igl | #define RW_WD_CTRL 0x40 |
39 | ca87d03b | edgar_igl | #define RW_INTR_MASK 0x48 |
40 | ca87d03b | edgar_igl | #define RW_ACK_INTR 0x4c |
41 | ca87d03b | edgar_igl | #define R_INTR 0x50 |
42 | ca87d03b | edgar_igl | #define R_MASKED_INTR 0x54 |
43 | 83fa1010 | ths | |
44 | 83fa1010 | ths | struct fs_timer_t {
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45 | ca87d03b | edgar_igl | CPUState *env; |
46 | ca87d03b | edgar_igl | qemu_irq *irq; |
47 | ca87d03b | edgar_igl | target_phys_addr_t base; |
48 | ca87d03b | edgar_igl | |
49 | 83fa1010 | ths | QEMUBH *bh; |
50 | ca87d03b | edgar_igl | ptimer_state *ptimer; |
51 | bbaf29c7 | edgar_igl | struct timeval last;
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52 | e62b5b13 | edgar_igl | |
53 | 60237223 | edgar_igl | /* Control registers. */
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54 | 60237223 | edgar_igl | uint32_t rw_tmr0_div; |
55 | 60237223 | edgar_igl | uint32_t r_tmr0_data; |
56 | 60237223 | edgar_igl | uint32_t rw_tmr0_ctrl; |
57 | 60237223 | edgar_igl | |
58 | 60237223 | edgar_igl | uint32_t rw_tmr1_div; |
59 | 60237223 | edgar_igl | uint32_t r_tmr1_data; |
60 | 60237223 | edgar_igl | uint32_t rw_tmr1_ctrl; |
61 | 60237223 | edgar_igl | |
62 | e62b5b13 | edgar_igl | uint32_t rw_intr_mask; |
63 | e62b5b13 | edgar_igl | uint32_t rw_ack_intr; |
64 | e62b5b13 | edgar_igl | uint32_t r_intr; |
65 | 60237223 | edgar_igl | uint32_t r_masked_intr; |
66 | 83fa1010 | ths | }; |
67 | 83fa1010 | ths | |
68 | ca87d03b | edgar_igl | static uint32_t timer_rinvalid (void *opaque, target_phys_addr_t addr) |
69 | 83fa1010 | ths | { |
70 | ca87d03b | edgar_igl | struct fs_timer_t *t = opaque;
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71 | ca87d03b | edgar_igl | CPUState *env = t->env; |
72 | ca87d03b | edgar_igl | cpu_abort(env, "Unsupported short access. reg=%x pc=%x.\n",
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73 | ca87d03b | edgar_igl | addr, env->pc); |
74 | ca87d03b | edgar_igl | return 0; |
75 | 83fa1010 | ths | } |
76 | 83fa1010 | ths | |
77 | 83fa1010 | ths | static uint32_t timer_readl (void *opaque, target_phys_addr_t addr) |
78 | 83fa1010 | ths | { |
79 | ca87d03b | edgar_igl | struct fs_timer_t *t = opaque;
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80 | ca87d03b | edgar_igl | D(CPUState *env = t->env); |
81 | 83fa1010 | ths | uint32_t r = 0;
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82 | 83fa1010 | ths | |
83 | ca87d03b | edgar_igl | /* Make addr relative to this instances base. */
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84 | ca87d03b | edgar_igl | addr -= t->base; |
85 | 83fa1010 | ths | switch (addr) {
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86 | 83fa1010 | ths | case R_TMR0_DATA:
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87 | 83fa1010 | ths | break;
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88 | 83fa1010 | ths | case R_TMR1_DATA:
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89 | bbaf29c7 | edgar_igl | D(printf ("R_TMR1_DATA\n"));
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90 | 83fa1010 | ths | break;
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91 | 83fa1010 | ths | case R_TIME:
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92 | 60237223 | edgar_igl | r = qemu_get_clock(vm_clock) * 10;
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93 | 83fa1010 | ths | break;
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94 | 83fa1010 | ths | case RW_INTR_MASK:
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95 | ca87d03b | edgar_igl | r = t->rw_intr_mask; |
96 | 83fa1010 | ths | break;
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97 | 83fa1010 | ths | case R_MASKED_INTR:
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98 | ca87d03b | edgar_igl | r = t->r_intr & t->rw_intr_mask; |
99 | 83fa1010 | ths | break;
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100 | 83fa1010 | ths | default:
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101 | e62b5b13 | edgar_igl | D(printf ("%s %x p=%x\n", __func__, addr, env->pc));
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102 | 83fa1010 | ths | break;
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103 | 83fa1010 | ths | } |
104 | 83fa1010 | ths | return r;
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105 | 83fa1010 | ths | } |
106 | 83fa1010 | ths | |
107 | 83fa1010 | ths | static void |
108 | ca87d03b | edgar_igl | timer_winvalid (void *opaque, target_phys_addr_t addr, uint32_t value)
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109 | 83fa1010 | ths | { |
110 | ca87d03b | edgar_igl | struct fs_timer_t *t = opaque;
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111 | ca87d03b | edgar_igl | CPUState *env = t->env; |
112 | ca87d03b | edgar_igl | cpu_abort(env, "Unsupported short access. reg=%x pc=%x.\n",
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113 | ca87d03b | edgar_igl | addr, env->pc); |
114 | 83fa1010 | ths | } |
115 | 83fa1010 | ths | |
116 | f0b86b14 | edgar_igl | #define TIMER_SLOWDOWN 1 |
117 | 60237223 | edgar_igl | static void update_ctrl(struct fs_timer_t *t) |
118 | 83fa1010 | ths | { |
119 | 60237223 | edgar_igl | unsigned int op; |
120 | 60237223 | edgar_igl | unsigned int freq; |
121 | 60237223 | edgar_igl | unsigned int freq_hz; |
122 | 60237223 | edgar_igl | unsigned int div; |
123 | 83fa1010 | ths | |
124 | 60237223 | edgar_igl | op = t->rw_tmr0_ctrl & 3;
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125 | 60237223 | edgar_igl | freq = t->rw_tmr0_ctrl >> 2;
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126 | 83fa1010 | ths | freq_hz = 32000000;
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127 | 83fa1010 | ths | |
128 | 83fa1010 | ths | switch (freq)
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129 | 83fa1010 | ths | { |
130 | 83fa1010 | ths | case 0: |
131 | 83fa1010 | ths | case 1: |
132 | e62b5b13 | edgar_igl | D(printf ("extern or disabled timer clock?\n"));
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133 | 83fa1010 | ths | break;
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134 | 83fa1010 | ths | case 4: freq_hz = 29493000; break; |
135 | 83fa1010 | ths | case 5: freq_hz = 32000000; break; |
136 | 83fa1010 | ths | case 6: freq_hz = 32768000; break; |
137 | 83fa1010 | ths | case 7: freq_hz = 100000000; break; |
138 | 83fa1010 | ths | default:
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139 | 83fa1010 | ths | abort(); |
140 | 83fa1010 | ths | break;
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141 | 83fa1010 | ths | } |
142 | 83fa1010 | ths | |
143 | 60237223 | edgar_igl | D(printf ("freq_hz=%d div=%d\n", freq_hz, t->rw_tmr0_div));
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144 | 60237223 | edgar_igl | div = t->rw_tmr0_div * TIMER_SLOWDOWN; |
145 | 60237223 | edgar_igl | div >>= 15;
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146 | 60237223 | edgar_igl | freq_hz >>= 15;
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147 | 60237223 | edgar_igl | ptimer_set_freq(t->ptimer, freq_hz); |
148 | 60237223 | edgar_igl | ptimer_set_limit(t->ptimer, div, 0);
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149 | 83fa1010 | ths | |
150 | 83fa1010 | ths | switch (op)
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151 | 83fa1010 | ths | { |
152 | 83fa1010 | ths | case 0: |
153 | 60237223 | edgar_igl | /* Load. */
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154 | 60237223 | edgar_igl | ptimer_set_limit(t->ptimer, div, 1);
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155 | 60237223 | edgar_igl | ptimer_run(t->ptimer, 1);
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156 | 83fa1010 | ths | break;
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157 | 83fa1010 | ths | case 1: |
158 | 60237223 | edgar_igl | /* Hold. */
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159 | 83fa1010 | ths | ptimer_stop(t->ptimer); |
160 | 83fa1010 | ths | break;
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161 | 83fa1010 | ths | case 2: |
162 | 60237223 | edgar_igl | /* Run. */
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163 | 83fa1010 | ths | ptimer_run(t->ptimer, 0);
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164 | 83fa1010 | ths | break;
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165 | 83fa1010 | ths | default:
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166 | 83fa1010 | ths | abort(); |
167 | 83fa1010 | ths | break;
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168 | 83fa1010 | ths | } |
169 | 83fa1010 | ths | } |
170 | 83fa1010 | ths | |
171 | 60237223 | edgar_igl | static void timer_update_irq(struct fs_timer_t *t) |
172 | 83fa1010 | ths | { |
173 | 60237223 | edgar_igl | t->r_intr &= ~(t->rw_ack_intr); |
174 | 60237223 | edgar_igl | t->r_masked_intr = t->r_intr & t->rw_intr_mask; |
175 | 60237223 | edgar_igl | |
176 | 60237223 | edgar_igl | D(printf("%s: masked_intr=%x\n", __func__, t->r_masked_intr));
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177 | 60237223 | edgar_igl | if (t->r_masked_intr & 1) |
178 | 60237223 | edgar_igl | qemu_irq_raise(t->irq[0]);
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179 | 60237223 | edgar_igl | else
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180 | bbaf29c7 | edgar_igl | qemu_irq_lower(t->irq[0]);
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181 | 83fa1010 | ths | } |
182 | 83fa1010 | ths | |
183 | 63c1d925 | edgar_igl | static void timer_hit(void *opaque) |
184 | 60237223 | edgar_igl | { |
185 | 63c1d925 | edgar_igl | struct fs_timer_t *t = opaque;
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186 | 60237223 | edgar_igl | t->r_intr |= 1;
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187 | 60237223 | edgar_igl | timer_update_irq(t); |
188 | 60237223 | edgar_igl | } |
189 | 60237223 | edgar_igl | |
190 | 83fa1010 | ths | static void |
191 | 83fa1010 | ths | timer_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
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192 | 83fa1010 | ths | { |
193 | ca87d03b | edgar_igl | struct fs_timer_t *t = opaque;
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194 | ca87d03b | edgar_igl | CPUState *env = t->env; |
195 | bbaf29c7 | edgar_igl | |
196 | ca87d03b | edgar_igl | /* Make addr relative to this instances base. */
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197 | ca87d03b | edgar_igl | addr -= t->base; |
198 | 83fa1010 | ths | switch (addr)
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199 | 83fa1010 | ths | { |
200 | 83fa1010 | ths | case RW_TMR0_DIV:
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201 | 60237223 | edgar_igl | t->rw_tmr0_div = value; |
202 | 83fa1010 | ths | break;
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203 | 83fa1010 | ths | case RW_TMR0_CTRL:
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204 | bbaf29c7 | edgar_igl | D(printf ("RW_TMR0_CTRL=%x\n", value));
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205 | 60237223 | edgar_igl | t->rw_tmr0_ctrl = value; |
206 | 60237223 | edgar_igl | update_ctrl(t); |
207 | 83fa1010 | ths | break;
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208 | 83fa1010 | ths | case RW_TMR1_DIV:
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209 | 60237223 | edgar_igl | t->rw_tmr1_div = value; |
210 | 83fa1010 | ths | break;
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211 | 83fa1010 | ths | case RW_TMR1_CTRL:
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212 | bbaf29c7 | edgar_igl | D(printf ("RW_TMR1_CTRL=%x\n", value));
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213 | 83fa1010 | ths | break;
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214 | 83fa1010 | ths | case RW_INTR_MASK:
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215 | bbaf29c7 | edgar_igl | D(printf ("RW_INTR_MASK=%x\n", value));
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216 | ca87d03b | edgar_igl | t->rw_intr_mask = value; |
217 | 60237223 | edgar_igl | timer_update_irq(t); |
218 | e62b5b13 | edgar_igl | break;
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219 | e62b5b13 | edgar_igl | case RW_WD_CTRL:
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220 | e62b5b13 | edgar_igl | D(printf ("RW_WD_CTRL=%x\n", value));
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221 | 83fa1010 | ths | break;
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222 | 83fa1010 | ths | case RW_ACK_INTR:
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223 | 60237223 | edgar_igl | t->rw_ack_intr = value; |
224 | 60237223 | edgar_igl | timer_update_irq(t); |
225 | 60237223 | edgar_igl | t->rw_ack_intr = 0;
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226 | 83fa1010 | ths | break;
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227 | 83fa1010 | ths | default:
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228 | 83fa1010 | ths | printf ("%s %x %x pc=%x\n",
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229 | 83fa1010 | ths | __func__, addr, value, env->pc); |
230 | 83fa1010 | ths | break;
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231 | 83fa1010 | ths | } |
232 | 83fa1010 | ths | } |
233 | 83fa1010 | ths | |
234 | 83fa1010 | ths | static CPUReadMemoryFunc *timer_read[] = {
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235 | ca87d03b | edgar_igl | &timer_rinvalid, |
236 | ca87d03b | edgar_igl | &timer_rinvalid, |
237 | 83fa1010 | ths | &timer_readl, |
238 | 83fa1010 | ths | }; |
239 | 83fa1010 | ths | |
240 | 83fa1010 | ths | static CPUWriteMemoryFunc *timer_write[] = {
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241 | ca87d03b | edgar_igl | &timer_winvalid, |
242 | ca87d03b | edgar_igl | &timer_winvalid, |
243 | 83fa1010 | ths | &timer_writel, |
244 | 83fa1010 | ths | }; |
245 | 83fa1010 | ths | |
246 | ca87d03b | edgar_igl | void etraxfs_timer_init(CPUState *env, qemu_irq *irqs,
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247 | ca87d03b | edgar_igl | target_phys_addr_t base) |
248 | 83fa1010 | ths | { |
249 | ca87d03b | edgar_igl | static struct fs_timer_t *t; |
250 | 83fa1010 | ths | int timer_regs;
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251 | 83fa1010 | ths | |
252 | ca87d03b | edgar_igl | t = qemu_mallocz(sizeof *t);
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253 | ca87d03b | edgar_igl | if (!t)
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254 | ca87d03b | edgar_igl | return;
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255 | bbaf29c7 | edgar_igl | |
256 | 60237223 | edgar_igl | t->bh = qemu_bh_new(timer_hit, t); |
257 | ca87d03b | edgar_igl | t->ptimer = ptimer_init(t->bh); |
258 | 60237223 | edgar_igl | t->irq = irqs; |
259 | ca87d03b | edgar_igl | t->env = env; |
260 | ca87d03b | edgar_igl | t->base = base; |
261 | 83fa1010 | ths | |
262 | ca87d03b | edgar_igl | timer_regs = cpu_register_io_memory(0, timer_read, timer_write, t);
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263 | ca87d03b | edgar_igl | cpu_register_physical_memory (base, 0x5c, timer_regs);
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264 | 83fa1010 | ths | } |