root / hw / irq.h @ a350e694
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| 1 | 87ecb68b | pbrook | #ifndef QEMU_IRQ_H
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| 2 | 87ecb68b | pbrook | #define QEMU_IRQ_H
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| 3 | 87ecb68b | pbrook | |
| 4 | d537cf6c | pbrook | /* Generic IRQ/GPIO pin infrastructure. */
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| 5 | d537cf6c | pbrook | |
| 6 | 87ecb68b | pbrook | /* FIXME: Rmove one of these. */
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| 7 | d537cf6c | pbrook | typedef void (*qemu_irq_handler)(void *opaque, int n, int level); |
| 8 | 87ecb68b | pbrook | typedef void SetIRQFunc(void *opaque, int irq_num, int level); |
| 9 | d537cf6c | pbrook | |
| 10 | d537cf6c | pbrook | void qemu_set_irq(qemu_irq irq, int level); |
| 11 | d537cf6c | pbrook | |
| 12 | d537cf6c | pbrook | static inline void qemu_irq_raise(qemu_irq irq) |
| 13 | d537cf6c | pbrook | {
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| 14 | d537cf6c | pbrook | qemu_set_irq(irq, 1);
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| 15 | d537cf6c | pbrook | } |
| 16 | d537cf6c | pbrook | |
| 17 | d537cf6c | pbrook | static inline void qemu_irq_lower(qemu_irq irq) |
| 18 | d537cf6c | pbrook | {
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| 19 | d537cf6c | pbrook | qemu_set_irq(irq, 0);
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| 20 | d537cf6c | pbrook | } |
| 21 | d537cf6c | pbrook | |
| 22 | 106627d0 | balrog | static inline void qemu_irq_pulse(qemu_irq irq) |
| 23 | 106627d0 | balrog | {
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| 24 | 106627d0 | balrog | qemu_set_irq(irq, 1);
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| 25 | 106627d0 | balrog | qemu_set_irq(irq, 0);
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| 26 | 106627d0 | balrog | } |
| 27 | 106627d0 | balrog | |
| 28 | d537cf6c | pbrook | /* Returns an array of N IRQs. */
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| 29 | d537cf6c | pbrook | qemu_irq *qemu_allocate_irqs(qemu_irq_handler handler, void *opaque, int n); |
| 30 | d537cf6c | pbrook | |
| 31 | b50a6563 | balrog | /* Returns a new IRQ with opposite polarity. */
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| 32 | b50a6563 | balrog | qemu_irq qemu_irq_invert(qemu_irq irq); |
| 33 | 87ecb68b | pbrook | |
| 34 | 87ecb68b | pbrook | #endif |