root / opreg_template.h @ a37904dd
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1 | d691f669 | bellard | /*
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2 | d691f669 | bellard | * i386 micro operations (templates for various register related
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3 | d691f669 | bellard | * operations)
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4 | d691f669 | bellard | *
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5 | d691f669 | bellard | * Copyright (c) 2003 Fabrice Bellard
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6 | d691f669 | bellard | *
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7 | d691f669 | bellard | * This library is free software; you can redistribute it and/or
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8 | d691f669 | bellard | * modify it under the terms of the GNU Lesser General Public
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9 | d691f669 | bellard | * License as published by the Free Software Foundation; either
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10 | d691f669 | bellard | * version 2 of the License, or (at your option) any later version.
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11 | d691f669 | bellard | *
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12 | d691f669 | bellard | * This library is distributed in the hope that it will be useful,
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13 | d691f669 | bellard | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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14 | d691f669 | bellard | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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15 | d691f669 | bellard | * Lesser General Public License for more details.
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16 | d691f669 | bellard | *
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17 | d691f669 | bellard | * You should have received a copy of the GNU Lesser General Public
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18 | d691f669 | bellard | * License along with this library; if not, write to the Free Software
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19 | d691f669 | bellard | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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20 | d691f669 | bellard | */
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21 | 7bfdb6d1 | bellard | void OPPROTO glue(op_movl_A0,REGNAME)(void) |
22 | 7bfdb6d1 | bellard | { |
23 | 7bfdb6d1 | bellard | A0 = REG; |
24 | 7bfdb6d1 | bellard | } |
25 | 7bfdb6d1 | bellard | |
26 | 7bfdb6d1 | bellard | void OPPROTO glue(op_addl_A0,REGNAME)(void) |
27 | 7bfdb6d1 | bellard | { |
28 | 7bfdb6d1 | bellard | A0 += REG; |
29 | 7bfdb6d1 | bellard | } |
30 | 7bfdb6d1 | bellard | |
31 | 7bfdb6d1 | bellard | void OPPROTO glue(glue(op_addl_A0,REGNAME),_s1)(void) |
32 | 7bfdb6d1 | bellard | { |
33 | 7bfdb6d1 | bellard | A0 += REG << 1;
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34 | 7bfdb6d1 | bellard | } |
35 | 7bfdb6d1 | bellard | |
36 | 7bfdb6d1 | bellard | void OPPROTO glue(glue(op_addl_A0,REGNAME),_s2)(void) |
37 | 7bfdb6d1 | bellard | { |
38 | 7bfdb6d1 | bellard | A0 += REG << 2;
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39 | 7bfdb6d1 | bellard | } |
40 | 7bfdb6d1 | bellard | |
41 | 7bfdb6d1 | bellard | void OPPROTO glue(glue(op_addl_A0,REGNAME),_s3)(void) |
42 | 7bfdb6d1 | bellard | { |
43 | 7bfdb6d1 | bellard | A0 += REG << 3;
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44 | 7bfdb6d1 | bellard | } |
45 | 7bfdb6d1 | bellard | |
46 | 7bfdb6d1 | bellard | void OPPROTO glue(op_movl_T0,REGNAME)(void) |
47 | 7bfdb6d1 | bellard | { |
48 | 7bfdb6d1 | bellard | T0 = REG; |
49 | 7bfdb6d1 | bellard | } |
50 | 7bfdb6d1 | bellard | |
51 | 7bfdb6d1 | bellard | void OPPROTO glue(op_movl_T1,REGNAME)(void) |
52 | 7bfdb6d1 | bellard | { |
53 | 7bfdb6d1 | bellard | T1 = REG; |
54 | 7bfdb6d1 | bellard | } |
55 | 7bfdb6d1 | bellard | |
56 | 7bfdb6d1 | bellard | void OPPROTO glue(op_movh_T0,REGNAME)(void) |
57 | 7bfdb6d1 | bellard | { |
58 | 7bfdb6d1 | bellard | T0 = REG >> 8;
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59 | 7bfdb6d1 | bellard | } |
60 | 7bfdb6d1 | bellard | |
61 | 7bfdb6d1 | bellard | void OPPROTO glue(op_movh_T1,REGNAME)(void) |
62 | 7bfdb6d1 | bellard | { |
63 | 7bfdb6d1 | bellard | T1 = REG >> 8;
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64 | 7bfdb6d1 | bellard | } |
65 | 7bfdb6d1 | bellard | |
66 | 7bfdb6d1 | bellard | void OPPROTO glue(glue(op_movl,REGNAME),_T0)(void) |
67 | 7bfdb6d1 | bellard | { |
68 | 7bfdb6d1 | bellard | REG = T0; |
69 | 7bfdb6d1 | bellard | } |
70 | 7bfdb6d1 | bellard | |
71 | 7bfdb6d1 | bellard | void OPPROTO glue(glue(op_movl,REGNAME),_T1)(void) |
72 | 7bfdb6d1 | bellard | { |
73 | 7bfdb6d1 | bellard | REG = T1; |
74 | 7bfdb6d1 | bellard | } |
75 | 7bfdb6d1 | bellard | |
76 | 7bfdb6d1 | bellard | void OPPROTO glue(glue(op_movl,REGNAME),_A0)(void) |
77 | 7bfdb6d1 | bellard | { |
78 | 7bfdb6d1 | bellard | REG = A0; |
79 | 5dd9488c | bellard | } |
80 | 5dd9488c | bellard | |
81 | 5dd9488c | bellard | /* mov T1 to REG if T0 is true */
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82 | 5dd9488c | bellard | void OPPROTO glue(glue(op_cmovw,REGNAME),_T1_T0)(void) |
83 | 5dd9488c | bellard | { |
84 | 5dd9488c | bellard | if (T0)
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85 | 5dd9488c | bellard | REG = (REG & 0xffff0000) | (T1 & 0xffff); |
86 | 5dd9488c | bellard | } |
87 | 5dd9488c | bellard | |
88 | 5dd9488c | bellard | void OPPROTO glue(glue(op_cmovl,REGNAME),_T1_T0)(void) |
89 | 5dd9488c | bellard | { |
90 | 5dd9488c | bellard | if (T0)
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91 | 5dd9488c | bellard | REG = T1; |
92 | 7bfdb6d1 | bellard | } |
93 | 7bfdb6d1 | bellard | |
94 | 7bfdb6d1 | bellard | /* NOTE: T0 high order bits are ignored */
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95 | 7bfdb6d1 | bellard | void OPPROTO glue(glue(op_movw,REGNAME),_T0)(void) |
96 | 7bfdb6d1 | bellard | { |
97 | 7bfdb6d1 | bellard | REG = (REG & 0xffff0000) | (T0 & 0xffff); |
98 | 7bfdb6d1 | bellard | } |
99 | 7bfdb6d1 | bellard | |
100 | 7bfdb6d1 | bellard | /* NOTE: T0 high order bits are ignored */
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101 | 7bfdb6d1 | bellard | void OPPROTO glue(glue(op_movw,REGNAME),_T1)(void) |
102 | 7bfdb6d1 | bellard | { |
103 | 7bfdb6d1 | bellard | REG = (REG & 0xffff0000) | (T1 & 0xffff); |
104 | 7bfdb6d1 | bellard | } |
105 | 7bfdb6d1 | bellard | |
106 | 7bfdb6d1 | bellard | /* NOTE: A0 high order bits are ignored */
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107 | 7bfdb6d1 | bellard | void OPPROTO glue(glue(op_movw,REGNAME),_A0)(void) |
108 | 7bfdb6d1 | bellard | { |
109 | 7bfdb6d1 | bellard | REG = (REG & 0xffff0000) | (A0 & 0xffff); |
110 | 7bfdb6d1 | bellard | } |
111 | 7bfdb6d1 | bellard | |
112 | 7bfdb6d1 | bellard | /* NOTE: T0 high order bits are ignored */
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113 | 7bfdb6d1 | bellard | void OPPROTO glue(glue(op_movb,REGNAME),_T0)(void) |
114 | 7bfdb6d1 | bellard | { |
115 | 7bfdb6d1 | bellard | REG = (REG & 0xffffff00) | (T0 & 0xff); |
116 | 7bfdb6d1 | bellard | } |
117 | 7bfdb6d1 | bellard | |
118 | 7bfdb6d1 | bellard | /* NOTE: T0 high order bits are ignored */
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119 | 7bfdb6d1 | bellard | void OPPROTO glue(glue(op_movh,REGNAME),_T0)(void) |
120 | 7bfdb6d1 | bellard | { |
121 | 7bfdb6d1 | bellard | REG = (REG & 0xffff00ff) | ((T0 & 0xff) << 8); |
122 | 7bfdb6d1 | bellard | } |
123 | 7bfdb6d1 | bellard | |
124 | 7bfdb6d1 | bellard | /* NOTE: T1 high order bits are ignored */
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125 | 7bfdb6d1 | bellard | void OPPROTO glue(glue(op_movb,REGNAME),_T1)(void) |
126 | 7bfdb6d1 | bellard | { |
127 | 7bfdb6d1 | bellard | REG = (REG & 0xffffff00) | (T1 & 0xff); |
128 | 7bfdb6d1 | bellard | } |
129 | 7bfdb6d1 | bellard | |
130 | 7bfdb6d1 | bellard | /* NOTE: T1 high order bits are ignored */
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131 | 7bfdb6d1 | bellard | void OPPROTO glue(glue(op_movh,REGNAME),_T1)(void) |
132 | 7bfdb6d1 | bellard | { |
133 | 7bfdb6d1 | bellard | REG = (REG & 0xffff00ff) | ((T1 & 0xff) << 8); |
134 | 7bfdb6d1 | bellard | } |