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/*
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 *  i386 translation
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 * 
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 *  Copyright (c) 2003 Fabrice Bellard
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 *
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 * This library is free software; you can redistribute it and/or
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 * modify it under the terms of the GNU Lesser General Public
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 * License as published by the Free Software Foundation; either
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 * version 2 of the License, or (at your option) any later version.
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 *
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 * This library is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
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 * Lesser General Public License for more details.
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 *
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 * You should have received a copy of the GNU Lesser General Public
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 * License along with this library; if not, write to the Free Software
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 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
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 */
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#include <stdarg.h>
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#include <stdlib.h>
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#include <stdio.h>
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#include <string.h>
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#include <inttypes.h>
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#include <signal.h>
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#include <assert.h>
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#include "disas.h"
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#define DEBUG_DISAS
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#define IN_OP_I386
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#include "cpu-i386.h"
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#include "exec.h"
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/* XXX: move that elsewhere */
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static uint16_t *gen_opc_ptr;
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static uint32_t *gen_opparam_ptr;
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int __op_param1, __op_param2, __op_param3;
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#ifdef USE_DIRECT_JUMP
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int __op_jmp0, __op_jmp1;
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#endif
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#ifdef __i386__
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static inline void flush_icache_range(unsigned long start, unsigned long stop)
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{
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}
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#endif
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#ifdef __s390__
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static inline void flush_icache_range(unsigned long start, unsigned long stop)
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{
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}
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#endif
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#ifdef __ia64__
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static inline void flush_icache_range(unsigned long start, unsigned long stop)
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{
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}
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#endif
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#ifdef __powerpc__
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#define MIN_CACHE_LINE_SIZE 8 /* conservative value */
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static void inline flush_icache_range(unsigned long start, unsigned long stop)
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{
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    unsigned long p;
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    p = start & ~(MIN_CACHE_LINE_SIZE - 1);
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    stop = (stop + MIN_CACHE_LINE_SIZE - 1) & ~(MIN_CACHE_LINE_SIZE - 1);
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    for (p = start; p < stop; p += MIN_CACHE_LINE_SIZE) {
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        asm volatile ("dcbst 0,%0" : : "r"(p) : "memory");
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    }
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    asm volatile ("sync" : : : "memory");
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    for (p = start; p < stop; p += MIN_CACHE_LINE_SIZE) {
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        asm volatile ("icbi 0,%0" : : "r"(p) : "memory");
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    }
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    asm volatile ("sync" : : : "memory");
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    asm volatile ("isync" : : : "memory");
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}
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#endif
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#ifdef __alpha__
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static inline void flush_icache_range(unsigned long start, unsigned long stop)
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{
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    asm ("imb");
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}
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#endif
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#ifdef __sparc__
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static void inline flush_icache_range(unsigned long start, unsigned long stop)
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{
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        unsigned long p;
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        p = start & ~(8UL - 1UL);
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        stop = (stop + (8UL - 1UL)) & ~(8UL - 1UL);
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        for (; p < stop; p += 8)
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                __asm__ __volatile__("flush\t%0" : : "r" (p));
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}
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#endif
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extern FILE *logfile;
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extern int loglevel;
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#define PREFIX_REPZ   0x01
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#define PREFIX_REPNZ  0x02
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#define PREFIX_LOCK   0x04
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#define PREFIX_DATA   0x08
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#define PREFIX_ADR    0x10
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typedef struct DisasContext {
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    /* current insn context */
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    int override; /* -1 if no override */
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    int prefix;
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    int aflag, dflag;
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    uint8_t *pc; /* pc = eip + cs_base */
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    int is_jmp; /* 1 = means jump (stop translation), 2 means CPU
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                   static state change (stop translation) */
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    /* current block context */
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    uint8_t *cs_base; /* base of CS segment */
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    int code32; /* 32 bit code segment */
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    int ss32;   /* 32 bit stack segment */
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    int cc_op;  /* current CC operation */
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    int addseg; /* non zero if either DS/ES/SS have a non zero base */
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    int f_st;   /* currently unused */
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    int vm86;   /* vm86 mode */
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    int cpl;
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    int iopl;
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    int tf;     /* TF cpu flag */
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    TranslationBlock *tb;
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} DisasContext;
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/* i386 arith/logic operations */
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enum {
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    OP_ADDL, 
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    OP_ORL, 
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    OP_ADCL, 
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    OP_SBBL,
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    OP_ANDL, 
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    OP_SUBL, 
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    OP_XORL, 
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    OP_CMPL,
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};
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/* i386 shift ops */
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enum {
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    OP_ROL, 
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    OP_ROR, 
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    OP_RCL, 
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    OP_RCR, 
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    OP_SHL, 
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    OP_SHR, 
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    OP_SHL1, /* undocumented */
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    OP_SAR = 7,
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};
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enum {
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#define DEF(s, n) INDEX_op_ ## s,
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#include "opc-i386.h"
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#undef DEF
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    NB_OPS,
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};
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#include "op-i386.h"
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/* operand size */
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enum {
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    OT_BYTE = 0,
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    OT_WORD,
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    OT_LONG, 
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    OT_QUAD,
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};
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enum {
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    /* I386 int registers */
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    OR_EAX,   /* MUST be even numbered */
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    OR_ECX,
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    OR_EDX,
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    OR_EBX,
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    OR_ESP,
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    OR_EBP,
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    OR_ESI,
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    OR_EDI,
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    OR_TMP0,    /* temporary operand register */
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    OR_TMP1,
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    OR_A0, /* temporary register used when doing address evaluation */
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    OR_ZERO, /* fixed zero register */
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    NB_OREGS,
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};
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typedef void (GenOpFunc)(void);
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typedef void (GenOpFunc1)(long);
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typedef void (GenOpFunc2)(long, long);
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typedef void (GenOpFunc3)(long, long, long);
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static GenOpFunc *gen_op_mov_reg_T0[3][8] = {
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    [OT_BYTE] = {
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        gen_op_movb_EAX_T0,
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        gen_op_movb_ECX_T0,
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        gen_op_movb_EDX_T0,
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        gen_op_movb_EBX_T0,
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        gen_op_movh_EAX_T0,
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        gen_op_movh_ECX_T0,
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        gen_op_movh_EDX_T0,
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        gen_op_movh_EBX_T0,
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    },
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    [OT_WORD] = {
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        gen_op_movw_EAX_T0,
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        gen_op_movw_ECX_T0,
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        gen_op_movw_EDX_T0,
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        gen_op_movw_EBX_T0,
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        gen_op_movw_ESP_T0,
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        gen_op_movw_EBP_T0,
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        gen_op_movw_ESI_T0,
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        gen_op_movw_EDI_T0,
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    },
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    [OT_LONG] = {
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        gen_op_movl_EAX_T0,
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        gen_op_movl_ECX_T0,
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        gen_op_movl_EDX_T0,
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        gen_op_movl_EBX_T0,
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        gen_op_movl_ESP_T0,
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        gen_op_movl_EBP_T0,
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        gen_op_movl_ESI_T0,
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        gen_op_movl_EDI_T0,
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    },
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};
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static GenOpFunc *gen_op_mov_reg_T1[3][8] = {
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    [OT_BYTE] = {
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        gen_op_movb_EAX_T1,
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        gen_op_movb_ECX_T1,
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        gen_op_movb_EDX_T1,
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        gen_op_movb_EBX_T1,
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        gen_op_movh_EAX_T1,
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        gen_op_movh_ECX_T1,
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        gen_op_movh_EDX_T1,
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        gen_op_movh_EBX_T1,
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    },
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    [OT_WORD] = {
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        gen_op_movw_EAX_T1,
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        gen_op_movw_ECX_T1,
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        gen_op_movw_EDX_T1,
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        gen_op_movw_EBX_T1,
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        gen_op_movw_ESP_T1,
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        gen_op_movw_EBP_T1,
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        gen_op_movw_ESI_T1,
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        gen_op_movw_EDI_T1,
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    },
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    [OT_LONG] = {
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        gen_op_movl_EAX_T1,
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        gen_op_movl_ECX_T1,
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        gen_op_movl_EDX_T1,
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        gen_op_movl_EBX_T1,
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        gen_op_movl_ESP_T1,
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        gen_op_movl_EBP_T1,
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        gen_op_movl_ESI_T1,
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        gen_op_movl_EDI_T1,
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    },
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};
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static GenOpFunc *gen_op_mov_reg_A0[2][8] = {
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    [0] = {
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        gen_op_movw_EAX_A0,
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        gen_op_movw_ECX_A0,
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        gen_op_movw_EDX_A0,
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        gen_op_movw_EBX_A0,
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        gen_op_movw_ESP_A0,
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        gen_op_movw_EBP_A0,
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        gen_op_movw_ESI_A0,
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        gen_op_movw_EDI_A0,
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    },
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    [1] = {
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        gen_op_movl_EAX_A0,
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        gen_op_movl_ECX_A0,
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        gen_op_movl_EDX_A0,
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        gen_op_movl_EBX_A0,
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        gen_op_movl_ESP_A0,
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        gen_op_movl_EBP_A0,
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        gen_op_movl_ESI_A0,
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        gen_op_movl_EDI_A0,
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    },
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};
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static GenOpFunc *gen_op_mov_TN_reg[3][2][8] = 
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{
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    [OT_BYTE] = {
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        {
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            gen_op_movl_T0_EAX,
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            gen_op_movl_T0_ECX,
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            gen_op_movl_T0_EDX,
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            gen_op_movl_T0_EBX,
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            gen_op_movh_T0_EAX,
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            gen_op_movh_T0_ECX,
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            gen_op_movh_T0_EDX,
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            gen_op_movh_T0_EBX,
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        },
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        {
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            gen_op_movl_T1_EAX,
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            gen_op_movl_T1_ECX,
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            gen_op_movl_T1_EDX,
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            gen_op_movl_T1_EBX,
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            gen_op_movh_T1_EAX,
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            gen_op_movh_T1_ECX,
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            gen_op_movh_T1_EDX,
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            gen_op_movh_T1_EBX,
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        },
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    },
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    [OT_WORD] = {
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        {
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            gen_op_movl_T0_EAX,
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            gen_op_movl_T0_ECX,
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            gen_op_movl_T0_EDX,
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            gen_op_movl_T0_EBX,
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            gen_op_movl_T0_ESP,
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            gen_op_movl_T0_EBP,
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            gen_op_movl_T0_ESI,
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            gen_op_movl_T0_EDI,
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        },
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        {
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            gen_op_movl_T1_EAX,
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            gen_op_movl_T1_ECX,
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            gen_op_movl_T1_EDX,
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            gen_op_movl_T1_EBX,
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            gen_op_movl_T1_ESP,
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            gen_op_movl_T1_EBP,
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            gen_op_movl_T1_ESI,
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            gen_op_movl_T1_EDI,
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        },
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    },
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    [OT_LONG] = {
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        {
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            gen_op_movl_T0_EAX,
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            gen_op_movl_T0_ECX,
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            gen_op_movl_T0_EDX,
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            gen_op_movl_T0_EBX,
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            gen_op_movl_T0_ESP,
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            gen_op_movl_T0_EBP,
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            gen_op_movl_T0_ESI,
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            gen_op_movl_T0_EDI,
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        },
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        {
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            gen_op_movl_T1_EAX,
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            gen_op_movl_T1_ECX,
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            gen_op_movl_T1_EDX,
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            gen_op_movl_T1_EBX,
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            gen_op_movl_T1_ESP,
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            gen_op_movl_T1_EBP,
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            gen_op_movl_T1_ESI,
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            gen_op_movl_T1_EDI,
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        },
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    },
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};
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static GenOpFunc *gen_op_movl_A0_reg[8] = {
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    gen_op_movl_A0_EAX,
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    gen_op_movl_A0_ECX,
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    gen_op_movl_A0_EDX,
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    gen_op_movl_A0_EBX,
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    gen_op_movl_A0_ESP,
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    gen_op_movl_A0_EBP,
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    gen_op_movl_A0_ESI,
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    gen_op_movl_A0_EDI,
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};
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static GenOpFunc *gen_op_addl_A0_reg_sN[4][8] = {
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    [0] = {
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        gen_op_addl_A0_EAX,
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        gen_op_addl_A0_ECX,
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        gen_op_addl_A0_EDX,
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        gen_op_addl_A0_EBX,
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        gen_op_addl_A0_ESP,
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        gen_op_addl_A0_EBP,
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        gen_op_addl_A0_ESI,
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        gen_op_addl_A0_EDI,
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    },
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    [1] = {
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        gen_op_addl_A0_EAX_s1,
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        gen_op_addl_A0_ECX_s1,
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        gen_op_addl_A0_EDX_s1,
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        gen_op_addl_A0_EBX_s1,
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        gen_op_addl_A0_ESP_s1,
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        gen_op_addl_A0_EBP_s1,
389 367e86e8 bellard
        gen_op_addl_A0_ESI_s1,
390 367e86e8 bellard
        gen_op_addl_A0_EDI_s1,
391 367e86e8 bellard
    },
392 367e86e8 bellard
    [2] = {
393 367e86e8 bellard
        gen_op_addl_A0_EAX_s2,
394 367e86e8 bellard
        gen_op_addl_A0_ECX_s2,
395 367e86e8 bellard
        gen_op_addl_A0_EDX_s2,
396 367e86e8 bellard
        gen_op_addl_A0_EBX_s2,
397 367e86e8 bellard
        gen_op_addl_A0_ESP_s2,
398 367e86e8 bellard
        gen_op_addl_A0_EBP_s2,
399 367e86e8 bellard
        gen_op_addl_A0_ESI_s2,
400 367e86e8 bellard
        gen_op_addl_A0_EDI_s2,
401 367e86e8 bellard
    },
402 367e86e8 bellard
    [3] = {
403 367e86e8 bellard
        gen_op_addl_A0_EAX_s3,
404 367e86e8 bellard
        gen_op_addl_A0_ECX_s3,
405 367e86e8 bellard
        gen_op_addl_A0_EDX_s3,
406 367e86e8 bellard
        gen_op_addl_A0_EBX_s3,
407 367e86e8 bellard
        gen_op_addl_A0_ESP_s3,
408 367e86e8 bellard
        gen_op_addl_A0_EBP_s3,
409 367e86e8 bellard
        gen_op_addl_A0_ESI_s3,
410 367e86e8 bellard
        gen_op_addl_A0_EDI_s3,
411 367e86e8 bellard
    },
412 367e86e8 bellard
};
413 367e86e8 bellard
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static GenOpFunc *gen_op_cmov_reg_T1_T0[2][8] = {
415 5dd9488c bellard
    [0] = {
416 5dd9488c bellard
        gen_op_cmovw_EAX_T1_T0,
417 5dd9488c bellard
        gen_op_cmovw_ECX_T1_T0,
418 5dd9488c bellard
        gen_op_cmovw_EDX_T1_T0,
419 5dd9488c bellard
        gen_op_cmovw_EBX_T1_T0,
420 5dd9488c bellard
        gen_op_cmovw_ESP_T1_T0,
421 5dd9488c bellard
        gen_op_cmovw_EBP_T1_T0,
422 5dd9488c bellard
        gen_op_cmovw_ESI_T1_T0,
423 5dd9488c bellard
        gen_op_cmovw_EDI_T1_T0,
424 5dd9488c bellard
    },
425 5dd9488c bellard
    [1] = {
426 5dd9488c bellard
        gen_op_cmovl_EAX_T1_T0,
427 5dd9488c bellard
        gen_op_cmovl_ECX_T1_T0,
428 5dd9488c bellard
        gen_op_cmovl_EDX_T1_T0,
429 5dd9488c bellard
        gen_op_cmovl_EBX_T1_T0,
430 5dd9488c bellard
        gen_op_cmovl_ESP_T1_T0,
431 5dd9488c bellard
        gen_op_cmovl_EBP_T1_T0,
432 5dd9488c bellard
        gen_op_cmovl_ESI_T1_T0,
433 5dd9488c bellard
        gen_op_cmovl_EDI_T1_T0,
434 5dd9488c bellard
    },
435 5dd9488c bellard
};
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static GenOpFunc *gen_op_arith_T0_T1_cc[8] = {
438 367e86e8 bellard
    gen_op_addl_T0_T1_cc,
439 367e86e8 bellard
    gen_op_orl_T0_T1_cc,
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    NULL,
441 4b74fe1f bellard
    NULL,
442 367e86e8 bellard
    gen_op_andl_T0_T1_cc,
443 367e86e8 bellard
    gen_op_subl_T0_T1_cc,
444 367e86e8 bellard
    gen_op_xorl_T0_T1_cc,
445 367e86e8 bellard
    gen_op_cmpl_T0_T1_cc,
446 367e86e8 bellard
};
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static GenOpFunc *gen_op_arithc_T0_T1_cc[3][2] = {
449 4b74fe1f bellard
    [OT_BYTE] = {
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        gen_op_adcb_T0_T1_cc,
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        gen_op_sbbb_T0_T1_cc,
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    },
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    [OT_WORD] = {
454 4b74fe1f bellard
        gen_op_adcw_T0_T1_cc,
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        gen_op_sbbw_T0_T1_cc,
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    },
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    [OT_LONG] = {
458 4b74fe1f bellard
        gen_op_adcl_T0_T1_cc,
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        gen_op_sbbl_T0_T1_cc,
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    },
461 4b74fe1f bellard
};
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static const int cc_op_arithb[8] = {
464 367e86e8 bellard
    CC_OP_ADDB,
465 367e86e8 bellard
    CC_OP_LOGICB,
466 367e86e8 bellard
    CC_OP_ADDB,
467 367e86e8 bellard
    CC_OP_SUBB,
468 367e86e8 bellard
    CC_OP_LOGICB,
469 367e86e8 bellard
    CC_OP_SUBB,
470 367e86e8 bellard
    CC_OP_LOGICB,
471 367e86e8 bellard
    CC_OP_SUBB,
472 367e86e8 bellard
};
473 367e86e8 bellard
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static GenOpFunc *gen_op_cmpxchg_T0_T1_EAX_cc[3] = {
475 1a9353d2 bellard
    gen_op_cmpxchgb_T0_T1_EAX_cc,
476 1a9353d2 bellard
    gen_op_cmpxchgw_T0_T1_EAX_cc,
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    gen_op_cmpxchgl_T0_T1_EAX_cc,
478 1a9353d2 bellard
};
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480 367e86e8 bellard
static GenOpFunc *gen_op_shift_T0_T1_cc[3][8] = {
481 367e86e8 bellard
    [OT_BYTE] = {
482 367e86e8 bellard
        gen_op_rolb_T0_T1_cc,
483 367e86e8 bellard
        gen_op_rorb_T0_T1_cc,
484 367e86e8 bellard
        gen_op_rclb_T0_T1_cc,
485 367e86e8 bellard
        gen_op_rcrb_T0_T1_cc,
486 367e86e8 bellard
        gen_op_shlb_T0_T1_cc,
487 367e86e8 bellard
        gen_op_shrb_T0_T1_cc,
488 367e86e8 bellard
        gen_op_shlb_T0_T1_cc,
489 367e86e8 bellard
        gen_op_sarb_T0_T1_cc,
490 367e86e8 bellard
    },
491 367e86e8 bellard
    [OT_WORD] = {
492 367e86e8 bellard
        gen_op_rolw_T0_T1_cc,
493 367e86e8 bellard
        gen_op_rorw_T0_T1_cc,
494 367e86e8 bellard
        gen_op_rclw_T0_T1_cc,
495 367e86e8 bellard
        gen_op_rcrw_T0_T1_cc,
496 367e86e8 bellard
        gen_op_shlw_T0_T1_cc,
497 367e86e8 bellard
        gen_op_shrw_T0_T1_cc,
498 367e86e8 bellard
        gen_op_shlw_T0_T1_cc,
499 367e86e8 bellard
        gen_op_sarw_T0_T1_cc,
500 367e86e8 bellard
    },
501 367e86e8 bellard
    [OT_LONG] = {
502 367e86e8 bellard
        gen_op_roll_T0_T1_cc,
503 367e86e8 bellard
        gen_op_rorl_T0_T1_cc,
504 367e86e8 bellard
        gen_op_rcll_T0_T1_cc,
505 367e86e8 bellard
        gen_op_rcrl_T0_T1_cc,
506 367e86e8 bellard
        gen_op_shll_T0_T1_cc,
507 367e86e8 bellard
        gen_op_shrl_T0_T1_cc,
508 367e86e8 bellard
        gen_op_shll_T0_T1_cc,
509 367e86e8 bellard
        gen_op_sarl_T0_T1_cc,
510 367e86e8 bellard
    },
511 367e86e8 bellard
};
512 367e86e8 bellard
513 d57c4e01 bellard
static GenOpFunc1 *gen_op_shiftd_T0_T1_im_cc[2][2] = {
514 d57c4e01 bellard
    [0] = {
515 d57c4e01 bellard
        gen_op_shldw_T0_T1_im_cc,
516 d57c4e01 bellard
        gen_op_shrdw_T0_T1_im_cc,
517 d57c4e01 bellard
    },
518 d57c4e01 bellard
    [1] = {
519 d57c4e01 bellard
        gen_op_shldl_T0_T1_im_cc,
520 d57c4e01 bellard
        gen_op_shrdl_T0_T1_im_cc,
521 d57c4e01 bellard
    },
522 d57c4e01 bellard
};
523 d57c4e01 bellard
524 d57c4e01 bellard
static GenOpFunc *gen_op_shiftd_T0_T1_ECX_cc[2][2] = {
525 d57c4e01 bellard
    [0] = {
526 d57c4e01 bellard
        gen_op_shldw_T0_T1_ECX_cc,
527 d57c4e01 bellard
        gen_op_shrdw_T0_T1_ECX_cc,
528 d57c4e01 bellard
    },
529 d57c4e01 bellard
    [1] = {
530 d57c4e01 bellard
        gen_op_shldl_T0_T1_ECX_cc,
531 d57c4e01 bellard
        gen_op_shrdl_T0_T1_ECX_cc,
532 d57c4e01 bellard
    },
533 d57c4e01 bellard
};
534 d57c4e01 bellard
535 4b74fe1f bellard
static GenOpFunc *gen_op_btx_T0_T1_cc[2][4] = {
536 4b74fe1f bellard
    [0] = {
537 4b74fe1f bellard
        gen_op_btw_T0_T1_cc,
538 4b74fe1f bellard
        gen_op_btsw_T0_T1_cc,
539 4b74fe1f bellard
        gen_op_btrw_T0_T1_cc,
540 4b74fe1f bellard
        gen_op_btcw_T0_T1_cc,
541 4b74fe1f bellard
    },
542 4b74fe1f bellard
    [1] = {
543 4b74fe1f bellard
        gen_op_btl_T0_T1_cc,
544 4b74fe1f bellard
        gen_op_btsl_T0_T1_cc,
545 4b74fe1f bellard
        gen_op_btrl_T0_T1_cc,
546 4b74fe1f bellard
        gen_op_btcl_T0_T1_cc,
547 4b74fe1f bellard
    },
548 4b74fe1f bellard
};
549 4b74fe1f bellard
550 77f8dd5a bellard
static GenOpFunc *gen_op_bsx_T0_cc[2][2] = {
551 77f8dd5a bellard
    [0] = {
552 77f8dd5a bellard
        gen_op_bsfw_T0_cc,
553 77f8dd5a bellard
        gen_op_bsrw_T0_cc,
554 77f8dd5a bellard
    },
555 77f8dd5a bellard
    [1] = {
556 77f8dd5a bellard
        gen_op_bsfl_T0_cc,
557 77f8dd5a bellard
        gen_op_bsrl_T0_cc,
558 77f8dd5a bellard
    },
559 77f8dd5a bellard
};
560 77f8dd5a bellard
561 367e86e8 bellard
static GenOpFunc *gen_op_lds_T0_A0[3] = {
562 367e86e8 bellard
    gen_op_ldsb_T0_A0,
563 367e86e8 bellard
    gen_op_ldsw_T0_A0,
564 367e86e8 bellard
};
565 367e86e8 bellard
566 367e86e8 bellard
static GenOpFunc *gen_op_ldu_T0_A0[3] = {
567 367e86e8 bellard
    gen_op_ldub_T0_A0,
568 367e86e8 bellard
    gen_op_lduw_T0_A0,
569 367e86e8 bellard
};
570 367e86e8 bellard
571 367e86e8 bellard
/* sign does not matter */
572 367e86e8 bellard
static GenOpFunc *gen_op_ld_T0_A0[3] = {
573 367e86e8 bellard
    gen_op_ldub_T0_A0,
574 367e86e8 bellard
    gen_op_lduw_T0_A0,
575 367e86e8 bellard
    gen_op_ldl_T0_A0,
576 367e86e8 bellard
};
577 367e86e8 bellard
578 367e86e8 bellard
static GenOpFunc *gen_op_ld_T1_A0[3] = {
579 367e86e8 bellard
    gen_op_ldub_T1_A0,
580 367e86e8 bellard
    gen_op_lduw_T1_A0,
581 367e86e8 bellard
    gen_op_ldl_T1_A0,
582 367e86e8 bellard
};
583 367e86e8 bellard
584 367e86e8 bellard
static GenOpFunc *gen_op_st_T0_A0[3] = {
585 367e86e8 bellard
    gen_op_stb_T0_A0,
586 367e86e8 bellard
    gen_op_stw_T0_A0,
587 367e86e8 bellard
    gen_op_stl_T0_A0,
588 367e86e8 bellard
};
589 367e86e8 bellard
590 9c605cb1 bellard
/* the _a32 and _a16 string operations use A0 as the base register. */
591 9c605cb1 bellard
592 9c605cb1 bellard
#define STRINGOP(x) \
593 9c605cb1 bellard
    gen_op_ ## x ## b_fast, \
594 9c605cb1 bellard
    gen_op_ ## x ## w_fast, \
595 9c605cb1 bellard
    gen_op_ ## x ## l_fast, \
596 9c605cb1 bellard
    gen_op_ ## x ## b_a32, \
597 9c605cb1 bellard
    gen_op_ ## x ## w_a32, \
598 9c605cb1 bellard
    gen_op_ ## x ## l_a32, \
599 9c605cb1 bellard
    gen_op_ ## x ## b_a16, \
600 9c605cb1 bellard
    gen_op_ ## x ## w_a16, \
601 9c605cb1 bellard
    gen_op_ ## x ## l_a16,
602 9c605cb1 bellard
     
603 9c605cb1 bellard
static GenOpFunc *gen_op_movs[9 * 2] = {
604 9c605cb1 bellard
    STRINGOP(movs)
605 9c605cb1 bellard
    STRINGOP(rep_movs)
606 367e86e8 bellard
};
607 367e86e8 bellard
608 9c605cb1 bellard
static GenOpFunc *gen_op_stos[9 * 2] = {
609 9c605cb1 bellard
    STRINGOP(stos)
610 9c605cb1 bellard
    STRINGOP(rep_stos)
611 367e86e8 bellard
};
612 367e86e8 bellard
613 9c605cb1 bellard
static GenOpFunc *gen_op_lods[9 * 2] = {
614 9c605cb1 bellard
    STRINGOP(lods)
615 9c605cb1 bellard
    STRINGOP(rep_lods)
616 367e86e8 bellard
};
617 367e86e8 bellard
618 9c605cb1 bellard
static GenOpFunc *gen_op_scas[9 * 3] = {
619 9c605cb1 bellard
    STRINGOP(scas)
620 9c605cb1 bellard
    STRINGOP(repz_scas)
621 9c605cb1 bellard
    STRINGOP(repnz_scas)
622 367e86e8 bellard
};
623 367e86e8 bellard
624 9c605cb1 bellard
static GenOpFunc *gen_op_cmps[9 * 3] = {
625 9c605cb1 bellard
    STRINGOP(cmps)
626 9c605cb1 bellard
    STRINGOP(repz_cmps)
627 9c605cb1 bellard
    STRINGOP(repnz_cmps)
628 367e86e8 bellard
};
629 367e86e8 bellard
630 9c605cb1 bellard
static GenOpFunc *gen_op_ins[9 * 2] = {
631 9c605cb1 bellard
    STRINGOP(ins)
632 9c605cb1 bellard
    STRINGOP(rep_ins)
633 367e86e8 bellard
};
634 367e86e8 bellard
635 367e86e8 bellard
636 9c605cb1 bellard
static GenOpFunc *gen_op_outs[9 * 2] = {
637 9c605cb1 bellard
    STRINGOP(outs)
638 9c605cb1 bellard
    STRINGOP(rep_outs)
639 367e86e8 bellard
};
640 367e86e8 bellard
641 9c605cb1 bellard
642 9c605cb1 bellard
static inline void gen_string_ds(DisasContext *s, int ot, GenOpFunc **func)
643 9c605cb1 bellard
{
644 9c605cb1 bellard
    int index, override;
645 9c605cb1 bellard
646 9c605cb1 bellard
    override = s->override;
647 9c605cb1 bellard
    if (s->aflag) {
648 9c605cb1 bellard
        /* 32 bit address */
649 9c605cb1 bellard
        if (s->addseg && override < 0)
650 9c605cb1 bellard
            override = R_DS;
651 9c605cb1 bellard
        if (override >= 0) {
652 9c605cb1 bellard
            gen_op_movl_A0_seg(offsetof(CPUX86State,seg_cache[override].base));
653 9c605cb1 bellard
            index = 3 + ot;
654 9c605cb1 bellard
        } else {
655 9c605cb1 bellard
            index = ot;
656 9c605cb1 bellard
        }
657 9c605cb1 bellard
    } else {
658 9c605cb1 bellard
        if (override < 0)
659 9c605cb1 bellard
            override = R_DS;
660 9c605cb1 bellard
        gen_op_movl_A0_seg(offsetof(CPUX86State,seg_cache[override].base));
661 9c605cb1 bellard
        /* 16 address, always override */
662 9c605cb1 bellard
        index = 6 + ot;
663 9c605cb1 bellard
    }
664 9c605cb1 bellard
    func[index]();
665 9c605cb1 bellard
}
666 9c605cb1 bellard
667 9c605cb1 bellard
static inline void gen_string_es(DisasContext *s, int ot, GenOpFunc **func)
668 9c605cb1 bellard
{
669 9c605cb1 bellard
    int index;
670 9c605cb1 bellard
            
671 9c605cb1 bellard
    if (s->aflag) {
672 9c605cb1 bellard
        if (s->addseg) {
673 9c605cb1 bellard
            index = 3 + ot;
674 9c605cb1 bellard
        } else {
675 9c605cb1 bellard
            index = ot;
676 9c605cb1 bellard
        }
677 9c605cb1 bellard
    } else {
678 9c605cb1 bellard
        index = 6 + ot;
679 9c605cb1 bellard
    }
680 9c605cb1 bellard
    func[index]();
681 9c605cb1 bellard
}
682 9c605cb1 bellard
683 9c605cb1 bellard
684 ba1c6e37 bellard
static GenOpFunc *gen_op_in[3] = {
685 ba1c6e37 bellard
    gen_op_inb_T0_T1,
686 ba1c6e37 bellard
    gen_op_inw_T0_T1,
687 ba1c6e37 bellard
    gen_op_inl_T0_T1,
688 ba1c6e37 bellard
};
689 ba1c6e37 bellard
690 ba1c6e37 bellard
static GenOpFunc *gen_op_out[3] = {
691 ba1c6e37 bellard
    gen_op_outb_T0_T1,
692 ba1c6e37 bellard
    gen_op_outw_T0_T1,
693 ba1c6e37 bellard
    gen_op_outl_T0_T1,
694 ba1c6e37 bellard
};
695 ba1c6e37 bellard
696 367e86e8 bellard
enum {
697 367e86e8 bellard
    JCC_O,
698 367e86e8 bellard
    JCC_B,
699 367e86e8 bellard
    JCC_Z,
700 367e86e8 bellard
    JCC_BE,
701 367e86e8 bellard
    JCC_S,
702 367e86e8 bellard
    JCC_P,
703 367e86e8 bellard
    JCC_L,
704 367e86e8 bellard
    JCC_LE,
705 367e86e8 bellard
};
706 367e86e8 bellard
707 d4e8164f bellard
static GenOpFunc3 *gen_jcc_sub[3][8] = {
708 367e86e8 bellard
    [OT_BYTE] = {
709 367e86e8 bellard
        NULL,
710 367e86e8 bellard
        gen_op_jb_subb,
711 367e86e8 bellard
        gen_op_jz_subb,
712 367e86e8 bellard
        gen_op_jbe_subb,
713 367e86e8 bellard
        gen_op_js_subb,
714 367e86e8 bellard
        NULL,
715 367e86e8 bellard
        gen_op_jl_subb,
716 367e86e8 bellard
        gen_op_jle_subb,
717 367e86e8 bellard
    },
718 367e86e8 bellard
    [OT_WORD] = {
719 367e86e8 bellard
        NULL,
720 367e86e8 bellard
        gen_op_jb_subw,
721 367e86e8 bellard
        gen_op_jz_subw,
722 367e86e8 bellard
        gen_op_jbe_subw,
723 367e86e8 bellard
        gen_op_js_subw,
724 367e86e8 bellard
        NULL,
725 367e86e8 bellard
        gen_op_jl_subw,
726 367e86e8 bellard
        gen_op_jle_subw,
727 367e86e8 bellard
    },
728 367e86e8 bellard
    [OT_LONG] = {
729 367e86e8 bellard
        NULL,
730 367e86e8 bellard
        gen_op_jb_subl,
731 367e86e8 bellard
        gen_op_jz_subl,
732 367e86e8 bellard
        gen_op_jbe_subl,
733 367e86e8 bellard
        gen_op_js_subl,
734 367e86e8 bellard
        NULL,
735 367e86e8 bellard
        gen_op_jl_subl,
736 367e86e8 bellard
        gen_op_jle_subl,
737 367e86e8 bellard
    },
738 367e86e8 bellard
};
739 1a9353d2 bellard
static GenOpFunc2 *gen_op_loop[2][4] = {
740 1a9353d2 bellard
    [0] = {
741 1a9353d2 bellard
        gen_op_loopnzw,
742 1a9353d2 bellard
        gen_op_loopzw,
743 1a9353d2 bellard
        gen_op_loopw,
744 1a9353d2 bellard
        gen_op_jecxzw,
745 1a9353d2 bellard
    },
746 1a9353d2 bellard
    [1] = {
747 1a9353d2 bellard
        gen_op_loopnzl,
748 1a9353d2 bellard
        gen_op_loopzl,
749 1a9353d2 bellard
        gen_op_loopl,
750 1a9353d2 bellard
        gen_op_jecxzl,
751 1a9353d2 bellard
    },
752 1a9353d2 bellard
};
753 367e86e8 bellard
754 367e86e8 bellard
static GenOpFunc *gen_setcc_slow[8] = {
755 367e86e8 bellard
    gen_op_seto_T0_cc,
756 367e86e8 bellard
    gen_op_setb_T0_cc,
757 367e86e8 bellard
    gen_op_setz_T0_cc,
758 367e86e8 bellard
    gen_op_setbe_T0_cc,
759 367e86e8 bellard
    gen_op_sets_T0_cc,
760 367e86e8 bellard
    gen_op_setp_T0_cc,
761 367e86e8 bellard
    gen_op_setl_T0_cc,
762 367e86e8 bellard
    gen_op_setle_T0_cc,
763 367e86e8 bellard
};
764 367e86e8 bellard
765 367e86e8 bellard
static GenOpFunc *gen_setcc_sub[3][8] = {
766 367e86e8 bellard
    [OT_BYTE] = {
767 367e86e8 bellard
        NULL,
768 367e86e8 bellard
        gen_op_setb_T0_subb,
769 367e86e8 bellard
        gen_op_setz_T0_subb,
770 367e86e8 bellard
        gen_op_setbe_T0_subb,
771 367e86e8 bellard
        gen_op_sets_T0_subb,
772 367e86e8 bellard
        NULL,
773 367e86e8 bellard
        gen_op_setl_T0_subb,
774 367e86e8 bellard
        gen_op_setle_T0_subb,
775 367e86e8 bellard
    },
776 367e86e8 bellard
    [OT_WORD] = {
777 367e86e8 bellard
        NULL,
778 367e86e8 bellard
        gen_op_setb_T0_subw,
779 367e86e8 bellard
        gen_op_setz_T0_subw,
780 367e86e8 bellard
        gen_op_setbe_T0_subw,
781 367e86e8 bellard
        gen_op_sets_T0_subw,
782 367e86e8 bellard
        NULL,
783 367e86e8 bellard
        gen_op_setl_T0_subw,
784 367e86e8 bellard
        gen_op_setle_T0_subw,
785 367e86e8 bellard
    },
786 367e86e8 bellard
    [OT_LONG] = {
787 367e86e8 bellard
        NULL,
788 367e86e8 bellard
        gen_op_setb_T0_subl,
789 367e86e8 bellard
        gen_op_setz_T0_subl,
790 367e86e8 bellard
        gen_op_setbe_T0_subl,
791 367e86e8 bellard
        gen_op_sets_T0_subl,
792 367e86e8 bellard
        NULL,
793 367e86e8 bellard
        gen_op_setl_T0_subl,
794 367e86e8 bellard
        gen_op_setle_T0_subl,
795 367e86e8 bellard
    },
796 367e86e8 bellard
};
797 367e86e8 bellard
798 927f621e bellard
static GenOpFunc *gen_op_fp_arith_ST0_FT0[8] = {
799 927f621e bellard
    gen_op_fadd_ST0_FT0,
800 927f621e bellard
    gen_op_fmul_ST0_FT0,
801 927f621e bellard
    gen_op_fcom_ST0_FT0,
802 927f621e bellard
    gen_op_fcom_ST0_FT0,
803 927f621e bellard
    gen_op_fsub_ST0_FT0,
804 927f621e bellard
    gen_op_fsubr_ST0_FT0,
805 927f621e bellard
    gen_op_fdiv_ST0_FT0,
806 927f621e bellard
    gen_op_fdivr_ST0_FT0,
807 927f621e bellard
};
808 927f621e bellard
809 77f8dd5a bellard
/* NOTE the exception in "r" op ordering */
810 927f621e bellard
static GenOpFunc1 *gen_op_fp_arith_STN_ST0[8] = {
811 927f621e bellard
    gen_op_fadd_STN_ST0,
812 927f621e bellard
    gen_op_fmul_STN_ST0,
813 927f621e bellard
    NULL,
814 927f621e bellard
    NULL,
815 927f621e bellard
    gen_op_fsubr_STN_ST0,
816 77f8dd5a bellard
    gen_op_fsub_STN_ST0,
817 927f621e bellard
    gen_op_fdivr_STN_ST0,
818 77f8dd5a bellard
    gen_op_fdiv_STN_ST0,
819 927f621e bellard
};
820 927f621e bellard
821 367e86e8 bellard
static void gen_op(DisasContext *s1, int op, int ot, int d, int s)
822 367e86e8 bellard
{
823 367e86e8 bellard
    if (d != OR_TMP0)
824 367e86e8 bellard
        gen_op_mov_TN_reg[ot][0][d]();
825 367e86e8 bellard
    if (s != OR_TMP1)
826 367e86e8 bellard
        gen_op_mov_TN_reg[ot][1][s]();
827 4b74fe1f bellard
    if (op == OP_ADCL || op == OP_SBBL) {
828 4b74fe1f bellard
        if (s1->cc_op != CC_OP_DYNAMIC)
829 4b74fe1f bellard
            gen_op_set_cc_op(s1->cc_op);
830 4b74fe1f bellard
        gen_op_arithc_T0_T1_cc[ot][op - OP_ADCL]();
831 4b74fe1f bellard
        s1->cc_op = CC_OP_DYNAMIC;
832 4b74fe1f bellard
    } else {
833 4b74fe1f bellard
        gen_op_arith_T0_T1_cc[op]();
834 4b74fe1f bellard
        s1->cc_op = cc_op_arithb[op] + ot;
835 4b74fe1f bellard
    }
836 367e86e8 bellard
    if (d != OR_TMP0 && op != OP_CMPL)
837 367e86e8 bellard
        gen_op_mov_reg_T0[ot][d]();
838 367e86e8 bellard
}
839 367e86e8 bellard
840 367e86e8 bellard
static void gen_opi(DisasContext *s1, int op, int ot, int d, int c)
841 367e86e8 bellard
{
842 ba1c6e37 bellard
    gen_op_movl_T1_im(c);
843 4b74fe1f bellard
    gen_op(s1, op, ot, d, OR_TMP1);
844 367e86e8 bellard
}
845 367e86e8 bellard
846 367e86e8 bellard
static void gen_inc(DisasContext *s1, int ot, int d, int c)
847 367e86e8 bellard
{
848 367e86e8 bellard
    if (d != OR_TMP0)
849 367e86e8 bellard
        gen_op_mov_TN_reg[ot][0][d]();
850 367e86e8 bellard
    if (s1->cc_op != CC_OP_DYNAMIC)
851 367e86e8 bellard
        gen_op_set_cc_op(s1->cc_op);
852 4b74fe1f bellard
    if (c > 0) {
853 367e86e8 bellard
        gen_op_incl_T0_cc();
854 4b74fe1f bellard
        s1->cc_op = CC_OP_INCB + ot;
855 4b74fe1f bellard
    } else {
856 367e86e8 bellard
        gen_op_decl_T0_cc();
857 4b74fe1f bellard
        s1->cc_op = CC_OP_DECB + ot;
858 4b74fe1f bellard
    }
859 367e86e8 bellard
    if (d != OR_TMP0)
860 367e86e8 bellard
        gen_op_mov_reg_T0[ot][d]();
861 367e86e8 bellard
}
862 367e86e8 bellard
863 367e86e8 bellard
static void gen_shift(DisasContext *s1, int op, int ot, int d, int s)
864 367e86e8 bellard
{
865 367e86e8 bellard
    if (d != OR_TMP0)
866 367e86e8 bellard
        gen_op_mov_TN_reg[ot][0][d]();
867 367e86e8 bellard
    if (s != OR_TMP1)
868 367e86e8 bellard
        gen_op_mov_TN_reg[ot][1][s]();
869 4b74fe1f bellard
    /* for zero counts, flags are not updated, so must do it dynamically */
870 4b74fe1f bellard
    if (s1->cc_op != CC_OP_DYNAMIC)
871 4b74fe1f bellard
        gen_op_set_cc_op(s1->cc_op);
872 4b74fe1f bellard
873 4b74fe1f bellard
    gen_op_shift_T0_T1_cc[ot][op]();
874 4b74fe1f bellard
875 367e86e8 bellard
    if (d != OR_TMP0)
876 367e86e8 bellard
        gen_op_mov_reg_T0[ot][d]();
877 367e86e8 bellard
    s1->cc_op = CC_OP_DYNAMIC; /* cannot predict flags after */
878 367e86e8 bellard
}
879 367e86e8 bellard
880 367e86e8 bellard
static void gen_shifti(DisasContext *s1, int op, int ot, int d, int c)
881 367e86e8 bellard
{
882 367e86e8 bellard
    /* currently not optimized */
883 ba1c6e37 bellard
    gen_op_movl_T1_im(c);
884 367e86e8 bellard
    gen_shift(s1, op, ot, d, OR_TMP1);
885 367e86e8 bellard
}
886 367e86e8 bellard
887 367e86e8 bellard
static void gen_lea_modrm(DisasContext *s, int modrm, int *reg_ptr, int *offset_ptr)
888 367e86e8 bellard
{
889 367e86e8 bellard
    int havesib;
890 367e86e8 bellard
    int base, disp;
891 6dbad63e bellard
    int index;
892 6dbad63e bellard
    int scale;
893 6dbad63e bellard
    int opreg;
894 6dbad63e bellard
    int mod, rm, code, override, must_add_seg;
895 6dbad63e bellard
896 9c605cb1 bellard
    override = s->override;
897 6dbad63e bellard
    must_add_seg = s->addseg;
898 9c605cb1 bellard
    if (override >= 0)
899 6dbad63e bellard
        must_add_seg = 1;
900 367e86e8 bellard
    mod = (modrm >> 6) & 3;
901 367e86e8 bellard
    rm = modrm & 7;
902 367e86e8 bellard
903 367e86e8 bellard
    if (s->aflag) {
904 367e86e8 bellard
905 367e86e8 bellard
        havesib = 0;
906 367e86e8 bellard
        base = rm;
907 6dbad63e bellard
        index = 0;
908 6dbad63e bellard
        scale = 0;
909 367e86e8 bellard
        
910 367e86e8 bellard
        if (base == 4) {
911 367e86e8 bellard
            havesib = 1;
912 367e86e8 bellard
            code = ldub(s->pc++);
913 367e86e8 bellard
            scale = (code >> 6) & 3;
914 367e86e8 bellard
            index = (code >> 3) & 7;
915 367e86e8 bellard
            base = code & 7;
916 367e86e8 bellard
        }
917 367e86e8 bellard
918 367e86e8 bellard
        switch (mod) {
919 367e86e8 bellard
        case 0:
920 367e86e8 bellard
            if (base == 5) {
921 6dbad63e bellard
                base = -1;
922 367e86e8 bellard
                disp = ldl(s->pc);
923 367e86e8 bellard
                s->pc += 4;
924 367e86e8 bellard
            } else {
925 367e86e8 bellard
                disp = 0;
926 367e86e8 bellard
            }
927 367e86e8 bellard
            break;
928 367e86e8 bellard
        case 1:
929 367e86e8 bellard
            disp = (int8_t)ldub(s->pc++);
930 367e86e8 bellard
            break;
931 367e86e8 bellard
        default:
932 367e86e8 bellard
        case 2:
933 367e86e8 bellard
            disp = ldl(s->pc);
934 367e86e8 bellard
            s->pc += 4;
935 367e86e8 bellard
            break;
936 367e86e8 bellard
        }
937 6dbad63e bellard
        
938 6dbad63e bellard
        if (base >= 0) {
939 6dbad63e bellard
            gen_op_movl_A0_reg[base]();
940 6dbad63e bellard
            if (disp != 0)
941 6dbad63e bellard
                gen_op_addl_A0_im(disp);
942 367e86e8 bellard
        } else {
943 6dbad63e bellard
            gen_op_movl_A0_im(disp);
944 6dbad63e bellard
        }
945 6dbad63e bellard
        if (havesib && (index != 4 || scale != 0)) {
946 6dbad63e bellard
            gen_op_addl_A0_reg_sN[scale][index]();
947 6dbad63e bellard
        }
948 6dbad63e bellard
        if (must_add_seg) {
949 6dbad63e bellard
            if (override < 0) {
950 6dbad63e bellard
                if (base == R_EBP || base == R_ESP)
951 6dbad63e bellard
                    override = R_SS;
952 6dbad63e bellard
                else
953 6dbad63e bellard
                    override = R_DS;
954 367e86e8 bellard
            }
955 6dbad63e bellard
            gen_op_addl_A0_seg(offsetof(CPUX86State,seg_cache[override].base));
956 367e86e8 bellard
        }
957 367e86e8 bellard
    } else {
958 4b74fe1f bellard
        switch (mod) {
959 4b74fe1f bellard
        case 0:
960 4b74fe1f bellard
            if (rm == 6) {
961 4b74fe1f bellard
                disp = lduw(s->pc);
962 4b74fe1f bellard
                s->pc += 2;
963 4b74fe1f bellard
                gen_op_movl_A0_im(disp);
964 6dbad63e bellard
                rm = 0; /* avoid SS override */
965 4b74fe1f bellard
                goto no_rm;
966 4b74fe1f bellard
            } else {
967 4b74fe1f bellard
                disp = 0;
968 4b74fe1f bellard
            }
969 4b74fe1f bellard
            break;
970 4b74fe1f bellard
        case 1:
971 4b74fe1f bellard
            disp = (int8_t)ldub(s->pc++);
972 4b74fe1f bellard
            break;
973 4b74fe1f bellard
        default:
974 4b74fe1f bellard
        case 2:
975 4b74fe1f bellard
            disp = lduw(s->pc);
976 4b74fe1f bellard
            s->pc += 2;
977 4b74fe1f bellard
            break;
978 4b74fe1f bellard
        }
979 4b74fe1f bellard
        switch(rm) {
980 4b74fe1f bellard
        case 0:
981 4b74fe1f bellard
            gen_op_movl_A0_reg[R_EBX]();
982 4b74fe1f bellard
            gen_op_addl_A0_reg_sN[0][R_ESI]();
983 4b74fe1f bellard
            break;
984 4b74fe1f bellard
        case 1:
985 4b74fe1f bellard
            gen_op_movl_A0_reg[R_EBX]();
986 4b74fe1f bellard
            gen_op_addl_A0_reg_sN[0][R_EDI]();
987 4b74fe1f bellard
            break;
988 4b74fe1f bellard
        case 2:
989 4b74fe1f bellard
            gen_op_movl_A0_reg[R_EBP]();
990 4b74fe1f bellard
            gen_op_addl_A0_reg_sN[0][R_ESI]();
991 4b74fe1f bellard
            break;
992 4b74fe1f bellard
        case 3:
993 4b74fe1f bellard
            gen_op_movl_A0_reg[R_EBP]();
994 4b74fe1f bellard
            gen_op_addl_A0_reg_sN[0][R_EDI]();
995 4b74fe1f bellard
            break;
996 4b74fe1f bellard
        case 4:
997 4b74fe1f bellard
            gen_op_movl_A0_reg[R_ESI]();
998 4b74fe1f bellard
            break;
999 4b74fe1f bellard
        case 5:
1000 4b74fe1f bellard
            gen_op_movl_A0_reg[R_EDI]();
1001 4b74fe1f bellard
            break;
1002 4b74fe1f bellard
        case 6:
1003 4b74fe1f bellard
            gen_op_movl_A0_reg[R_EBP]();
1004 4b74fe1f bellard
            break;
1005 4b74fe1f bellard
        default:
1006 4b74fe1f bellard
        case 7:
1007 4b74fe1f bellard
            gen_op_movl_A0_reg[R_EBX]();
1008 4b74fe1f bellard
            break;
1009 4b74fe1f bellard
        }
1010 4b74fe1f bellard
        if (disp != 0)
1011 4b74fe1f bellard
            gen_op_addl_A0_im(disp);
1012 4b74fe1f bellard
        gen_op_andl_A0_ffff();
1013 6dbad63e bellard
    no_rm:
1014 6dbad63e bellard
        if (must_add_seg) {
1015 6dbad63e bellard
            if (override < 0) {
1016 6dbad63e bellard
                if (rm == 2 || rm == 3 || rm == 6)
1017 6dbad63e bellard
                    override = R_SS;
1018 6dbad63e bellard
                else
1019 6dbad63e bellard
                    override = R_DS;
1020 6dbad63e bellard
            }
1021 6dbad63e bellard
            gen_op_addl_A0_seg(offsetof(CPUX86State,seg_cache[override].base));
1022 6dbad63e bellard
        }
1023 367e86e8 bellard
    }
1024 6dbad63e bellard
1025 4b74fe1f bellard
    opreg = OR_A0;
1026 4b74fe1f bellard
    disp = 0;
1027 367e86e8 bellard
    *reg_ptr = opreg;
1028 367e86e8 bellard
    *offset_ptr = disp;
1029 367e86e8 bellard
}
1030 367e86e8 bellard
1031 367e86e8 bellard
/* generate modrm memory load or store of 'reg'. TMP0 is used if reg !=
1032 367e86e8 bellard
   OR_TMP0 */
1033 367e86e8 bellard
static void gen_ldst_modrm(DisasContext *s, int modrm, int ot, int reg, int is_store)
1034 367e86e8 bellard
{
1035 367e86e8 bellard
    int mod, rm, opreg, disp;
1036 367e86e8 bellard
1037 367e86e8 bellard
    mod = (modrm >> 6) & 3;
1038 367e86e8 bellard
    rm = modrm & 7;
1039 367e86e8 bellard
    if (mod == 3) {
1040 367e86e8 bellard
        if (is_store) {
1041 367e86e8 bellard
            if (reg != OR_TMP0)
1042 367e86e8 bellard
                gen_op_mov_TN_reg[ot][0][reg]();
1043 367e86e8 bellard
            gen_op_mov_reg_T0[ot][rm]();
1044 367e86e8 bellard
        } else {
1045 367e86e8 bellard
            gen_op_mov_TN_reg[ot][0][rm]();
1046 367e86e8 bellard
            if (reg != OR_TMP0)
1047 367e86e8 bellard
                gen_op_mov_reg_T0[ot][reg]();
1048 367e86e8 bellard
        }
1049 367e86e8 bellard
    } else {
1050 367e86e8 bellard
        gen_lea_modrm(s, modrm, &opreg, &disp);
1051 367e86e8 bellard
        if (is_store) {
1052 367e86e8 bellard
            if (reg != OR_TMP0)
1053 367e86e8 bellard
                gen_op_mov_TN_reg[ot][0][reg]();
1054 367e86e8 bellard
            gen_op_st_T0_A0[ot]();
1055 367e86e8 bellard
        } else {
1056 367e86e8 bellard
            gen_op_ld_T0_A0[ot]();
1057 367e86e8 bellard
            if (reg != OR_TMP0)
1058 367e86e8 bellard
                gen_op_mov_reg_T0[ot][reg]();
1059 367e86e8 bellard
        }
1060 367e86e8 bellard
    }
1061 367e86e8 bellard
}
1062 367e86e8 bellard
1063 367e86e8 bellard
static inline uint32_t insn_get(DisasContext *s, int ot)
1064 367e86e8 bellard
{
1065 367e86e8 bellard
    uint32_t ret;
1066 367e86e8 bellard
1067 367e86e8 bellard
    switch(ot) {
1068 367e86e8 bellard
    case OT_BYTE:
1069 367e86e8 bellard
        ret = ldub(s->pc);
1070 367e86e8 bellard
        s->pc++;
1071 367e86e8 bellard
        break;
1072 367e86e8 bellard
    case OT_WORD:
1073 367e86e8 bellard
        ret = lduw(s->pc);
1074 367e86e8 bellard
        s->pc += 2;
1075 367e86e8 bellard
        break;
1076 367e86e8 bellard
    default:
1077 367e86e8 bellard
    case OT_LONG:
1078 367e86e8 bellard
        ret = ldl(s->pc);
1079 367e86e8 bellard
        s->pc += 4;
1080 367e86e8 bellard
        break;
1081 367e86e8 bellard
    }
1082 367e86e8 bellard
    return ret;
1083 367e86e8 bellard
}
1084 367e86e8 bellard
1085 dab2ed99 bellard
static inline void gen_jcc(DisasContext *s, int b, int val, int next_eip)
1086 367e86e8 bellard
{
1087 d4e8164f bellard
    TranslationBlock *tb;
1088 367e86e8 bellard
    int inv, jcc_op;
1089 d4e8164f bellard
    GenOpFunc3 *func;
1090 367e86e8 bellard
1091 367e86e8 bellard
    inv = b & 1;
1092 367e86e8 bellard
    jcc_op = (b >> 1) & 7;
1093 367e86e8 bellard
    switch(s->cc_op) {
1094 367e86e8 bellard
        /* we optimize the cmp/jcc case */
1095 367e86e8 bellard
    case CC_OP_SUBB:
1096 367e86e8 bellard
    case CC_OP_SUBW:
1097 367e86e8 bellard
    case CC_OP_SUBL:
1098 367e86e8 bellard
        func = gen_jcc_sub[s->cc_op - CC_OP_SUBB][jcc_op];
1099 367e86e8 bellard
        break;
1100 367e86e8 bellard
        
1101 367e86e8 bellard
        /* some jumps are easy to compute */
1102 367e86e8 bellard
    case CC_OP_ADDB:
1103 367e86e8 bellard
    case CC_OP_ADDW:
1104 367e86e8 bellard
    case CC_OP_ADDL:
1105 4b74fe1f bellard
    case CC_OP_ADCB:
1106 4b74fe1f bellard
    case CC_OP_ADCW:
1107 4b74fe1f bellard
    case CC_OP_ADCL:
1108 4b74fe1f bellard
    case CC_OP_SBBB:
1109 4b74fe1f bellard
    case CC_OP_SBBW:
1110 4b74fe1f bellard
    case CC_OP_SBBL:
1111 367e86e8 bellard
    case CC_OP_LOGICB:
1112 367e86e8 bellard
    case CC_OP_LOGICW:
1113 367e86e8 bellard
    case CC_OP_LOGICL:
1114 367e86e8 bellard
    case CC_OP_INCB:
1115 367e86e8 bellard
    case CC_OP_INCW:
1116 367e86e8 bellard
    case CC_OP_INCL:
1117 367e86e8 bellard
    case CC_OP_DECB:
1118 367e86e8 bellard
    case CC_OP_DECW:
1119 367e86e8 bellard
    case CC_OP_DECL:
1120 367e86e8 bellard
    case CC_OP_SHLB:
1121 367e86e8 bellard
    case CC_OP_SHLW:
1122 367e86e8 bellard
    case CC_OP_SHLL:
1123 4b74fe1f bellard
    case CC_OP_SARB:
1124 4b74fe1f bellard
    case CC_OP_SARW:
1125 4b74fe1f bellard
    case CC_OP_SARL:
1126 367e86e8 bellard
        switch(jcc_op) {
1127 367e86e8 bellard
        case JCC_Z:
1128 367e86e8 bellard
            func = gen_jcc_sub[(s->cc_op - CC_OP_ADDB) % 3][jcc_op];
1129 367e86e8 bellard
            break;
1130 367e86e8 bellard
        case JCC_S:
1131 367e86e8 bellard
            func = gen_jcc_sub[(s->cc_op - CC_OP_ADDB) % 3][jcc_op];
1132 367e86e8 bellard
            break;
1133 367e86e8 bellard
        default:
1134 d4e8164f bellard
            func = NULL;
1135 d4e8164f bellard
            break;
1136 367e86e8 bellard
        }
1137 367e86e8 bellard
        break;
1138 367e86e8 bellard
    default:
1139 d4e8164f bellard
        func = NULL;
1140 367e86e8 bellard
        break;
1141 367e86e8 bellard
    }
1142 d4e8164f bellard
1143 d4e8164f bellard
    if (s->cc_op != CC_OP_DYNAMIC)
1144 d4e8164f bellard
        gen_op_set_cc_op(s->cc_op);
1145 d4e8164f bellard
1146 d4e8164f bellard
    if (!func) {
1147 d4e8164f bellard
        gen_setcc_slow[jcc_op]();
1148 d4e8164f bellard
        func = gen_op_jcc;
1149 d4e8164f bellard
    }
1150 d4e8164f bellard
    
1151 d4e8164f bellard
    tb = s->tb;
1152 367e86e8 bellard
    if (!inv) {
1153 d4e8164f bellard
        func((long)tb, val, next_eip);
1154 367e86e8 bellard
    } else {
1155 d4e8164f bellard
        func((long)tb, next_eip, val);
1156 367e86e8 bellard
    }
1157 d4e8164f bellard
    s->is_jmp = 3;
1158 367e86e8 bellard
}
1159 367e86e8 bellard
1160 367e86e8 bellard
static void gen_setcc(DisasContext *s, int b)
1161 367e86e8 bellard
{
1162 367e86e8 bellard
    int inv, jcc_op;
1163 367e86e8 bellard
    GenOpFunc *func;
1164 367e86e8 bellard
1165 367e86e8 bellard
    inv = b & 1;
1166 367e86e8 bellard
    jcc_op = (b >> 1) & 7;
1167 367e86e8 bellard
    switch(s->cc_op) {
1168 367e86e8 bellard
        /* we optimize the cmp/jcc case */
1169 367e86e8 bellard
    case CC_OP_SUBB:
1170 367e86e8 bellard
    case CC_OP_SUBW:
1171 367e86e8 bellard
    case CC_OP_SUBL:
1172 367e86e8 bellard
        func = gen_setcc_sub[s->cc_op - CC_OP_SUBB][jcc_op];
1173 367e86e8 bellard
        if (!func)
1174 367e86e8 bellard
            goto slow_jcc;
1175 367e86e8 bellard
        break;
1176 367e86e8 bellard
        
1177 367e86e8 bellard
        /* some jumps are easy to compute */
1178 367e86e8 bellard
    case CC_OP_ADDB:
1179 367e86e8 bellard
    case CC_OP_ADDW:
1180 367e86e8 bellard
    case CC_OP_ADDL:
1181 367e86e8 bellard
    case CC_OP_LOGICB:
1182 367e86e8 bellard
    case CC_OP_LOGICW:
1183 367e86e8 bellard
    case CC_OP_LOGICL:
1184 367e86e8 bellard
    case CC_OP_INCB:
1185 367e86e8 bellard
    case CC_OP_INCW:
1186 367e86e8 bellard
    case CC_OP_INCL:
1187 367e86e8 bellard
    case CC_OP_DECB:
1188 367e86e8 bellard
    case CC_OP_DECW:
1189 367e86e8 bellard
    case CC_OP_DECL:
1190 367e86e8 bellard
    case CC_OP_SHLB:
1191 367e86e8 bellard
    case CC_OP_SHLW:
1192 367e86e8 bellard
    case CC_OP_SHLL:
1193 367e86e8 bellard
        switch(jcc_op) {
1194 367e86e8 bellard
        case JCC_Z:
1195 1017ebe9 bellard
            func = gen_setcc_sub[(s->cc_op - CC_OP_ADDB) % 3][jcc_op];
1196 367e86e8 bellard
            break;
1197 367e86e8 bellard
        case JCC_S:
1198 1017ebe9 bellard
            func = gen_setcc_sub[(s->cc_op - CC_OP_ADDB) % 3][jcc_op];
1199 367e86e8 bellard
            break;
1200 367e86e8 bellard
        default:
1201 367e86e8 bellard
            goto slow_jcc;
1202 367e86e8 bellard
        }
1203 367e86e8 bellard
        break;
1204 367e86e8 bellard
    default:
1205 367e86e8 bellard
    slow_jcc:
1206 367e86e8 bellard
        if (s->cc_op != CC_OP_DYNAMIC)
1207 1017ebe9 bellard
            gen_op_set_cc_op(s->cc_op);
1208 367e86e8 bellard
        func = gen_setcc_slow[jcc_op];
1209 367e86e8 bellard
        break;
1210 367e86e8 bellard
    }
1211 367e86e8 bellard
    func();
1212 367e86e8 bellard
    if (inv) {
1213 367e86e8 bellard
        gen_op_xor_T0_1();
1214 367e86e8 bellard
    }
1215 367e86e8 bellard
}
1216 367e86e8 bellard
1217 6dbad63e bellard
/* move T0 to seg_reg and compute if the CPU state may change */
1218 dab2ed99 bellard
static void gen_movl_seg_T0(DisasContext *s, int seg_reg)
1219 6dbad63e bellard
{
1220 6dbad63e bellard
    gen_op_movl_seg_T0(seg_reg);
1221 6dbad63e bellard
    if (!s->addseg && seg_reg < R_FS)
1222 6dbad63e bellard
        s->is_jmp = 2; /* abort translation because the register may
1223 6dbad63e bellard
                          have a non zero base */
1224 6dbad63e bellard
}
1225 6dbad63e bellard
1226 dab2ed99 bellard
/* generate a push. It depends on ss32, addseg and dflag */
1227 dab2ed99 bellard
static void gen_push_T0(DisasContext *s)
1228 dab2ed99 bellard
{
1229 dab2ed99 bellard
    if (s->ss32) {
1230 dab2ed99 bellard
        if (!s->addseg) {
1231 dab2ed99 bellard
            if (s->dflag)
1232 dab2ed99 bellard
                gen_op_pushl_T0();
1233 dab2ed99 bellard
            else
1234 dab2ed99 bellard
                gen_op_pushw_T0();
1235 dab2ed99 bellard
        } else {
1236 dab2ed99 bellard
            if (s->dflag)
1237 dab2ed99 bellard
                gen_op_pushl_ss32_T0();
1238 dab2ed99 bellard
            else
1239 dab2ed99 bellard
                gen_op_pushw_ss32_T0();
1240 dab2ed99 bellard
        }
1241 dab2ed99 bellard
    } else {
1242 dab2ed99 bellard
        if (s->dflag)
1243 dab2ed99 bellard
            gen_op_pushl_ss16_T0();
1244 dab2ed99 bellard
        else
1245 dab2ed99 bellard
            gen_op_pushw_ss16_T0();
1246 dab2ed99 bellard
    }
1247 dab2ed99 bellard
}
1248 dab2ed99 bellard
1249 dab2ed99 bellard
/* two step pop is necessary for precise exceptions */
1250 dab2ed99 bellard
static void gen_pop_T0(DisasContext *s)
1251 dab2ed99 bellard
{
1252 dab2ed99 bellard
    if (s->ss32) {
1253 dab2ed99 bellard
        if (!s->addseg) {
1254 dab2ed99 bellard
            if (s->dflag)
1255 dab2ed99 bellard
                gen_op_popl_T0();
1256 dab2ed99 bellard
            else
1257 dab2ed99 bellard
                gen_op_popw_T0();
1258 dab2ed99 bellard
        } else {
1259 dab2ed99 bellard
            if (s->dflag)
1260 dab2ed99 bellard
                gen_op_popl_ss32_T0();
1261 dab2ed99 bellard
            else
1262 dab2ed99 bellard
                gen_op_popw_ss32_T0();
1263 dab2ed99 bellard
        }
1264 dab2ed99 bellard
    } else {
1265 dab2ed99 bellard
        if (s->dflag)
1266 dab2ed99 bellard
            gen_op_popl_ss16_T0();
1267 dab2ed99 bellard
        else
1268 dab2ed99 bellard
            gen_op_popw_ss16_T0();
1269 dab2ed99 bellard
    }
1270 dab2ed99 bellard
}
1271 dab2ed99 bellard
1272 dab2ed99 bellard
static void gen_pop_update(DisasContext *s)
1273 dab2ed99 bellard
{
1274 dab2ed99 bellard
    if (s->ss32) {
1275 dab2ed99 bellard
        if (s->dflag)
1276 dab2ed99 bellard
            gen_op_addl_ESP_4();
1277 dab2ed99 bellard
        else
1278 dab2ed99 bellard
            gen_op_addl_ESP_2();
1279 dab2ed99 bellard
    } else {
1280 dab2ed99 bellard
        if (s->dflag)
1281 dab2ed99 bellard
            gen_op_addw_ESP_4();
1282 dab2ed99 bellard
        else
1283 dab2ed99 bellard
            gen_op_addw_ESP_2();
1284 dab2ed99 bellard
    }
1285 dab2ed99 bellard
}
1286 dab2ed99 bellard
1287 dab2ed99 bellard
/* NOTE: wrap around in 16 bit not fully handled */
1288 dab2ed99 bellard
static void gen_pusha(DisasContext *s)
1289 dab2ed99 bellard
{
1290 dab2ed99 bellard
    int i;
1291 dab2ed99 bellard
    gen_op_movl_A0_ESP();
1292 dab2ed99 bellard
    gen_op_addl_A0_im(-16 <<  s->dflag);
1293 dab2ed99 bellard
    if (!s->ss32)
1294 dab2ed99 bellard
        gen_op_andl_A0_ffff();
1295 dab2ed99 bellard
    gen_op_movl_T1_A0();
1296 dab2ed99 bellard
    if (s->addseg)
1297 dab2ed99 bellard
        gen_op_addl_A0_seg(offsetof(CPUX86State,seg_cache[R_SS].base));
1298 dab2ed99 bellard
    for(i = 0;i < 8; i++) {
1299 dab2ed99 bellard
        gen_op_mov_TN_reg[OT_LONG][0][7 - i]();
1300 dab2ed99 bellard
        gen_op_st_T0_A0[OT_WORD + s->dflag]();
1301 dab2ed99 bellard
        gen_op_addl_A0_im(2 <<  s->dflag);
1302 dab2ed99 bellard
    }
1303 dab2ed99 bellard
    gen_op_mov_reg_T1[OT_WORD + s->dflag][R_ESP]();
1304 dab2ed99 bellard
}
1305 dab2ed99 bellard
1306 dab2ed99 bellard
/* NOTE: wrap around in 16 bit not fully handled */
1307 dab2ed99 bellard
static void gen_popa(DisasContext *s)
1308 dab2ed99 bellard
{
1309 dab2ed99 bellard
    int i;
1310 dab2ed99 bellard
    gen_op_movl_A0_ESP();
1311 dab2ed99 bellard
    if (!s->ss32)
1312 dab2ed99 bellard
        gen_op_andl_A0_ffff();
1313 dab2ed99 bellard
    gen_op_movl_T1_A0();
1314 dab2ed99 bellard
    gen_op_addl_T1_im(16 <<  s->dflag);
1315 dab2ed99 bellard
    if (s->addseg)
1316 dab2ed99 bellard
        gen_op_addl_A0_seg(offsetof(CPUX86State,seg_cache[R_SS].base));
1317 dab2ed99 bellard
    for(i = 0;i < 8; i++) {
1318 dab2ed99 bellard
        /* ESP is not reloaded */
1319 dab2ed99 bellard
        if (i != 3) {
1320 dab2ed99 bellard
            gen_op_ld_T0_A0[OT_WORD + s->dflag]();
1321 dab2ed99 bellard
            gen_op_mov_reg_T0[OT_WORD + s->dflag][7 - i]();
1322 dab2ed99 bellard
        }
1323 dab2ed99 bellard
        gen_op_addl_A0_im(2 <<  s->dflag);
1324 dab2ed99 bellard
    }
1325 dab2ed99 bellard
    gen_op_mov_reg_T1[OT_WORD + s->dflag][R_ESP]();
1326 dab2ed99 bellard
}
1327 dab2ed99 bellard
1328 dab2ed99 bellard
/* NOTE: wrap around in 16 bit not fully handled */
1329 dab2ed99 bellard
/* XXX: check this */
1330 dab2ed99 bellard
static void gen_enter(DisasContext *s, int esp_addend, int level)
1331 dab2ed99 bellard
{
1332 dab2ed99 bellard
    int ot, level1, addend, opsize;
1333 dab2ed99 bellard
1334 dab2ed99 bellard
    ot = s->dflag + OT_WORD;
1335 dab2ed99 bellard
    level &= 0x1f;
1336 dab2ed99 bellard
    level1 = level;
1337 dab2ed99 bellard
    opsize = 2 << s->dflag;
1338 dab2ed99 bellard
1339 dab2ed99 bellard
    gen_op_movl_A0_ESP();
1340 dab2ed99 bellard
    gen_op_addl_A0_im(-opsize);
1341 dab2ed99 bellard
    if (!s->ss32)
1342 dab2ed99 bellard
        gen_op_andl_A0_ffff();
1343 dab2ed99 bellard
    gen_op_movl_T1_A0();
1344 dab2ed99 bellard
    if (s->addseg)
1345 dab2ed99 bellard
        gen_op_addl_A0_seg(offsetof(CPUX86State,seg_cache[R_SS].base));
1346 dab2ed99 bellard
    /* push bp */
1347 dab2ed99 bellard
    gen_op_mov_TN_reg[OT_LONG][0][R_EBP]();
1348 dab2ed99 bellard
    gen_op_st_T0_A0[ot]();
1349 dab2ed99 bellard
    if (level) {
1350 dab2ed99 bellard
        while (level--) {
1351 dab2ed99 bellard
            gen_op_addl_A0_im(-opsize);
1352 dab2ed99 bellard
            gen_op_addl_T0_im(-opsize);
1353 dab2ed99 bellard
            gen_op_st_T0_A0[ot]();
1354 dab2ed99 bellard
        }
1355 dab2ed99 bellard
        gen_op_addl_A0_im(-opsize);
1356 dab2ed99 bellard
        /* XXX: add st_T1_A0 ? */
1357 dab2ed99 bellard
        gen_op_movl_T0_T1();
1358 dab2ed99 bellard
        gen_op_st_T0_A0[ot]();
1359 dab2ed99 bellard
    }
1360 dab2ed99 bellard
    gen_op_mov_reg_T1[ot][R_EBP]();
1361 dab2ed99 bellard
    addend = -esp_addend;
1362 dab2ed99 bellard
    if (level1)
1363 dab2ed99 bellard
        addend -= opsize * (level1 + 1);
1364 dab2ed99 bellard
    gen_op_addl_T1_im(addend);
1365 dab2ed99 bellard
    gen_op_mov_reg_T1[ot][R_ESP]();
1366 dab2ed99 bellard
}
1367 dab2ed99 bellard
1368 c50c0c3f bellard
static void gen_exception(DisasContext *s, int trapno, unsigned int cur_eip)
1369 c50c0c3f bellard
{
1370 c50c0c3f bellard
    if (s->cc_op != CC_OP_DYNAMIC)
1371 c50c0c3f bellard
        gen_op_set_cc_op(s->cc_op);
1372 c50c0c3f bellard
    gen_op_jmp_im(cur_eip);
1373 c50c0c3f bellard
    gen_op_raise_exception(trapno);
1374 c50c0c3f bellard
    s->is_jmp = 1;
1375 c50c0c3f bellard
}
1376 c50c0c3f bellard
1377 d4e8164f bellard
/* generate a jump to eip. No segment change must happen before as a
1378 d4e8164f bellard
   direct call to the next block may occur */
1379 d4e8164f bellard
static void gen_jmp(DisasContext *s, unsigned int eip)
1380 d4e8164f bellard
{
1381 d4e8164f bellard
    TranslationBlock *tb = s->tb;
1382 d4e8164f bellard
1383 d4e8164f bellard
    if (s->cc_op != CC_OP_DYNAMIC)
1384 d4e8164f bellard
        gen_op_set_cc_op(s->cc_op);
1385 d4e8164f bellard
    gen_op_jmp_tb_next((long)tb, eip);
1386 d4e8164f bellard
    s->is_jmp = 3;
1387 d4e8164f bellard
}
1388 d4e8164f bellard
1389 0ecfa993 bellard
/* return the next pc address. Return -1 if no insn found. *is_jmp_ptr
1390 0ecfa993 bellard
   is set to true if the instruction sets the PC (last instruction of
1391 0ecfa993 bellard
   a basic block) */
1392 6dbad63e bellard
long disas_insn(DisasContext *s, uint8_t *pc_start)
1393 367e86e8 bellard
{
1394 367e86e8 bellard
    int b, prefixes, aflag, dflag;
1395 367e86e8 bellard
    int shift, ot;
1396 367e86e8 bellard
    int modrm, reg, rm, mod, reg_addr, op, opreg, offset_addr, val;
1397 dab2ed99 bellard
    unsigned int next_eip;
1398 367e86e8 bellard
1399 367e86e8 bellard
    s->pc = pc_start;
1400 367e86e8 bellard
    prefixes = 0;
1401 6dbad63e bellard
    aflag = s->code32;
1402 6dbad63e bellard
    dflag = s->code32;
1403 9c605cb1 bellard
    s->override = -1;
1404 367e86e8 bellard
 next_byte:
1405 367e86e8 bellard
    b = ldub(s->pc);
1406 367e86e8 bellard
    s->pc++;
1407 367e86e8 bellard
    /* check prefixes */
1408 367e86e8 bellard
    switch (b) {
1409 367e86e8 bellard
    case 0xf3:
1410 367e86e8 bellard
        prefixes |= PREFIX_REPZ;
1411 367e86e8 bellard
        goto next_byte;
1412 367e86e8 bellard
    case 0xf2:
1413 367e86e8 bellard
        prefixes |= PREFIX_REPNZ;
1414 367e86e8 bellard
        goto next_byte;
1415 367e86e8 bellard
    case 0xf0:
1416 367e86e8 bellard
        prefixes |= PREFIX_LOCK;
1417 367e86e8 bellard
        goto next_byte;
1418 367e86e8 bellard
    case 0x2e:
1419 9c605cb1 bellard
        s->override = R_CS;
1420 367e86e8 bellard
        goto next_byte;
1421 367e86e8 bellard
    case 0x36:
1422 9c605cb1 bellard
        s->override = R_SS;
1423 367e86e8 bellard
        goto next_byte;
1424 367e86e8 bellard
    case 0x3e:
1425 9c605cb1 bellard
        s->override = R_DS;
1426 367e86e8 bellard
        goto next_byte;
1427 367e86e8 bellard
    case 0x26:
1428 9c605cb1 bellard
        s->override = R_ES;
1429 367e86e8 bellard
        goto next_byte;
1430 367e86e8 bellard
    case 0x64:
1431 9c605cb1 bellard
        s->override = R_FS;
1432 367e86e8 bellard
        goto next_byte;
1433 367e86e8 bellard
    case 0x65:
1434 9c605cb1 bellard
        s->override = R_GS;
1435 367e86e8 bellard
        goto next_byte;
1436 367e86e8 bellard
    case 0x66:
1437 367e86e8 bellard
        prefixes |= PREFIX_DATA;
1438 367e86e8 bellard
        goto next_byte;
1439 367e86e8 bellard
    case 0x67:
1440 367e86e8 bellard
        prefixes |= PREFIX_ADR;
1441 367e86e8 bellard
        goto next_byte;
1442 367e86e8 bellard
    }
1443 367e86e8 bellard
1444 367e86e8 bellard
    if (prefixes & PREFIX_DATA)
1445 367e86e8 bellard
        dflag ^= 1;
1446 367e86e8 bellard
    if (prefixes & PREFIX_ADR)
1447 367e86e8 bellard
        aflag ^= 1;
1448 367e86e8 bellard
1449 367e86e8 bellard
    s->prefix = prefixes;
1450 367e86e8 bellard
    s->aflag = aflag;
1451 367e86e8 bellard
    s->dflag = dflag;
1452 367e86e8 bellard
1453 1b6b029e bellard
    /* lock generation */
1454 1b6b029e bellard
    if (prefixes & PREFIX_LOCK)
1455 1b6b029e bellard
        gen_op_lock();
1456 1b6b029e bellard
1457 367e86e8 bellard
    /* now check op code */
1458 367e86e8 bellard
 reswitch:
1459 367e86e8 bellard
    switch(b) {
1460 367e86e8 bellard
    case 0x0f:
1461 367e86e8 bellard
        /**************************/
1462 367e86e8 bellard
        /* extended op code */
1463 367e86e8 bellard
        b = ldub(s->pc++) | 0x100;
1464 367e86e8 bellard
        goto reswitch;
1465 367e86e8 bellard
        
1466 367e86e8 bellard
        /**************************/
1467 367e86e8 bellard
        /* arith & logic */
1468 367e86e8 bellard
    case 0x00 ... 0x05:
1469 367e86e8 bellard
    case 0x08 ... 0x0d:
1470 367e86e8 bellard
    case 0x10 ... 0x15:
1471 367e86e8 bellard
    case 0x18 ... 0x1d:
1472 367e86e8 bellard
    case 0x20 ... 0x25:
1473 367e86e8 bellard
    case 0x28 ... 0x2d:
1474 367e86e8 bellard
    case 0x30 ... 0x35:
1475 367e86e8 bellard
    case 0x38 ... 0x3d:
1476 367e86e8 bellard
        {
1477 367e86e8 bellard
            int op, f, val;
1478 367e86e8 bellard
            op = (b >> 3) & 7;
1479 367e86e8 bellard
            f = (b >> 1) & 3;
1480 367e86e8 bellard
1481 367e86e8 bellard
            if ((b & 1) == 0)
1482 367e86e8 bellard
                ot = OT_BYTE;
1483 367e86e8 bellard
            else
1484 367e86e8 bellard
                ot = dflag ? OT_LONG : OT_WORD;
1485 367e86e8 bellard
            
1486 367e86e8 bellard
            switch(f) {
1487 367e86e8 bellard
            case 0: /* OP Ev, Gv */
1488 367e86e8 bellard
                modrm = ldub(s->pc++);
1489 367e86e8 bellard
                reg = ((modrm >> 3) & 7) + OR_EAX;
1490 367e86e8 bellard
                mod = (modrm >> 6) & 3;
1491 367e86e8 bellard
                rm = modrm & 7;
1492 367e86e8 bellard
                if (mod != 3) {
1493 367e86e8 bellard
                    gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
1494 367e86e8 bellard
                    gen_op_ld_T0_A0[ot]();
1495 367e86e8 bellard
                    opreg = OR_TMP0;
1496 367e86e8 bellard
                } else {
1497 367e86e8 bellard
                    opreg = OR_EAX + rm;
1498 367e86e8 bellard
                }
1499 367e86e8 bellard
                gen_op(s, op, ot, opreg, reg);
1500 367e86e8 bellard
                if (mod != 3 && op != 7) {
1501 367e86e8 bellard
                    gen_op_st_T0_A0[ot]();
1502 367e86e8 bellard
                }
1503 367e86e8 bellard
                break;
1504 367e86e8 bellard
            case 1: /* OP Gv, Ev */
1505 367e86e8 bellard
                modrm = ldub(s->pc++);
1506 367e86e8 bellard
                mod = (modrm >> 6) & 3;
1507 367e86e8 bellard
                reg = ((modrm >> 3) & 7) + OR_EAX;
1508 367e86e8 bellard
                rm = modrm & 7;
1509 367e86e8 bellard
                if (mod != 3) {
1510 367e86e8 bellard
                    gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
1511 367e86e8 bellard
                    gen_op_ld_T1_A0[ot]();
1512 367e86e8 bellard
                    opreg = OR_TMP1;
1513 367e86e8 bellard
                } else {
1514 367e86e8 bellard
                    opreg = OR_EAX + rm;
1515 367e86e8 bellard
                }
1516 367e86e8 bellard
                gen_op(s, op, ot, reg, opreg);
1517 367e86e8 bellard
                break;
1518 367e86e8 bellard
            case 2: /* OP A, Iv */
1519 367e86e8 bellard
                val = insn_get(s, ot);
1520 367e86e8 bellard
                gen_opi(s, op, ot, OR_EAX, val);
1521 367e86e8 bellard
                break;
1522 367e86e8 bellard
            }
1523 367e86e8 bellard
        }
1524 367e86e8 bellard
        break;
1525 367e86e8 bellard
1526 367e86e8 bellard
    case 0x80: /* GRP1 */
1527 367e86e8 bellard
    case 0x81:
1528 367e86e8 bellard
    case 0x83:
1529 367e86e8 bellard
        {
1530 367e86e8 bellard
            int val;
1531 367e86e8 bellard
1532 367e86e8 bellard
            if ((b & 1) == 0)
1533 367e86e8 bellard
                ot = OT_BYTE;
1534 367e86e8 bellard
            else
1535 367e86e8 bellard
                ot = dflag ? OT_LONG : OT_WORD;
1536 367e86e8 bellard
            
1537 367e86e8 bellard
            modrm = ldub(s->pc++);
1538 367e86e8 bellard
            mod = (modrm >> 6) & 3;
1539 367e86e8 bellard
            rm = modrm & 7;
1540 367e86e8 bellard
            op = (modrm >> 3) & 7;
1541 367e86e8 bellard
            
1542 367e86e8 bellard
            if (mod != 3) {
1543 367e86e8 bellard
                gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
1544 367e86e8 bellard
                gen_op_ld_T0_A0[ot]();
1545 367e86e8 bellard
                opreg = OR_TMP0;
1546 367e86e8 bellard
            } else {
1547 367e86e8 bellard
                opreg = rm + OR_EAX;
1548 367e86e8 bellard
            }
1549 367e86e8 bellard
1550 367e86e8 bellard
            switch(b) {
1551 367e86e8 bellard
            default:
1552 367e86e8 bellard
            case 0x80:
1553 367e86e8 bellard
            case 0x81:
1554 367e86e8 bellard
                val = insn_get(s, ot);
1555 367e86e8 bellard
                break;
1556 367e86e8 bellard
            case 0x83:
1557 367e86e8 bellard
                val = (int8_t)insn_get(s, OT_BYTE);
1558 367e86e8 bellard
                break;
1559 367e86e8 bellard
            }
1560 367e86e8 bellard
1561 367e86e8 bellard
            gen_opi(s, op, ot, opreg, val);
1562 367e86e8 bellard
            if (op != 7 && mod != 3) {
1563 367e86e8 bellard
                gen_op_st_T0_A0[ot]();
1564 367e86e8 bellard
            }
1565 367e86e8 bellard
        }
1566 367e86e8 bellard
        break;
1567 367e86e8 bellard
1568 367e86e8 bellard
        /**************************/
1569 367e86e8 bellard
        /* inc, dec, and other misc arith */
1570 367e86e8 bellard
    case 0x40 ... 0x47: /* inc Gv */
1571 367e86e8 bellard
        ot = dflag ? OT_LONG : OT_WORD;
1572 367e86e8 bellard
        gen_inc(s, ot, OR_EAX + (b & 7), 1);
1573 367e86e8 bellard
        break;
1574 367e86e8 bellard
    case 0x48 ... 0x4f: /* dec Gv */
1575 367e86e8 bellard
        ot = dflag ? OT_LONG : OT_WORD;
1576 367e86e8 bellard
        gen_inc(s, ot, OR_EAX + (b & 7), -1);
1577 367e86e8 bellard
        break;
1578 367e86e8 bellard
    case 0xf6: /* GRP3 */
1579 367e86e8 bellard
    case 0xf7:
1580 367e86e8 bellard
        if ((b & 1) == 0)
1581 367e86e8 bellard
            ot = OT_BYTE;
1582 367e86e8 bellard
        else
1583 367e86e8 bellard
            ot = dflag ? OT_LONG : OT_WORD;
1584 367e86e8 bellard
1585 367e86e8 bellard
        modrm = ldub(s->pc++);
1586 367e86e8 bellard
        mod = (modrm >> 6) & 3;
1587 367e86e8 bellard
        rm = modrm & 7;
1588 367e86e8 bellard
        op = (modrm >> 3) & 7;
1589 367e86e8 bellard
        if (mod != 3) {
1590 367e86e8 bellard
            gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
1591 367e86e8 bellard
            gen_op_ld_T0_A0[ot]();
1592 367e86e8 bellard
        } else {
1593 367e86e8 bellard
            gen_op_mov_TN_reg[ot][0][rm]();
1594 367e86e8 bellard
        }
1595 367e86e8 bellard
1596 367e86e8 bellard
        switch(op) {
1597 367e86e8 bellard
        case 0: /* test */
1598 367e86e8 bellard
            val = insn_get(s, ot);
1599 ba1c6e37 bellard
            gen_op_movl_T1_im(val);
1600 367e86e8 bellard
            gen_op_testl_T0_T1_cc();
1601 367e86e8 bellard
            s->cc_op = CC_OP_LOGICB + ot;
1602 367e86e8 bellard
            break;
1603 367e86e8 bellard
        case 2: /* not */
1604 367e86e8 bellard
            gen_op_notl_T0();
1605 367e86e8 bellard
            if (mod != 3) {
1606 367e86e8 bellard
                gen_op_st_T0_A0[ot]();
1607 367e86e8 bellard
            } else {
1608 367e86e8 bellard
                gen_op_mov_reg_T0[ot][rm]();
1609 367e86e8 bellard
            }
1610 367e86e8 bellard
            break;
1611 367e86e8 bellard
        case 3: /* neg */
1612 367e86e8 bellard
            gen_op_negl_T0_cc();
1613 367e86e8 bellard
            if (mod != 3) {
1614 367e86e8 bellard
                gen_op_st_T0_A0[ot]();
1615 367e86e8 bellard
            } else {
1616 367e86e8 bellard
                gen_op_mov_reg_T0[ot][rm]();
1617 367e86e8 bellard
            }
1618 367e86e8 bellard
            s->cc_op = CC_OP_SUBB + ot;
1619 367e86e8 bellard
            break;
1620 367e86e8 bellard
        case 4: /* mul */
1621 367e86e8 bellard
            switch(ot) {
1622 367e86e8 bellard
            case OT_BYTE:
1623 367e86e8 bellard
                gen_op_mulb_AL_T0();
1624 367e86e8 bellard
                break;
1625 367e86e8 bellard
            case OT_WORD:
1626 367e86e8 bellard
                gen_op_mulw_AX_T0();
1627 367e86e8 bellard
                break;
1628 367e86e8 bellard
            default:
1629 367e86e8 bellard
            case OT_LONG:
1630 367e86e8 bellard
                gen_op_mull_EAX_T0();
1631 367e86e8 bellard
                break;
1632 367e86e8 bellard
            }
1633 0ecfa993 bellard
            s->cc_op = CC_OP_MUL;
1634 367e86e8 bellard
            break;
1635 367e86e8 bellard
        case 5: /* imul */
1636 367e86e8 bellard
            switch(ot) {
1637 367e86e8 bellard
            case OT_BYTE:
1638 367e86e8 bellard
                gen_op_imulb_AL_T0();
1639 367e86e8 bellard
                break;
1640 367e86e8 bellard
            case OT_WORD:
1641 367e86e8 bellard
                gen_op_imulw_AX_T0();
1642 367e86e8 bellard
                break;
1643 367e86e8 bellard
            default:
1644 367e86e8 bellard
            case OT_LONG:
1645 367e86e8 bellard
                gen_op_imull_EAX_T0();
1646 367e86e8 bellard
                break;
1647 367e86e8 bellard
            }
1648 0ecfa993 bellard
            s->cc_op = CC_OP_MUL;
1649 367e86e8 bellard
            break;
1650 367e86e8 bellard
        case 6: /* div */
1651 367e86e8 bellard
            switch(ot) {
1652 367e86e8 bellard
            case OT_BYTE:
1653 367e86e8 bellard
                gen_op_divb_AL_T0();
1654 367e86e8 bellard
                break;
1655 367e86e8 bellard
            case OT_WORD:
1656 367e86e8 bellard
                gen_op_divw_AX_T0();
1657 367e86e8 bellard
                break;
1658 367e86e8 bellard
            default:
1659 367e86e8 bellard
            case OT_LONG:
1660 367e86e8 bellard
                gen_op_divl_EAX_T0();
1661 367e86e8 bellard
                break;
1662 367e86e8 bellard
            }
1663 367e86e8 bellard
            break;
1664 367e86e8 bellard
        case 7: /* idiv */
1665 367e86e8 bellard
            switch(ot) {
1666 367e86e8 bellard
            case OT_BYTE:
1667 367e86e8 bellard
                gen_op_idivb_AL_T0();
1668 367e86e8 bellard
                break;
1669 367e86e8 bellard
            case OT_WORD:
1670 367e86e8 bellard
                gen_op_idivw_AX_T0();
1671 367e86e8 bellard
                break;
1672 367e86e8 bellard
            default:
1673 367e86e8 bellard
            case OT_LONG:
1674 367e86e8 bellard
                gen_op_idivl_EAX_T0();
1675 367e86e8 bellard
                break;
1676 367e86e8 bellard
            }
1677 367e86e8 bellard
            break;
1678 367e86e8 bellard
        default:
1679 1a9353d2 bellard
            goto illegal_op;
1680 367e86e8 bellard
        }
1681 367e86e8 bellard
        break;
1682 367e86e8 bellard
1683 367e86e8 bellard
    case 0xfe: /* GRP4 */
1684 367e86e8 bellard
    case 0xff: /* GRP5 */
1685 367e86e8 bellard
        if ((b & 1) == 0)
1686 367e86e8 bellard
            ot = OT_BYTE;
1687 367e86e8 bellard
        else
1688 367e86e8 bellard
            ot = dflag ? OT_LONG : OT_WORD;
1689 367e86e8 bellard
1690 367e86e8 bellard
        modrm = ldub(s->pc++);
1691 367e86e8 bellard
        mod = (modrm >> 6) & 3;
1692 367e86e8 bellard
        rm = modrm & 7;
1693 367e86e8 bellard
        op = (modrm >> 3) & 7;
1694 367e86e8 bellard
        if (op >= 2 && b == 0xfe) {
1695 1a9353d2 bellard
            goto illegal_op;
1696 367e86e8 bellard
        }
1697 367e86e8 bellard
        if (mod != 3) {
1698 367e86e8 bellard
            gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
1699 dab2ed99 bellard
            if (op != 3 && op != 5)
1700 dab2ed99 bellard
                gen_op_ld_T0_A0[ot]();
1701 367e86e8 bellard
        } else {
1702 367e86e8 bellard
            gen_op_mov_TN_reg[ot][0][rm]();
1703 367e86e8 bellard
        }
1704 367e86e8 bellard
1705 367e86e8 bellard
        switch(op) {
1706 367e86e8 bellard
        case 0: /* inc Ev */
1707 367e86e8 bellard
            gen_inc(s, ot, OR_TMP0, 1);
1708 367e86e8 bellard
            if (mod != 3)
1709 367e86e8 bellard
                gen_op_st_T0_A0[ot]();
1710 4b74fe1f bellard
            else
1711 4b74fe1f bellard
                gen_op_mov_reg_T0[ot][rm]();
1712 367e86e8 bellard
            break;
1713 367e86e8 bellard
        case 1: /* dec Ev */
1714 367e86e8 bellard
            gen_inc(s, ot, OR_TMP0, -1);
1715 367e86e8 bellard
            if (mod != 3)
1716 367e86e8 bellard
                gen_op_st_T0_A0[ot]();
1717 4b74fe1f bellard
            else
1718 4b74fe1f bellard
                gen_op_mov_reg_T0[ot][rm]();
1719 367e86e8 bellard
            break;
1720 367e86e8 bellard
        case 2: /* call Ev */
1721 dab2ed99 bellard
            /* XXX: optimize if memory (no and is necessary) */
1722 dab2ed99 bellard
            if (s->dflag == 0)
1723 dab2ed99 bellard
                gen_op_andl_T0_ffff();
1724 dab2ed99 bellard
            gen_op_jmp_T0();
1725 dab2ed99 bellard
            next_eip = s->pc - s->cs_base;
1726 dab2ed99 bellard
            gen_op_movl_T0_im(next_eip);
1727 dab2ed99 bellard
            gen_push_T0(s);
1728 dab2ed99 bellard
            s->is_jmp = 1;
1729 dab2ed99 bellard
            break;
1730 dab2ed99 bellard
        case 3: /* lcall Ev */
1731 dab2ed99 bellard
            /* push return segment + offset */
1732 dab2ed99 bellard
            gen_op_movl_T0_seg(R_CS);
1733 dab2ed99 bellard
            gen_push_T0(s);
1734 dab2ed99 bellard
            next_eip = s->pc - s->cs_base;
1735 dab2ed99 bellard
            gen_op_movl_T0_im(next_eip);
1736 dab2ed99 bellard
            gen_push_T0(s);
1737 dab2ed99 bellard
1738 dab2ed99 bellard
            gen_op_ld_T1_A0[ot]();
1739 dab2ed99 bellard
            gen_op_addl_A0_im(1 << (ot - OT_WORD + 1));
1740 dab2ed99 bellard
            gen_op_lduw_T0_A0();
1741 dab2ed99 bellard
            gen_movl_seg_T0(s, R_CS);
1742 dab2ed99 bellard
            gen_op_movl_T0_T1();
1743 367e86e8 bellard
            gen_op_jmp_T0();
1744 6dbad63e bellard
            s->is_jmp = 1;
1745 367e86e8 bellard
            break;
1746 367e86e8 bellard
        case 4: /* jmp Ev */
1747 dab2ed99 bellard
            if (s->dflag == 0)
1748 dab2ed99 bellard
                gen_op_andl_T0_ffff();
1749 dab2ed99 bellard
            gen_op_jmp_T0();
1750 dab2ed99 bellard
            s->is_jmp = 1;
1751 dab2ed99 bellard
            break;
1752 dab2ed99 bellard
        case 5: /* ljmp Ev */
1753 dab2ed99 bellard
            gen_op_ld_T1_A0[ot]();
1754 dab2ed99 bellard
            gen_op_addl_A0_im(1 << (ot - OT_WORD + 1));
1755 dab2ed99 bellard
            gen_op_lduw_T0_A0();
1756 dab2ed99 bellard
            gen_movl_seg_T0(s, R_CS);
1757 dab2ed99 bellard
            gen_op_movl_T0_T1();
1758 367e86e8 bellard
            gen_op_jmp_T0();
1759 6dbad63e bellard
            s->is_jmp = 1;
1760 367e86e8 bellard
            break;
1761 367e86e8 bellard
        case 6: /* push Ev */
1762 dab2ed99 bellard
            gen_push_T0(s);
1763 367e86e8 bellard
            break;
1764 367e86e8 bellard
        default:
1765 1a9353d2 bellard
            goto illegal_op;
1766 367e86e8 bellard
        }
1767 367e86e8 bellard
        break;
1768 367e86e8 bellard
1769 367e86e8 bellard
    case 0x84: /* test Ev, Gv */
1770 367e86e8 bellard
    case 0x85: 
1771 367e86e8 bellard
        if ((b & 1) == 0)
1772 367e86e8 bellard
            ot = OT_BYTE;
1773 367e86e8 bellard
        else
1774 367e86e8 bellard
            ot = dflag ? OT_LONG : OT_WORD;
1775 367e86e8 bellard
1776 367e86e8 bellard
        modrm = ldub(s->pc++);
1777 367e86e8 bellard
        mod = (modrm >> 6) & 3;
1778 367e86e8 bellard
        rm = modrm & 7;
1779 367e86e8 bellard
        reg = (modrm >> 3) & 7;
1780 367e86e8 bellard
        
1781 367e86e8 bellard
        gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0);
1782 367e86e8 bellard
        gen_op_mov_TN_reg[ot][1][reg + OR_EAX]();
1783 367e86e8 bellard
        gen_op_testl_T0_T1_cc();
1784 367e86e8 bellard
        s->cc_op = CC_OP_LOGICB + ot;
1785 367e86e8 bellard
        break;
1786 367e86e8 bellard
        
1787 367e86e8 bellard
    case 0xa8: /* test eAX, Iv */
1788 367e86e8 bellard
    case 0xa9:
1789 367e86e8 bellard
        if ((b & 1) == 0)
1790 367e86e8 bellard
            ot = OT_BYTE;
1791 367e86e8 bellard
        else
1792 367e86e8 bellard
            ot = dflag ? OT_LONG : OT_WORD;
1793 367e86e8 bellard
        val = insn_get(s, ot);
1794 367e86e8 bellard
1795 367e86e8 bellard
        gen_op_mov_TN_reg[ot][0][OR_EAX]();
1796 ba1c6e37 bellard
        gen_op_movl_T1_im(val);
1797 367e86e8 bellard
        gen_op_testl_T0_T1_cc();
1798 367e86e8 bellard
        s->cc_op = CC_OP_LOGICB + ot;
1799 367e86e8 bellard
        break;
1800 367e86e8 bellard
        
1801 367e86e8 bellard
    case 0x98: /* CWDE/CBW */
1802 367e86e8 bellard
        if (dflag)
1803 367e86e8 bellard
            gen_op_movswl_EAX_AX();
1804 367e86e8 bellard
        else
1805 367e86e8 bellard
            gen_op_movsbw_AX_AL();
1806 367e86e8 bellard
        break;
1807 367e86e8 bellard
    case 0x99: /* CDQ/CWD */
1808 367e86e8 bellard
        if (dflag)
1809 367e86e8 bellard
            gen_op_movslq_EDX_EAX();
1810 367e86e8 bellard
        else
1811 367e86e8 bellard
            gen_op_movswl_DX_AX();
1812 367e86e8 bellard
        break;
1813 367e86e8 bellard
    case 0x1af: /* imul Gv, Ev */
1814 367e86e8 bellard
    case 0x69: /* imul Gv, Ev, I */
1815 367e86e8 bellard
    case 0x6b:
1816 367e86e8 bellard
        ot = dflag ? OT_LONG : OT_WORD;
1817 367e86e8 bellard
        modrm = ldub(s->pc++);
1818 367e86e8 bellard
        reg = ((modrm >> 3) & 7) + OR_EAX;
1819 367e86e8 bellard
        gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0);
1820 367e86e8 bellard
        if (b == 0x69) {
1821 367e86e8 bellard
            val = insn_get(s, ot);
1822 ba1c6e37 bellard
            gen_op_movl_T1_im(val);
1823 367e86e8 bellard
        } else if (b == 0x6b) {
1824 367e86e8 bellard
            val = insn_get(s, OT_BYTE);
1825 ba1c6e37 bellard
            gen_op_movl_T1_im(val);
1826 367e86e8 bellard
        } else {
1827 367e86e8 bellard
            gen_op_mov_TN_reg[ot][1][reg]();
1828 367e86e8 bellard
        }
1829 367e86e8 bellard
1830 367e86e8 bellard
        if (ot == OT_LONG) {
1831 4b74fe1f bellard
            gen_op_imull_T0_T1();
1832 367e86e8 bellard
        } else {
1833 4b74fe1f bellard
            gen_op_imulw_T0_T1();
1834 367e86e8 bellard
        }
1835 367e86e8 bellard
        gen_op_mov_reg_T0[ot][reg]();
1836 0ecfa993 bellard
        s->cc_op = CC_OP_MUL;
1837 367e86e8 bellard
        break;
1838 1a9353d2 bellard
    case 0x1c0:
1839 1a9353d2 bellard
    case 0x1c1: /* xadd Ev, Gv */
1840 1a9353d2 bellard
        if ((b & 1) == 0)
1841 1a9353d2 bellard
            ot = OT_BYTE;
1842 1a9353d2 bellard
        else
1843 1a9353d2 bellard
            ot = dflag ? OT_LONG : OT_WORD;
1844 1a9353d2 bellard
        modrm = ldub(s->pc++);
1845 1a9353d2 bellard
        reg = (modrm >> 3) & 7;
1846 1a9353d2 bellard
        mod = (modrm >> 6) & 3;
1847 1a9353d2 bellard
        if (mod == 3) {
1848 1a9353d2 bellard
            rm = modrm & 7;
1849 1a9353d2 bellard
            gen_op_mov_TN_reg[ot][0][reg]();
1850 1a9353d2 bellard
            gen_op_mov_TN_reg[ot][1][rm]();
1851 1a9353d2 bellard
            gen_op_addl_T0_T1_cc();
1852 1a9353d2 bellard
            gen_op_mov_reg_T0[ot][rm]();
1853 1a9353d2 bellard
            gen_op_mov_reg_T1[ot][reg]();
1854 1a9353d2 bellard
        } else {
1855 1a9353d2 bellard
            gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
1856 1a9353d2 bellard
            gen_op_mov_TN_reg[ot][0][reg]();
1857 1a9353d2 bellard
            gen_op_ld_T1_A0[ot]();
1858 1a9353d2 bellard
            gen_op_addl_T0_T1_cc();
1859 1a9353d2 bellard
            gen_op_st_T0_A0[ot]();
1860 1a9353d2 bellard
            gen_op_mov_reg_T1[ot][reg]();
1861 1a9353d2 bellard
        }
1862 1a9353d2 bellard
        s->cc_op = CC_OP_ADDB + ot;
1863 1a9353d2 bellard
        break;
1864 1a9353d2 bellard
    case 0x1b0:
1865 1a9353d2 bellard
    case 0x1b1: /* cmpxchg Ev, Gv */
1866 1a9353d2 bellard
        if ((b & 1) == 0)
1867 1a9353d2 bellard
            ot = OT_BYTE;
1868 1a9353d2 bellard
        else
1869 1a9353d2 bellard
            ot = dflag ? OT_LONG : OT_WORD;
1870 1a9353d2 bellard
        modrm = ldub(s->pc++);
1871 1a9353d2 bellard
        reg = (modrm >> 3) & 7;
1872 1a9353d2 bellard
        mod = (modrm >> 6) & 3;
1873 1a9353d2 bellard
        gen_op_mov_TN_reg[ot][1][reg]();
1874 1a9353d2 bellard
        if (mod == 3) {
1875 1a9353d2 bellard
            rm = modrm & 7;
1876 1a9353d2 bellard
            gen_op_mov_TN_reg[ot][0][rm]();
1877 1a9353d2 bellard
            gen_op_cmpxchg_T0_T1_EAX_cc[ot]();
1878 1a9353d2 bellard
            gen_op_mov_reg_T0[ot][rm]();
1879 1a9353d2 bellard
        } else {
1880 1a9353d2 bellard
            gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
1881 1a9353d2 bellard
            gen_op_ld_T0_A0[ot]();
1882 1a9353d2 bellard
            gen_op_cmpxchg_T0_T1_EAX_cc[ot]();
1883 1a9353d2 bellard
            gen_op_st_T0_A0[ot]();
1884 1a9353d2 bellard
        }
1885 1a9353d2 bellard
        s->cc_op = CC_OP_SUBB + ot;
1886 1a9353d2 bellard
        break;
1887 9c605cb1 bellard
    case 0x1c7: /* cmpxchg8b */
1888 9c605cb1 bellard
        modrm = ldub(s->pc++);
1889 9c605cb1 bellard
        mod = (modrm >> 6) & 3;
1890 9c605cb1 bellard
        if (mod == 3)
1891 9c605cb1 bellard
            goto illegal_op;
1892 9c605cb1 bellard
        if (s->cc_op != CC_OP_DYNAMIC)
1893 9c605cb1 bellard
            gen_op_set_cc_op(s->cc_op);
1894 9c605cb1 bellard
        gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
1895 9c605cb1 bellard
        gen_op_cmpxchg8b();
1896 9c605cb1 bellard
        s->cc_op = CC_OP_EFLAGS;
1897 9c605cb1 bellard
        break;
1898 367e86e8 bellard
        
1899 367e86e8 bellard
        /**************************/
1900 367e86e8 bellard
        /* push/pop */
1901 367e86e8 bellard
    case 0x50 ... 0x57: /* push */
1902 927f621e bellard
        gen_op_mov_TN_reg[OT_LONG][0][b & 7]();
1903 dab2ed99 bellard
        gen_push_T0(s);
1904 367e86e8 bellard
        break;
1905 367e86e8 bellard
    case 0x58 ... 0x5f: /* pop */
1906 dab2ed99 bellard
        ot = dflag ? OT_LONG : OT_WORD;
1907 dab2ed99 bellard
        gen_pop_T0(s);
1908 dab2ed99 bellard
        gen_op_mov_reg_T0[ot][b & 7]();
1909 dab2ed99 bellard
        gen_pop_update(s);
1910 367e86e8 bellard
        break;
1911 27362c82 bellard
    case 0x60: /* pusha */
1912 dab2ed99 bellard
        gen_pusha(s);
1913 27362c82 bellard
        break;
1914 27362c82 bellard
    case 0x61: /* popa */
1915 dab2ed99 bellard
        gen_popa(s);
1916 27362c82 bellard
        break;
1917 367e86e8 bellard
    case 0x68: /* push Iv */
1918 367e86e8 bellard
    case 0x6a:
1919 367e86e8 bellard
        ot = dflag ? OT_LONG : OT_WORD;
1920 367e86e8 bellard
        if (b == 0x68)
1921 367e86e8 bellard
            val = insn_get(s, ot);
1922 367e86e8 bellard
        else
1923 367e86e8 bellard
            val = (int8_t)insn_get(s, OT_BYTE);
1924 ba1c6e37 bellard
        gen_op_movl_T0_im(val);
1925 dab2ed99 bellard
        gen_push_T0(s);
1926 367e86e8 bellard
        break;
1927 367e86e8 bellard
    case 0x8f: /* pop Ev */
1928 367e86e8 bellard
        ot = dflag ? OT_LONG : OT_WORD;
1929 367e86e8 bellard
        modrm = ldub(s->pc++);
1930 dab2ed99 bellard
        gen_pop_T0(s);
1931 367e86e8 bellard
        gen_ldst_modrm(s, modrm, ot, OR_TMP0, 1);
1932 dab2ed99 bellard
        gen_pop_update(s);
1933 367e86e8 bellard
        break;
1934 27362c82 bellard
    case 0xc8: /* enter */
1935 27362c82 bellard
        {
1936 27362c82 bellard
            int level;
1937 27362c82 bellard
            val = lduw(s->pc);
1938 27362c82 bellard
            s->pc += 2;
1939 27362c82 bellard
            level = ldub(s->pc++);
1940 dab2ed99 bellard
            gen_enter(s, val, level);
1941 27362c82 bellard
        }
1942 27362c82 bellard
        break;
1943 367e86e8 bellard
    case 0xc9: /* leave */
1944 dab2ed99 bellard
        /* XXX: exception not precise (ESP is update before potential exception) */
1945 dab2ed99 bellard
        if (s->ss32) {
1946 dab2ed99 bellard
            gen_op_mov_TN_reg[OT_LONG][0][R_EBP]();
1947 dab2ed99 bellard
            gen_op_mov_reg_T0[OT_LONG][R_ESP]();
1948 dab2ed99 bellard
        } else {
1949 dab2ed99 bellard
            gen_op_mov_TN_reg[OT_WORD][0][R_EBP]();
1950 dab2ed99 bellard
            gen_op_mov_reg_T0[OT_WORD][R_ESP]();
1951 dab2ed99 bellard
        }
1952 dab2ed99 bellard
        gen_pop_T0(s);
1953 dab2ed99 bellard
        ot = dflag ? OT_LONG : OT_WORD;
1954 dab2ed99 bellard
        gen_op_mov_reg_T0[ot][R_EBP]();
1955 dab2ed99 bellard
        gen_pop_update(s);
1956 367e86e8 bellard
        break;
1957 6dbad63e bellard
    case 0x06: /* push es */
1958 6dbad63e bellard
    case 0x0e: /* push cs */
1959 6dbad63e bellard
    case 0x16: /* push ss */
1960 6dbad63e bellard
    case 0x1e: /* push ds */
1961 6dbad63e bellard
        gen_op_movl_T0_seg(b >> 3);
1962 dab2ed99 bellard
        gen_push_T0(s);
1963 6dbad63e bellard
        break;
1964 6dbad63e bellard
    case 0x1a0: /* push fs */
1965 6dbad63e bellard
    case 0x1a8: /* push gs */
1966 f631ef9b bellard
        gen_op_movl_T0_seg((b >> 3) & 7);
1967 dab2ed99 bellard
        gen_push_T0(s);
1968 6dbad63e bellard
        break;
1969 6dbad63e bellard
    case 0x07: /* pop es */
1970 6dbad63e bellard
    case 0x17: /* pop ss */
1971 6dbad63e bellard
    case 0x1f: /* pop ds */
1972 dab2ed99 bellard
        gen_pop_T0(s);
1973 6dbad63e bellard
        gen_movl_seg_T0(s, b >> 3);
1974 dab2ed99 bellard
        gen_pop_update(s);
1975 6dbad63e bellard
        break;
1976 6dbad63e bellard
    case 0x1a1: /* pop fs */
1977 6dbad63e bellard
    case 0x1a9: /* pop gs */
1978 dab2ed99 bellard
        gen_pop_T0(s);
1979 f631ef9b bellard
        gen_movl_seg_T0(s, (b >> 3) & 7);
1980 dab2ed99 bellard
        gen_pop_update(s);
1981 6dbad63e bellard
        break;
1982 6dbad63e bellard
1983 367e86e8 bellard
        /**************************/
1984 367e86e8 bellard
        /* mov */
1985 367e86e8 bellard
    case 0x88:
1986 367e86e8 bellard
    case 0x89: /* mov Gv, Ev */
1987 367e86e8 bellard
        if ((b & 1) == 0)
1988 367e86e8 bellard
            ot = OT_BYTE;
1989 367e86e8 bellard
        else
1990 367e86e8 bellard
            ot = dflag ? OT_LONG : OT_WORD;
1991 367e86e8 bellard
        modrm = ldub(s->pc++);
1992 367e86e8 bellard
        reg = (modrm >> 3) & 7;
1993 367e86e8 bellard
        
1994 367e86e8 bellard
        /* generate a generic store */
1995 367e86e8 bellard
        gen_ldst_modrm(s, modrm, ot, OR_EAX + reg, 1);
1996 367e86e8 bellard
        break;
1997 367e86e8 bellard
    case 0xc6:
1998 367e86e8 bellard
    case 0xc7: /* mov Ev, Iv */
1999 367e86e8 bellard
        if ((b & 1) == 0)
2000 367e86e8 bellard
            ot = OT_BYTE;
2001 367e86e8 bellard
        else
2002 367e86e8 bellard
            ot = dflag ? OT_LONG : OT_WORD;
2003 367e86e8 bellard
        modrm = ldub(s->pc++);
2004 367e86e8 bellard
        mod = (modrm >> 6) & 3;
2005 0ecfa993 bellard
        if (mod != 3)
2006 0ecfa993 bellard
            gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
2007 367e86e8 bellard
        val = insn_get(s, ot);
2008 ba1c6e37 bellard
        gen_op_movl_T0_im(val);
2009 0ecfa993 bellard
        if (mod != 3)
2010 0ecfa993 bellard
            gen_op_st_T0_A0[ot]();
2011 0ecfa993 bellard
        else
2012 0ecfa993 bellard
            gen_op_mov_reg_T0[ot][modrm & 7]();
2013 367e86e8 bellard
        break;
2014 367e86e8 bellard
    case 0x8a:
2015 367e86e8 bellard
    case 0x8b: /* mov Ev, Gv */
2016 367e86e8 bellard
        if ((b & 1) == 0)
2017 367e86e8 bellard
            ot = OT_BYTE;
2018 367e86e8 bellard
        else
2019 367e86e8 bellard
            ot = dflag ? OT_LONG : OT_WORD;
2020 367e86e8 bellard
        modrm = ldub(s->pc++);
2021 367e86e8 bellard
        reg = (modrm >> 3) & 7;
2022 367e86e8 bellard
        
2023 367e86e8 bellard
        gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0);
2024 367e86e8 bellard
        gen_op_mov_reg_T0[ot][reg]();
2025 367e86e8 bellard
        break;
2026 6dbad63e bellard
    case 0x8e: /* mov seg, Gv */
2027 6dbad63e bellard
        ot = dflag ? OT_LONG : OT_WORD;
2028 6dbad63e bellard
        modrm = ldub(s->pc++);
2029 6dbad63e bellard
        reg = (modrm >> 3) & 7;
2030 6dbad63e bellard
        gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0);
2031 dab2ed99 bellard
        if (reg >= 6 || reg == R_CS)
2032 6dbad63e bellard
            goto illegal_op;
2033 6dbad63e bellard
        gen_movl_seg_T0(s, reg);
2034 6dbad63e bellard
        break;
2035 6dbad63e bellard
    case 0x8c: /* mov Gv, seg */
2036 6dbad63e bellard
        ot = dflag ? OT_LONG : OT_WORD;
2037 6dbad63e bellard
        modrm = ldub(s->pc++);
2038 6dbad63e bellard
        reg = (modrm >> 3) & 7;
2039 6dbad63e bellard
        if (reg >= 6)
2040 6dbad63e bellard
            goto illegal_op;
2041 6dbad63e bellard
        gen_op_movl_T0_seg(reg);
2042 6dbad63e bellard
        gen_ldst_modrm(s, modrm, ot, OR_TMP0, 1);
2043 6dbad63e bellard
        break;
2044 367e86e8 bellard
2045 367e86e8 bellard
    case 0x1b6: /* movzbS Gv, Eb */
2046 367e86e8 bellard
    case 0x1b7: /* movzwS Gv, Eb */
2047 367e86e8 bellard
    case 0x1be: /* movsbS Gv, Eb */
2048 367e86e8 bellard
    case 0x1bf: /* movswS Gv, Eb */
2049 367e86e8 bellard
        {
2050 367e86e8 bellard
            int d_ot;
2051 367e86e8 bellard
            /* d_ot is the size of destination */
2052 367e86e8 bellard
            d_ot = dflag + OT_WORD;
2053 367e86e8 bellard
            /* ot is the size of source */
2054 367e86e8 bellard
            ot = (b & 1) + OT_BYTE;
2055 367e86e8 bellard
            modrm = ldub(s->pc++);
2056 367e86e8 bellard
            reg = ((modrm >> 3) & 7) + OR_EAX;
2057 367e86e8 bellard
            mod = (modrm >> 6) & 3;
2058 367e86e8 bellard
            rm = modrm & 7;
2059 367e86e8 bellard
            
2060 367e86e8 bellard
            if (mod == 3) {
2061 367e86e8 bellard
                gen_op_mov_TN_reg[ot][0][rm]();
2062 367e86e8 bellard
                switch(ot | (b & 8)) {
2063 367e86e8 bellard
                case OT_BYTE:
2064 367e86e8 bellard
                    gen_op_movzbl_T0_T0();
2065 367e86e8 bellard
                    break;
2066 367e86e8 bellard
                case OT_BYTE | 8:
2067 367e86e8 bellard
                    gen_op_movsbl_T0_T0();
2068 367e86e8 bellard
                    break;
2069 367e86e8 bellard
                case OT_WORD:
2070 367e86e8 bellard
                    gen_op_movzwl_T0_T0();
2071 367e86e8 bellard
                    break;
2072 367e86e8 bellard
                default:
2073 367e86e8 bellard
                case OT_WORD | 8:
2074 367e86e8 bellard
                    gen_op_movswl_T0_T0();
2075 367e86e8 bellard
                    break;
2076 367e86e8 bellard
                }
2077 367e86e8 bellard
                gen_op_mov_reg_T0[d_ot][reg]();
2078 367e86e8 bellard
            } else {
2079 367e86e8 bellard
                gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
2080 367e86e8 bellard
                if (b & 8) {
2081 367e86e8 bellard
                    gen_op_lds_T0_A0[ot]();
2082 367e86e8 bellard
                } else {
2083 367e86e8 bellard
                    gen_op_ldu_T0_A0[ot]();
2084 367e86e8 bellard
                }
2085 367e86e8 bellard
                gen_op_mov_reg_T0[d_ot][reg]();
2086 367e86e8 bellard
            }
2087 367e86e8 bellard
        }
2088 367e86e8 bellard
        break;
2089 367e86e8 bellard
2090 367e86e8 bellard
    case 0x8d: /* lea */
2091 367e86e8 bellard
        ot = dflag ? OT_LONG : OT_WORD;
2092 367e86e8 bellard
        modrm = ldub(s->pc++);
2093 367e86e8 bellard
        reg = (modrm >> 3) & 7;
2094 6dbad63e bellard
        /* we must ensure that no segment is added */
2095 9c605cb1 bellard
        s->override = -1;
2096 6dbad63e bellard
        val = s->addseg;
2097 6dbad63e bellard
        s->addseg = 0;
2098 367e86e8 bellard
        gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
2099 6dbad63e bellard
        s->addseg = val;
2100 367e86e8 bellard
        gen_op_mov_reg_A0[ot - OT_WORD][reg]();
2101 367e86e8 bellard
        break;
2102 367e86e8 bellard
        
2103 367e86e8 bellard
    case 0xa0: /* mov EAX, Ov */
2104 367e86e8 bellard
    case 0xa1:
2105 367e86e8 bellard
    case 0xa2: /* mov Ov, EAX */
2106 367e86e8 bellard
    case 0xa3:
2107 367e86e8 bellard
        if ((b & 1) == 0)
2108 367e86e8 bellard
            ot = OT_BYTE;
2109 367e86e8 bellard
        else
2110 367e86e8 bellard
            ot = dflag ? OT_LONG : OT_WORD;
2111 367e86e8 bellard
        if (s->aflag)
2112 367e86e8 bellard
            offset_addr = insn_get(s, OT_LONG);
2113 367e86e8 bellard
        else
2114 367e86e8 bellard
            offset_addr = insn_get(s, OT_WORD);
2115 4b74fe1f bellard
        gen_op_movl_A0_im(offset_addr);
2116 1a9353d2 bellard
        /* handle override */
2117 1a9353d2 bellard
        {
2118 1a9353d2 bellard
            int override, must_add_seg;
2119 1a9353d2 bellard
            must_add_seg = s->addseg;
2120 9c605cb1 bellard
            if (s->override >= 0) {
2121 9c605cb1 bellard
                override = s->override;
2122 1a9353d2 bellard
                must_add_seg = 1;
2123 9c605cb1 bellard
            } else {
2124 9c605cb1 bellard
                override = R_DS;
2125 1a9353d2 bellard
            }
2126 1a9353d2 bellard
            if (must_add_seg) {
2127 1a9353d2 bellard
                gen_op_addl_A0_seg(offsetof(CPUX86State,seg_cache[override].base));
2128 1a9353d2 bellard
            }
2129 1a9353d2 bellard
        }
2130 367e86e8 bellard
        if ((b & 2) == 0) {
2131 367e86e8 bellard
            gen_op_ld_T0_A0[ot]();
2132 367e86e8 bellard
            gen_op_mov_reg_T0[ot][R_EAX]();
2133 367e86e8 bellard
        } else {
2134 367e86e8 bellard
            gen_op_mov_TN_reg[ot][0][R_EAX]();
2135 367e86e8 bellard
            gen_op_st_T0_A0[ot]();
2136 367e86e8 bellard
        }
2137 367e86e8 bellard
        break;
2138 31bb950b bellard
    case 0xd7: /* xlat */
2139 31bb950b bellard
        gen_op_movl_A0_reg[R_EBX]();
2140 31bb950b bellard
        gen_op_addl_A0_AL();
2141 31bb950b bellard
        if (s->aflag == 0)
2142 31bb950b bellard
            gen_op_andl_A0_ffff();
2143 9c605cb1 bellard
        /* handle override */
2144 31bb950b bellard
        {
2145 31bb950b bellard
            int override, must_add_seg;
2146 31bb950b bellard
            must_add_seg = s->addseg;
2147 9c605cb1 bellard
            override = R_DS;
2148 9c605cb1 bellard
            if (s->override >= 0) {
2149 9c605cb1 bellard
                override = s->override;
2150 31bb950b bellard
                must_add_seg = 1;
2151 9c605cb1 bellard
            } else {
2152 9c605cb1 bellard
                override = R_DS;
2153 31bb950b bellard
            }
2154 31bb950b bellard
            if (must_add_seg) {
2155 31bb950b bellard
                gen_op_addl_A0_seg(offsetof(CPUX86State,seg_cache[override].base));
2156 31bb950b bellard
            }
2157 31bb950b bellard
        }
2158 31bb950b bellard
        gen_op_ldub_T0_A0();
2159 31bb950b bellard
        gen_op_mov_reg_T0[OT_BYTE][R_EAX]();
2160 31bb950b bellard
        break;
2161 367e86e8 bellard
    case 0xb0 ... 0xb7: /* mov R, Ib */
2162 367e86e8 bellard
        val = insn_get(s, OT_BYTE);
2163 ba1c6e37 bellard
        gen_op_movl_T0_im(val);
2164 367e86e8 bellard
        gen_op_mov_reg_T0[OT_BYTE][b & 7]();
2165 367e86e8 bellard
        break;
2166 367e86e8 bellard
    case 0xb8 ... 0xbf: /* mov R, Iv */
2167 367e86e8 bellard
        ot = dflag ? OT_LONG : OT_WORD;
2168 367e86e8 bellard
        val = insn_get(s, ot);
2169 367e86e8 bellard
        reg = OR_EAX + (b & 7);
2170 ba1c6e37 bellard
        gen_op_movl_T0_im(val);
2171 367e86e8 bellard
        gen_op_mov_reg_T0[ot][reg]();
2172 367e86e8 bellard
        break;
2173 367e86e8 bellard
2174 367e86e8 bellard
    case 0x91 ... 0x97: /* xchg R, EAX */
2175 367e86e8 bellard
        ot = dflag ? OT_LONG : OT_WORD;
2176 367e86e8 bellard
        reg = b & 7;
2177 1a9353d2 bellard
        rm = R_EAX;
2178 1a9353d2 bellard
        goto do_xchg_reg;
2179 367e86e8 bellard
    case 0x86:
2180 367e86e8 bellard
    case 0x87: /* xchg Ev, Gv */
2181 367e86e8 bellard
        if ((b & 1) == 0)
2182 367e86e8 bellard
            ot = OT_BYTE;
2183 367e86e8 bellard
        else
2184 367e86e8 bellard
            ot = dflag ? OT_LONG : OT_WORD;
2185 367e86e8 bellard
        modrm = ldub(s->pc++);
2186 367e86e8 bellard
        reg = (modrm >> 3) & 7;
2187 1a9353d2 bellard
        mod = (modrm >> 6) & 3;
2188 1a9353d2 bellard
        if (mod == 3) {
2189 1a9353d2 bellard
            rm = modrm & 7;
2190 1a9353d2 bellard
        do_xchg_reg:
2191 1a9353d2 bellard
            gen_op_mov_TN_reg[ot][0][reg]();
2192 1a9353d2 bellard
            gen_op_mov_TN_reg[ot][1][rm]();
2193 1a9353d2 bellard
            gen_op_mov_reg_T0[ot][rm]();
2194 1a9353d2 bellard
            gen_op_mov_reg_T1[ot][reg]();
2195 1a9353d2 bellard
        } else {
2196 1a9353d2 bellard
            gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
2197 1a9353d2 bellard
            gen_op_mov_TN_reg[ot][0][reg]();
2198 31bb950b bellard
            /* for xchg, lock is implicit */
2199 31bb950b bellard
            if (!(prefixes & PREFIX_LOCK))
2200 31bb950b bellard
                gen_op_lock();
2201 1a9353d2 bellard
            gen_op_ld_T1_A0[ot]();
2202 1a9353d2 bellard
            gen_op_st_T0_A0[ot]();
2203 31bb950b bellard
            if (!(prefixes & PREFIX_LOCK))
2204 31bb950b bellard
                gen_op_unlock();
2205 1a9353d2 bellard
            gen_op_mov_reg_T1[ot][reg]();
2206 1a9353d2 bellard
        }
2207 367e86e8 bellard
        break;
2208 6dbad63e bellard
    case 0xc4: /* les Gv */
2209 6dbad63e bellard
        op = R_ES;
2210 6dbad63e bellard
        goto do_lxx;
2211 6dbad63e bellard
    case 0xc5: /* lds Gv */
2212 6dbad63e bellard
        op = R_DS;
2213 6dbad63e bellard
        goto do_lxx;
2214 6dbad63e bellard
    case 0x1b2: /* lss Gv */
2215 6dbad63e bellard
        op = R_SS;
2216 6dbad63e bellard
        goto do_lxx;
2217 6dbad63e bellard
    case 0x1b4: /* lfs Gv */
2218 6dbad63e bellard
        op = R_FS;
2219 6dbad63e bellard
        goto do_lxx;
2220 6dbad63e bellard
    case 0x1b5: /* lgs Gv */
2221 6dbad63e bellard
        op = R_GS;
2222 6dbad63e bellard
    do_lxx:
2223 6dbad63e bellard
        ot = dflag ? OT_LONG : OT_WORD;
2224 6dbad63e bellard
        modrm = ldub(s->pc++);
2225 6dbad63e bellard
        reg = (modrm >> 3) & 7;
2226 6dbad63e bellard
        mod = (modrm >> 6) & 3;
2227 6dbad63e bellard
        if (mod == 3)
2228 6dbad63e bellard
            goto illegal_op;
2229 9c605cb1 bellard
        gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
2230 6dbad63e bellard
        gen_op_ld_T1_A0[ot]();
2231 dc99065b bellard
        gen_op_addl_A0_im(1 << (ot - OT_WORD + 1));
2232 6dbad63e bellard
        /* load the segment first to handle exceptions properly */
2233 6dbad63e bellard
        gen_op_lduw_T0_A0();
2234 6dbad63e bellard
        gen_movl_seg_T0(s, op);
2235 6dbad63e bellard
        /* then put the data */
2236 6dbad63e bellard
        gen_op_mov_reg_T1[ot][reg]();
2237 6dbad63e bellard
        break;
2238 367e86e8 bellard
        
2239 367e86e8 bellard
        /************************/
2240 367e86e8 bellard
        /* shifts */
2241 367e86e8 bellard
    case 0xc0:
2242 367e86e8 bellard
    case 0xc1:
2243 367e86e8 bellard
        /* shift Ev,Ib */
2244 367e86e8 bellard
        shift = 2;
2245 367e86e8 bellard
    grp2:
2246 367e86e8 bellard
        {
2247 367e86e8 bellard
            if ((b & 1) == 0)
2248 367e86e8 bellard
                ot = OT_BYTE;
2249 367e86e8 bellard
            else
2250 367e86e8 bellard
                ot = dflag ? OT_LONG : OT_WORD;
2251 367e86e8 bellard
            
2252 367e86e8 bellard
            modrm = ldub(s->pc++);
2253 367e86e8 bellard
            mod = (modrm >> 6) & 3;
2254 367e86e8 bellard
            rm = modrm & 7;
2255 367e86e8 bellard
            op = (modrm >> 3) & 7;
2256 367e86e8 bellard
            
2257 367e86e8 bellard
            if (mod != 3) {
2258 367e86e8 bellard
                gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
2259 367e86e8 bellard
                gen_op_ld_T0_A0[ot]();
2260 367e86e8 bellard
                opreg = OR_TMP0;
2261 367e86e8 bellard
            } else {
2262 367e86e8 bellard
                opreg = rm + OR_EAX;
2263 367e86e8 bellard
            }
2264 367e86e8 bellard
2265 367e86e8 bellard
            /* simpler op */
2266 367e86e8 bellard
            if (shift == 0) {
2267 367e86e8 bellard
                gen_shift(s, op, ot, opreg, OR_ECX);
2268 367e86e8 bellard
            } else {
2269 367e86e8 bellard
                if (shift == 2) {
2270 367e86e8 bellard
                    shift = ldub(s->pc++);
2271 367e86e8 bellard
                }
2272 367e86e8 bellard
                gen_shifti(s, op, ot, opreg, shift);
2273 367e86e8 bellard
            }
2274 367e86e8 bellard
2275 367e86e8 bellard
            if (mod != 3) {
2276 367e86e8 bellard
                gen_op_st_T0_A0[ot]();
2277 367e86e8 bellard
            }
2278 367e86e8 bellard
        }
2279 367e86e8 bellard
        break;
2280 367e86e8 bellard
    case 0xd0:
2281 367e86e8 bellard
    case 0xd1:
2282 367e86e8 bellard
        /* shift Ev,1 */
2283 367e86e8 bellard
        shift = 1;
2284 367e86e8 bellard
        goto grp2;
2285 367e86e8 bellard
    case 0xd2:
2286 367e86e8 bellard
    case 0xd3:
2287 367e86e8 bellard
        /* shift Ev,cl */
2288 367e86e8 bellard
        shift = 0;
2289 367e86e8 bellard
        goto grp2;
2290 367e86e8 bellard
2291 d57c4e01 bellard
    case 0x1a4: /* shld imm */
2292 d57c4e01 bellard
        op = 0;
2293 d57c4e01 bellard
        shift = 1;
2294 d57c4e01 bellard
        goto do_shiftd;
2295 d57c4e01 bellard
    case 0x1a5: /* shld cl */
2296 d57c4e01 bellard
        op = 0;
2297 d57c4e01 bellard
        shift = 0;
2298 d57c4e01 bellard
        goto do_shiftd;
2299 d57c4e01 bellard
    case 0x1ac: /* shrd imm */
2300 d57c4e01 bellard
        op = 1;
2301 d57c4e01 bellard
        shift = 1;
2302 d57c4e01 bellard
        goto do_shiftd;
2303 d57c4e01 bellard
    case 0x1ad: /* shrd cl */
2304 d57c4e01 bellard
        op = 1;
2305 d57c4e01 bellard
        shift = 0;
2306 d57c4e01 bellard
    do_shiftd:
2307 d57c4e01 bellard
        ot = dflag ? OT_LONG : OT_WORD;
2308 d57c4e01 bellard
        modrm = ldub(s->pc++);
2309 d57c4e01 bellard
        mod = (modrm >> 6) & 3;
2310 d57c4e01 bellard
        rm = modrm & 7;
2311 d57c4e01 bellard
        reg = (modrm >> 3) & 7;
2312 d57c4e01 bellard
        
2313 d57c4e01 bellard
        if (mod != 3) {
2314 d57c4e01 bellard
            gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
2315 d57c4e01 bellard
            gen_op_ld_T0_A0[ot]();
2316 d57c4e01 bellard
        } else {
2317 d57c4e01 bellard
            gen_op_mov_TN_reg[ot][0][rm]();
2318 d57c4e01 bellard
        }
2319 d57c4e01 bellard
        gen_op_mov_TN_reg[ot][1][reg]();
2320 d57c4e01 bellard
        
2321 d57c4e01 bellard
        if (shift) {
2322 d57c4e01 bellard
            val = ldub(s->pc++);
2323 d57c4e01 bellard
            val &= 0x1f;
2324 d57c4e01 bellard
            if (val) {
2325 d57c4e01 bellard
                gen_op_shiftd_T0_T1_im_cc[ot - OT_WORD][op](val);
2326 d57c4e01 bellard
                if (op == 0 && ot != OT_WORD)
2327 d57c4e01 bellard
                    s->cc_op = CC_OP_SHLB + ot;
2328 d57c4e01 bellard
                else
2329 d57c4e01 bellard
                    s->cc_op = CC_OP_SARB + ot;
2330 d57c4e01 bellard
            }
2331 d57c4e01 bellard
        } else {
2332 d57c4e01 bellard
            if (s->cc_op != CC_OP_DYNAMIC)
2333 d57c4e01 bellard
                gen_op_set_cc_op(s->cc_op);
2334 d57c4e01 bellard
            gen_op_shiftd_T0_T1_ECX_cc[ot - OT_WORD][op]();
2335 d57c4e01 bellard
            s->cc_op = CC_OP_DYNAMIC; /* cannot predict flags after */
2336 d57c4e01 bellard
        }
2337 d57c4e01 bellard
        if (mod != 3) {
2338 d57c4e01 bellard
            gen_op_st_T0_A0[ot]();
2339 d57c4e01 bellard
        } else {
2340 d57c4e01 bellard
            gen_op_mov_reg_T0[ot][rm]();
2341 d57c4e01 bellard
        }
2342 d57c4e01 bellard
        break;
2343 d57c4e01 bellard
2344 367e86e8 bellard
        /************************/
2345 367e86e8 bellard
        /* floats */
2346 367e86e8 bellard
    case 0xd8 ... 0xdf: 
2347 367e86e8 bellard
        modrm = ldub(s->pc++);
2348 367e86e8 bellard
        mod = (modrm >> 6) & 3;
2349 367e86e8 bellard
        rm = modrm & 7;
2350 367e86e8 bellard
        op = ((b & 7) << 3) | ((modrm >> 3) & 7);
2351 367e86e8 bellard
        
2352 367e86e8 bellard
        if (mod != 3) {
2353 367e86e8 bellard
            /* memory op */
2354 367e86e8 bellard
            gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
2355 367e86e8 bellard
            switch(op) {
2356 367e86e8 bellard
            case 0x00 ... 0x07: /* fxxxs */
2357 367e86e8 bellard
            case 0x10 ... 0x17: /* fixxxl */
2358 367e86e8 bellard
            case 0x20 ... 0x27: /* fxxxl */
2359 367e86e8 bellard
            case 0x30 ... 0x37: /* fixxx */
2360 367e86e8 bellard
                {
2361 927f621e bellard
                    int op1;
2362 927f621e bellard
                    op1 = op & 7;
2363 367e86e8 bellard
2364 367e86e8 bellard
                    switch(op >> 4) {
2365 367e86e8 bellard
                    case 0:
2366 927f621e bellard
                        gen_op_flds_FT0_A0();
2367 367e86e8 bellard
                        break;
2368 367e86e8 bellard
                    case 1:
2369 927f621e bellard
                        gen_op_fildl_FT0_A0();
2370 367e86e8 bellard
                        break;
2371 367e86e8 bellard
                    case 2:
2372 927f621e bellard
                        gen_op_fldl_FT0_A0();
2373 367e86e8 bellard
                        break;
2374 367e86e8 bellard
                    case 3:
2375 367e86e8 bellard
                    default:
2376 927f621e bellard
                        gen_op_fild_FT0_A0();
2377 367e86e8 bellard
                        break;
2378 367e86e8 bellard
                    }
2379 367e86e8 bellard
                    
2380 927f621e bellard
                    gen_op_fp_arith_ST0_FT0[op1]();
2381 927f621e bellard
                    if (op1 == 3) {
2382 367e86e8 bellard
                        /* fcomp needs pop */
2383 927f621e bellard
                        gen_op_fpop();
2384 367e86e8 bellard
                    }
2385 367e86e8 bellard
                }
2386 367e86e8 bellard
                break;
2387 367e86e8 bellard
            case 0x08: /* flds */
2388 367e86e8 bellard
            case 0x0a: /* fsts */
2389 367e86e8 bellard
            case 0x0b: /* fstps */
2390 367e86e8 bellard
            case 0x18: /* fildl */
2391 367e86e8 bellard
            case 0x1a: /* fistl */
2392 367e86e8 bellard
            case 0x1b: /* fistpl */
2393 367e86e8 bellard
            case 0x28: /* fldl */
2394 367e86e8 bellard
            case 0x2a: /* fstl */
2395 367e86e8 bellard
            case 0x2b: /* fstpl */
2396 367e86e8 bellard
            case 0x38: /* filds */
2397 367e86e8 bellard
            case 0x3a: /* fists */
2398 367e86e8 bellard
            case 0x3b: /* fistps */
2399 367e86e8 bellard
                
2400 367e86e8 bellard
                switch(op & 7) {
2401 367e86e8 bellard
                case 0:
2402 927f621e bellard
                    gen_op_fpush();
2403 927f621e bellard
                    switch(op >> 4) {
2404 927f621e bellard
                    case 0:
2405 927f621e bellard
                        gen_op_flds_ST0_A0();
2406 927f621e bellard
                        break;
2407 927f621e bellard
                    case 1:
2408 927f621e bellard
                        gen_op_fildl_ST0_A0();
2409 927f621e bellard
                        break;
2410 927f621e bellard
                    case 2:
2411 927f621e bellard
                        gen_op_fldl_ST0_A0();
2412 927f621e bellard
                        break;
2413 927f621e bellard
                    case 3:
2414 927f621e bellard
                    default:
2415 927f621e bellard
                        gen_op_fild_ST0_A0();
2416 927f621e bellard
                        break;
2417 367e86e8 bellard
                    }
2418 367e86e8 bellard
                    break;
2419 367e86e8 bellard
                default:
2420 927f621e bellard
                    switch(op >> 4) {
2421 927f621e bellard
                    case 0:
2422 927f621e bellard
                        gen_op_fsts_ST0_A0();
2423 927f621e bellard
                        break;
2424 927f621e bellard
                    case 1:
2425 927f621e bellard
                        gen_op_fistl_ST0_A0();
2426 927f621e bellard
                        break;
2427 927f621e bellard
                    case 2:
2428 927f621e bellard
                        gen_op_fstl_ST0_A0();
2429 927f621e bellard
                        break;
2430 927f621e bellard
                    case 3:
2431 927f621e bellard
                    default:
2432 927f621e bellard
                        gen_op_fist_ST0_A0();
2433 927f621e bellard
                        break;
2434 367e86e8 bellard
                    }
2435 367e86e8 bellard
                    if ((op & 7) == 3)
2436 927f621e bellard
                        gen_op_fpop();
2437 367e86e8 bellard
                    break;
2438 367e86e8 bellard
                }
2439 367e86e8 bellard
                break;
2440 4b74fe1f bellard
            case 0x0d: /* fldcw mem */
2441 4b74fe1f bellard
                gen_op_fldcw_A0();
2442 4b74fe1f bellard
                break;
2443 4b74fe1f bellard
            case 0x0f: /* fnstcw mem */
2444 4b74fe1f bellard
                gen_op_fnstcw_A0();
2445 4b74fe1f bellard
                break;
2446 77f8dd5a bellard
            case 0x1d: /* fldt mem */
2447 77f8dd5a bellard
                gen_op_fpush();
2448 77f8dd5a bellard
                gen_op_fldt_ST0_A0();
2449 77f8dd5a bellard
                break;
2450 77f8dd5a bellard
            case 0x1f: /* fstpt mem */
2451 77f8dd5a bellard
                gen_op_fstt_ST0_A0();
2452 77f8dd5a bellard
                gen_op_fpop();
2453 77f8dd5a bellard
                break;
2454 367e86e8 bellard
            case 0x2f: /* fnstsw mem */
2455 4b74fe1f bellard
                gen_op_fnstsw_A0();
2456 367e86e8 bellard
                break;
2457 367e86e8 bellard
            case 0x3c: /* fbld */
2458 77f8dd5a bellard
                gen_op_fpush();
2459 1017ebe9 bellard
                gen_op_fbld_ST0_A0();
2460 77f8dd5a bellard
                break;
2461 367e86e8 bellard
            case 0x3e: /* fbstp */
2462 77f8dd5a bellard
                gen_op_fbst_ST0_A0();
2463 77f8dd5a bellard
                gen_op_fpop();
2464 77f8dd5a bellard
                break;
2465 367e86e8 bellard
            case 0x3d: /* fildll */
2466 927f621e bellard
                gen_op_fpush();
2467 927f621e bellard
                gen_op_fildll_ST0_A0();
2468 367e86e8 bellard
                break;
2469 367e86e8 bellard
            case 0x3f: /* fistpll */
2470 927f621e bellard
                gen_op_fistll_ST0_A0();
2471 927f621e bellard
                gen_op_fpop();
2472 367e86e8 bellard
                break;
2473 367e86e8 bellard
            default:
2474 1a9353d2 bellard
                goto illegal_op;
2475 367e86e8 bellard
            }
2476 367e86e8 bellard
        } else {
2477 367e86e8 bellard
            /* register float ops */
2478 927f621e bellard
            opreg = rm;
2479 367e86e8 bellard
2480 367e86e8 bellard
            switch(op) {
2481 367e86e8 bellard
            case 0x08: /* fld sti */
2482 927f621e bellard
                gen_op_fpush();
2483 927f621e bellard
                gen_op_fmov_ST0_STN((opreg + 1) & 7);
2484 367e86e8 bellard
                break;
2485 367e86e8 bellard
            case 0x09: /* fxchg sti */
2486 77f8dd5a bellard
                gen_op_fxchg_ST0_STN(opreg);
2487 367e86e8 bellard
                break;
2488 367e86e8 bellard
            case 0x0a: /* grp d9/2 */
2489 367e86e8 bellard
                switch(rm) {
2490 367e86e8 bellard
                case 0: /* fnop */
2491 367e86e8 bellard
                    break;
2492 367e86e8 bellard
                default:
2493 1a9353d2 bellard
                    goto illegal_op;
2494 367e86e8 bellard
                }
2495 367e86e8 bellard
                break;
2496 367e86e8 bellard
            case 0x0c: /* grp d9/4 */
2497 367e86e8 bellard
                switch(rm) {
2498 367e86e8 bellard
                case 0: /* fchs */
2499 927f621e bellard
                    gen_op_fchs_ST0();
2500 367e86e8 bellard
                    break;
2501 367e86e8 bellard
                case 1: /* fabs */
2502 927f621e bellard
                    gen_op_fabs_ST0();
2503 367e86e8 bellard
                    break;
2504 367e86e8 bellard
                case 4: /* ftst */
2505 927f621e bellard
                    gen_op_fldz_FT0();
2506 927f621e bellard
                    gen_op_fcom_ST0_FT0();
2507 367e86e8 bellard
                    break;
2508 367e86e8 bellard
                case 5: /* fxam */
2509 927f621e bellard
                    gen_op_fxam_ST0();
2510 367e86e8 bellard
                    break;
2511 367e86e8 bellard
                default:
2512 1a9353d2 bellard
                    goto illegal_op;
2513 367e86e8 bellard
                }
2514 367e86e8 bellard
                break;
2515 367e86e8 bellard
            case 0x0d: /* grp d9/5 */
2516 367e86e8 bellard
                {
2517 927f621e bellard
                    switch(rm) {
2518 927f621e bellard
                    case 0:
2519 77f8dd5a bellard
                        gen_op_fpush();
2520 927f621e bellard
                        gen_op_fld1_ST0();
2521 927f621e bellard
                        break;
2522 927f621e bellard
                    case 1:
2523 77f8dd5a bellard
                        gen_op_fpush();
2524 77f8dd5a bellard
                        gen_op_fldl2t_ST0();
2525 927f621e bellard
                        break;
2526 927f621e bellard
                    case 2:
2527 77f8dd5a bellard
                        gen_op_fpush();
2528 77f8dd5a bellard
                        gen_op_fldl2e_ST0();
2529 927f621e bellard
                        break;
2530 927f621e bellard
                    case 3:
2531 77f8dd5a bellard
                        gen_op_fpush();
2532 927f621e bellard
                        gen_op_fldpi_ST0();
2533 927f621e bellard
                        break;
2534 927f621e bellard
                    case 4:
2535 77f8dd5a bellard
                        gen_op_fpush();
2536 927f621e bellard
                        gen_op_fldlg2_ST0();
2537 927f621e bellard
                        break;
2538 927f621e bellard
                    case 5:
2539 77f8dd5a bellard
                        gen_op_fpush();
2540 927f621e bellard
                        gen_op_fldln2_ST0();
2541 927f621e bellard
                        break;
2542 927f621e bellard
                    case 6:
2543 77f8dd5a bellard
                        gen_op_fpush();
2544 927f621e bellard
                        gen_op_fldz_ST0();
2545 927f621e bellard
                        break;
2546 927f621e bellard
                    default:
2547 1a9353d2 bellard
                        goto illegal_op;
2548 367e86e8 bellard
                    }
2549 367e86e8 bellard
                }
2550 367e86e8 bellard
                break;
2551 367e86e8 bellard
            case 0x0e: /* grp d9/6 */
2552 367e86e8 bellard
                switch(rm) {
2553 367e86e8 bellard
                case 0: /* f2xm1 */
2554 927f621e bellard
                    gen_op_f2xm1();
2555 367e86e8 bellard
                    break;
2556 367e86e8 bellard
                case 1: /* fyl2x */
2557 927f621e bellard
                    gen_op_fyl2x();
2558 367e86e8 bellard
                    break;
2559 367e86e8 bellard
                case 2: /* fptan */
2560 927f621e bellard
                    gen_op_fptan();
2561 367e86e8 bellard
                    break;
2562 367e86e8 bellard
                case 3: /* fpatan */
2563 927f621e bellard
                    gen_op_fpatan();
2564 367e86e8 bellard
                    break;
2565 367e86e8 bellard
                case 4: /* fxtract */
2566 927f621e bellard
                    gen_op_fxtract();
2567 367e86e8 bellard
                    break;
2568 367e86e8 bellard
                case 5: /* fprem1 */
2569 927f621e bellard
                    gen_op_fprem1();
2570 367e86e8 bellard
                    break;
2571 367e86e8 bellard
                case 6: /* fdecstp */
2572 927f621e bellard
                    gen_op_fdecstp();
2573 367e86e8 bellard
                    break;
2574 367e86e8 bellard
                default:
2575 927f621e bellard
                case 7: /* fincstp */
2576 927f621e bellard
                    gen_op_fincstp();
2577 367e86e8 bellard
                    break;
2578 367e86e8 bellard
                }
2579 367e86e8 bellard
                break;
2580 367e86e8 bellard
            case 0x0f: /* grp d9/7 */
2581 367e86e8 bellard
                switch(rm) {
2582 367e86e8 bellard
                case 0: /* fprem */
2583 927f621e bellard
                    gen_op_fprem();
2584 367e86e8 bellard
                    break;
2585 367e86e8 bellard
                case 1: /* fyl2xp1 */
2586 927f621e bellard
                    gen_op_fyl2xp1();
2587 927f621e bellard
                    break;
2588 927f621e bellard
                case 2: /* fsqrt */
2589 927f621e bellard
                    gen_op_fsqrt();
2590 367e86e8 bellard
                    break;
2591 367e86e8 bellard
                case 3: /* fsincos */
2592 927f621e bellard
                    gen_op_fsincos();
2593 367e86e8 bellard
                    break;
2594 367e86e8 bellard
                case 5: /* fscale */
2595 927f621e bellard
                    gen_op_fscale();
2596 367e86e8 bellard
                    break;
2597 367e86e8 bellard
                case 4: /* frndint */
2598 927f621e bellard
                    gen_op_frndint();
2599 927f621e bellard
                    break;
2600 367e86e8 bellard
                case 6: /* fsin */
2601 927f621e bellard
                    gen_op_fsin();
2602 927f621e bellard
                    break;
2603 367e86e8 bellard
                default:
2604 367e86e8 bellard
                case 7: /* fcos */
2605 927f621e bellard
                    gen_op_fcos();
2606 367e86e8 bellard
                    break;
2607 367e86e8 bellard
                }
2608 367e86e8 bellard
                break;
2609 367e86e8 bellard
            case 0x00: case 0x01: case 0x04 ... 0x07: /* fxxx st, sti */
2610 367e86e8 bellard
            case 0x20: case 0x21: case 0x24 ... 0x27: /* fxxx sti, st */
2611 367e86e8 bellard
            case 0x30: case 0x31: case 0x34 ... 0x37: /* fxxxp sti, st */
2612 367e86e8 bellard
                {
2613 927f621e bellard
                    int op1;
2614 367e86e8 bellard
                    
2615 927f621e bellard
                    op1 = op & 7;
2616 367e86e8 bellard
                    if (op >= 0x20) {
2617 927f621e bellard
                        gen_op_fp_arith_STN_ST0[op1](opreg);
2618 77f8dd5a bellard
                        if (op >= 0x30)
2619 77f8dd5a bellard
                            gen_op_fpop();
2620 367e86e8 bellard
                    } else {
2621 927f621e bellard
                        gen_op_fmov_FT0_STN(opreg);
2622 927f621e bellard
                        gen_op_fp_arith_ST0_FT0[op1]();
2623 367e86e8 bellard
                    }
2624 367e86e8 bellard
                }
2625 367e86e8 bellard
                break;
2626 367e86e8 bellard
            case 0x02: /* fcom */
2627 927f621e bellard
                gen_op_fmov_FT0_STN(opreg);
2628 927f621e bellard
                gen_op_fcom_ST0_FT0();
2629 367e86e8 bellard
                break;
2630 367e86e8 bellard
            case 0x03: /* fcomp */
2631 927f621e bellard
                gen_op_fmov_FT0_STN(opreg);
2632 927f621e bellard
                gen_op_fcom_ST0_FT0();
2633 927f621e bellard
                gen_op_fpop();
2634 367e86e8 bellard
                break;
2635 367e86e8 bellard
            case 0x15: /* da/5 */
2636 367e86e8 bellard
                switch(rm) {
2637 367e86e8 bellard
                case 1: /* fucompp */
2638 927f621e bellard
                    gen_op_fmov_FT0_STN(1);
2639 77f8dd5a bellard
                    gen_op_fucom_ST0_FT0();
2640 927f621e bellard
                    gen_op_fpop();
2641 927f621e bellard
                    gen_op_fpop();
2642 367e86e8 bellard
                    break;
2643 367e86e8 bellard
                default:
2644 1a9353d2 bellard
                    goto illegal_op;
2645 1a9353d2 bellard
                }
2646 1a9353d2 bellard
                break;
2647 1a9353d2 bellard
            case 0x1c:
2648 1a9353d2 bellard
                switch(rm) {
2649 1a9353d2 bellard
                case 2: /* fclex */
2650 1a9353d2 bellard
                    gen_op_fclex();
2651 1a9353d2 bellard
                    break;
2652 1a9353d2 bellard
                case 3: /* fninit */
2653 1a9353d2 bellard
                    gen_op_fninit();
2654 1a9353d2 bellard
                    break;
2655 1a9353d2 bellard
                default:
2656 1a9353d2 bellard
                    goto illegal_op;
2657 367e86e8 bellard
                }
2658 367e86e8 bellard
                break;
2659 367e86e8 bellard
            case 0x2a: /* fst sti */
2660 927f621e bellard
                gen_op_fmov_STN_ST0(opreg);
2661 367e86e8 bellard
                break;
2662 367e86e8 bellard
            case 0x2b: /* fstp sti */
2663 927f621e bellard
                gen_op_fmov_STN_ST0(opreg);
2664 927f621e bellard
                gen_op_fpop();
2665 367e86e8 bellard
                break;
2666 77f8dd5a bellard
            case 0x2c: /* fucom st(i) */
2667 77f8dd5a bellard
                gen_op_fmov_FT0_STN(opreg);
2668 77f8dd5a bellard
                gen_op_fucom_ST0_FT0();
2669 77f8dd5a bellard
                break;
2670 77f8dd5a bellard
            case 0x2d: /* fucomp st(i) */
2671 77f8dd5a bellard
                gen_op_fmov_FT0_STN(opreg);
2672 77f8dd5a bellard
                gen_op_fucom_ST0_FT0();
2673 77f8dd5a bellard
                gen_op_fpop();
2674 77f8dd5a bellard
                break;
2675 367e86e8 bellard
            case 0x33: /* de/3 */
2676 367e86e8 bellard
                switch(rm) {
2677 367e86e8 bellard
                case 1: /* fcompp */
2678 927f621e bellard
                    gen_op_fmov_FT0_STN(1);
2679 927f621e bellard
                    gen_op_fcom_ST0_FT0();
2680 927f621e bellard
                    gen_op_fpop();
2681 927f621e bellard
                    gen_op_fpop();
2682 367e86e8 bellard
                    break;
2683 367e86e8 bellard
                default:
2684 1a9353d2 bellard
                    goto illegal_op;
2685 367e86e8 bellard
                }
2686 367e86e8 bellard
                break;
2687 367e86e8 bellard
            case 0x3c: /* df/4 */
2688 367e86e8 bellard
                switch(rm) {
2689 367e86e8 bellard
                case 0:
2690 77f8dd5a bellard
                    gen_op_fnstsw_EAX();
2691 367e86e8 bellard
                    break;
2692 367e86e8 bellard
                default:
2693 1a9353d2 bellard
                    goto illegal_op;
2694 367e86e8 bellard
                }
2695 367e86e8 bellard
                break;
2696 367e86e8 bellard
            default:
2697 1a9353d2 bellard
                goto illegal_op;
2698 367e86e8 bellard
            }
2699 367e86e8 bellard
        }
2700 367e86e8 bellard
        break;
2701 367e86e8 bellard
        /************************/
2702 367e86e8 bellard
        /* string ops */
2703 9c605cb1 bellard
2704 367e86e8 bellard
    case 0xa4: /* movsS */
2705 367e86e8 bellard
    case 0xa5:
2706 367e86e8 bellard
        if ((b & 1) == 0)
2707 367e86e8 bellard
            ot = OT_BYTE;
2708 367e86e8 bellard
        else
2709 367e86e8 bellard
            ot = dflag ? OT_LONG : OT_WORD;
2710 9c605cb1 bellard
2711 367e86e8 bellard
        if (prefixes & PREFIX_REPZ) {
2712 9c605cb1 bellard
            gen_string_ds(s, ot, gen_op_movs + 9);
2713 367e86e8 bellard
        } else {
2714 9c605cb1 bellard
            gen_string_ds(s, ot, gen_op_movs);
2715 367e86e8 bellard
        }
2716 367e86e8 bellard
        break;
2717 367e86e8 bellard
        
2718 367e86e8 bellard
    case 0xaa: /* stosS */
2719 367e86e8 bellard
    case 0xab:
2720 367e86e8 bellard
        if ((b & 1) == 0)
2721 367e86e8 bellard
            ot = OT_BYTE;
2722 367e86e8 bellard
        else
2723 367e86e8 bellard
            ot = dflag ? OT_LONG : OT_WORD;
2724 9c605cb1 bellard
2725 367e86e8 bellard
        if (prefixes & PREFIX_REPZ) {
2726 9c605cb1 bellard
            gen_string_es(s, ot, gen_op_stos + 9);
2727 367e86e8 bellard
        } else {
2728 9c605cb1 bellard
            gen_string_es(s, ot, gen_op_stos);
2729 367e86e8 bellard
        }
2730 367e86e8 bellard
        break;
2731 367e86e8 bellard
    case 0xac: /* lodsS */
2732 367e86e8 bellard
    case 0xad:
2733 367e86e8 bellard
        if ((b & 1) == 0)
2734 367e86e8 bellard
            ot = OT_BYTE;
2735 367e86e8 bellard
        else
2736 367e86e8 bellard
            ot = dflag ? OT_LONG : OT_WORD;
2737 367e86e8 bellard
        if (prefixes & PREFIX_REPZ) {
2738 9c605cb1 bellard
            gen_string_ds(s, ot, gen_op_lods + 9);
2739 367e86e8 bellard
        } else {
2740 9c605cb1 bellard
            gen_string_ds(s, ot, gen_op_lods);
2741 367e86e8 bellard
        }
2742 367e86e8 bellard
        break;
2743 367e86e8 bellard
    case 0xae: /* scasS */
2744 367e86e8 bellard
    case 0xaf:
2745 367e86e8 bellard
        if ((b & 1) == 0)
2746 367e86e8 bellard
            ot = OT_BYTE;
2747 367e86e8 bellard
        else
2748 9c605cb1 bellard
                ot = dflag ? OT_LONG : OT_WORD;
2749 367e86e8 bellard
        if (prefixes & PREFIX_REPNZ) {
2750 4b74fe1f bellard
            if (s->cc_op != CC_OP_DYNAMIC)
2751 4b74fe1f bellard
                gen_op_set_cc_op(s->cc_op);
2752 9c605cb1 bellard
            gen_string_es(s, ot, gen_op_scas + 9 * 2);
2753 4b74fe1f bellard
            s->cc_op = CC_OP_DYNAMIC; /* cannot predict flags after */
2754 367e86e8 bellard
        } else if (prefixes & PREFIX_REPZ) {
2755 4b74fe1f bellard
            if (s->cc_op != CC_OP_DYNAMIC)
2756 4b74fe1f bellard
                gen_op_set_cc_op(s->cc_op);
2757 9c605cb1 bellard
            gen_string_es(s, ot, gen_op_scas + 9);
2758 4b74fe1f bellard
            s->cc_op = CC_OP_DYNAMIC; /* cannot predict flags after */
2759 367e86e8 bellard
        } else {
2760 9c605cb1 bellard
            gen_string_es(s, ot, gen_op_scas);
2761 4b74fe1f bellard
            s->cc_op = CC_OP_SUBB + ot;
2762 367e86e8 bellard
        }
2763 367e86e8 bellard
        break;
2764 367e86e8 bellard
2765 367e86e8 bellard
    case 0xa6: /* cmpsS */
2766 367e86e8 bellard
    case 0xa7:
2767 367e86e8 bellard
        if ((b & 1) == 0)
2768 367e86e8 bellard
            ot = OT_BYTE;
2769 367e86e8 bellard
        else
2770 367e86e8 bellard
            ot = dflag ? OT_LONG : OT_WORD;
2771 367e86e8 bellard
        if (prefixes & PREFIX_REPNZ) {
2772 4b74fe1f bellard
            if (s->cc_op != CC_OP_DYNAMIC)
2773 4b74fe1f bellard
                gen_op_set_cc_op(s->cc_op);
2774 9c605cb1 bellard
            gen_string_ds(s, ot, gen_op_cmps + 9 * 2);
2775 4b74fe1f bellard
            s->cc_op = CC_OP_DYNAMIC; /* cannot predict flags after */
2776 367e86e8 bellard
        } else if (prefixes & PREFIX_REPZ) {
2777 4b74fe1f bellard
            if (s->cc_op != CC_OP_DYNAMIC)
2778 4b74fe1f bellard
                gen_op_set_cc_op(s->cc_op);
2779 9c605cb1 bellard
            gen_string_ds(s, ot, gen_op_cmps + 9);
2780 4b74fe1f bellard
            s->cc_op = CC_OP_DYNAMIC; /* cannot predict flags after */
2781 367e86e8 bellard
        } else {
2782 9c605cb1 bellard
            gen_string_ds(s, ot, gen_op_cmps);
2783 4b74fe1f bellard
            s->cc_op = CC_OP_SUBB + ot;
2784 367e86e8 bellard
        }
2785 367e86e8 bellard
        break;
2786 367e86e8 bellard
    case 0x6c: /* insS */
2787 367e86e8 bellard
    case 0x6d:
2788 982b4315 bellard
        if (s->cpl > s->iopl || s->vm86) {
2789 982b4315 bellard
            /* NOTE: even for (E)CX = 0 the exception is raised */
2790 c50c0c3f bellard
            gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
2791 367e86e8 bellard
        } else {
2792 982b4315 bellard
            if ((b & 1) == 0)
2793 982b4315 bellard
                ot = OT_BYTE;
2794 982b4315 bellard
            else
2795 982b4315 bellard
                ot = dflag ? OT_LONG : OT_WORD;
2796 982b4315 bellard
            if (prefixes & PREFIX_REPZ) {
2797 982b4315 bellard
                gen_string_es(s, ot, gen_op_ins + 9);
2798 982b4315 bellard
            } else {
2799 982b4315 bellard
                gen_string_es(s, ot, gen_op_ins);
2800 982b4315 bellard
            }
2801 367e86e8 bellard
        }
2802 367e86e8 bellard
        break;
2803 367e86e8 bellard
    case 0x6e: /* outsS */
2804 367e86e8 bellard
    case 0x6f:
2805 982b4315 bellard
        if (s->cpl > s->iopl || s->vm86) {
2806 982b4315 bellard
            /* NOTE: even for (E)CX = 0 the exception is raised */
2807 c50c0c3f bellard
            gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
2808 367e86e8 bellard
        } else {
2809 982b4315 bellard
            if ((b & 1) == 0)
2810 982b4315 bellard
                ot = OT_BYTE;
2811 982b4315 bellard
            else
2812 982b4315 bellard
                ot = dflag ? OT_LONG : OT_WORD;
2813 982b4315 bellard
            if (prefixes & PREFIX_REPZ) {
2814 982b4315 bellard
                gen_string_ds(s, ot, gen_op_outs + 9);
2815 982b4315 bellard
            } else {
2816 982b4315 bellard
                gen_string_ds(s, ot, gen_op_outs);
2817 982b4315 bellard
            }
2818 367e86e8 bellard
        }
2819 367e86e8 bellard
        break;
2820 9c605cb1 bellard
2821 9c605cb1 bellard
        /************************/
2822 9c605cb1 bellard
        /* port I/O */
2823 ba1c6e37 bellard
    case 0xe4:
2824 ba1c6e37 bellard
    case 0xe5:
2825 982b4315 bellard
        if (s->cpl > s->iopl || s->vm86) {
2826 c50c0c3f bellard
            gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
2827 982b4315 bellard
        } else {
2828 982b4315 bellard
            if ((b & 1) == 0)
2829 982b4315 bellard
                ot = OT_BYTE;
2830 982b4315 bellard
            else
2831 982b4315 bellard
                ot = dflag ? OT_LONG : OT_WORD;
2832 982b4315 bellard
            val = ldub(s->pc++);
2833 982b4315 bellard
            gen_op_movl_T0_im(val);
2834 982b4315 bellard
            gen_op_in[ot]();
2835 982b4315 bellard
            gen_op_mov_reg_T1[ot][R_EAX]();
2836 982b4315 bellard
        }
2837 ba1c6e37 bellard
        break;
2838 ba1c6e37 bellard
    case 0xe6:
2839 ba1c6e37 bellard
    case 0xe7:
2840 982b4315 bellard
        if (s->cpl > s->iopl || s->vm86) {
2841 c50c0c3f bellard
            gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
2842 982b4315 bellard
        } else {
2843 982b4315 bellard
            if ((b & 1) == 0)
2844 982b4315 bellard
                ot = OT_BYTE;
2845 982b4315 bellard
            else
2846 982b4315 bellard
                ot = dflag ? OT_LONG : OT_WORD;
2847 982b4315 bellard
            val = ldub(s->pc++);
2848 982b4315 bellard
            gen_op_movl_T0_im(val);
2849 982b4315 bellard
            gen_op_mov_TN_reg[ot][1][R_EAX]();
2850 982b4315 bellard
            gen_op_out[ot]();
2851 982b4315 bellard
        }
2852 ba1c6e37 bellard
        break;
2853 ba1c6e37 bellard
    case 0xec:
2854 ba1c6e37 bellard
    case 0xed:
2855 982b4315 bellard
        if (s->cpl > s->iopl || s->vm86) {
2856 c50c0c3f bellard
            gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
2857 982b4315 bellard
        } else {
2858 982b4315 bellard
            if ((b & 1) == 0)
2859 982b4315 bellard
                ot = OT_BYTE;
2860 982b4315 bellard
            else
2861 982b4315 bellard
                ot = dflag ? OT_LONG : OT_WORD;
2862 982b4315 bellard
            gen_op_mov_TN_reg[OT_WORD][0][R_EDX]();
2863 982b4315 bellard
            gen_op_in[ot]();
2864 982b4315 bellard
            gen_op_mov_reg_T1[ot][R_EAX]();
2865 982b4315 bellard
        }
2866 ba1c6e37 bellard
        break;
2867 ba1c6e37 bellard
    case 0xee:
2868 ba1c6e37 bellard
    case 0xef:
2869 982b4315 bellard
        if (s->cpl > s->iopl || s->vm86) {
2870 c50c0c3f bellard
            gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
2871 982b4315 bellard
        } else {
2872 982b4315 bellard
            if ((b & 1) == 0)
2873 982b4315 bellard
                ot = OT_BYTE;
2874 982b4315 bellard
            else
2875 982b4315 bellard
                ot = dflag ? OT_LONG : OT_WORD;
2876 982b4315 bellard
            gen_op_mov_TN_reg[OT_WORD][0][R_EDX]();
2877 982b4315 bellard
            gen_op_mov_TN_reg[ot][1][R_EAX]();
2878 982b4315 bellard
            gen_op_out[ot]();
2879 982b4315 bellard
        }
2880 ba1c6e37 bellard
        break;
2881 367e86e8 bellard
2882 367e86e8 bellard
        /************************/
2883 367e86e8 bellard
        /* control */
2884 367e86e8 bellard
    case 0xc2: /* ret im */
2885 367e86e8 bellard
        val = ldsw(s->pc);
2886 367e86e8 bellard
        s->pc += 2;
2887 dab2ed99 bellard
        gen_pop_T0(s);
2888 dab2ed99 bellard
        if (s->ss32)
2889 dab2ed99 bellard
            gen_op_addl_ESP_im(val + (2 << s->dflag));
2890 dab2ed99 bellard
        else
2891 dab2ed99 bellard
            gen_op_addw_ESP_im(val + (2 << s->dflag));
2892 dab2ed99 bellard
        if (s->dflag == 0)
2893 dab2ed99 bellard
            gen_op_andl_T0_ffff();
2894 367e86e8 bellard
        gen_op_jmp_T0();
2895 6dbad63e bellard
        s->is_jmp = 1;
2896 367e86e8 bellard
        break;
2897 367e86e8 bellard
    case 0xc3: /* ret */
2898 dab2ed99 bellard
        gen_pop_T0(s);
2899 dab2ed99 bellard
        gen_pop_update(s);
2900 dab2ed99 bellard
        if (s->dflag == 0)
2901 dab2ed99 bellard
            gen_op_andl_T0_ffff();
2902 367e86e8 bellard
        gen_op_jmp_T0();
2903 6dbad63e bellard
        s->is_jmp = 1;
2904 367e86e8 bellard
        break;
2905 dab2ed99 bellard
    case 0xca: /* lret im */
2906 f631ef9b bellard
        /* XXX: not restartable */
2907 dab2ed99 bellard
        val = ldsw(s->pc);
2908 dab2ed99 bellard
        s->pc += 2;
2909 dab2ed99 bellard
        /* pop offset */
2910 dab2ed99 bellard
        gen_pop_T0(s);
2911 dab2ed99 bellard
        if (s->dflag == 0)
2912 dab2ed99 bellard
            gen_op_andl_T0_ffff();
2913 dab2ed99 bellard
        gen_op_jmp_T0();
2914 dab2ed99 bellard
        gen_pop_update(s);
2915 dab2ed99 bellard
        /* pop selector */
2916 dab2ed99 bellard
        gen_pop_T0(s);
2917 dab2ed99 bellard
        gen_movl_seg_T0(s, R_CS);
2918 dab2ed99 bellard
        gen_pop_update(s);
2919 dab2ed99 bellard
        /* add stack offset */
2920 dab2ed99 bellard
        if (s->ss32)
2921 148dfc2a bellard
            gen_op_addl_ESP_im(val);
2922 dab2ed99 bellard
        else
2923 148dfc2a bellard
            gen_op_addw_ESP_im(val);
2924 dab2ed99 bellard
        s->is_jmp = 1;
2925 dab2ed99 bellard
        break;
2926 dab2ed99 bellard
    case 0xcb: /* lret */
2927 f631ef9b bellard
        /* XXX: not restartable */
2928 dab2ed99 bellard
        /* pop offset */
2929 dab2ed99 bellard
        gen_pop_T0(s);
2930 dab2ed99 bellard
        if (s->dflag == 0)
2931 dab2ed99 bellard
            gen_op_andl_T0_ffff();
2932 dab2ed99 bellard
        gen_op_jmp_T0();
2933 dab2ed99 bellard
        gen_pop_update(s);
2934 dab2ed99 bellard
        /* pop selector */
2935 dab2ed99 bellard
        gen_pop_T0(s);
2936 dab2ed99 bellard
        gen_movl_seg_T0(s, R_CS);
2937 dab2ed99 bellard
        gen_pop_update(s);
2938 6dbad63e bellard
        s->is_jmp = 1;
2939 367e86e8 bellard
        break;
2940 f631ef9b bellard
    case 0xcf: /* iret */
2941 148dfc2a bellard
        if (s->vm86 && s->iopl != 3) {
2942 c50c0c3f bellard
            gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
2943 f631ef9b bellard
        } else {
2944 148dfc2a bellard
            /* XXX: not restartable */
2945 148dfc2a bellard
            /* pop offset */
2946 148dfc2a bellard
            gen_pop_T0(s);
2947 148dfc2a bellard
            if (s->dflag == 0)
2948 148dfc2a bellard
                gen_op_andl_T0_ffff();
2949 148dfc2a bellard
            gen_op_jmp_T0();
2950 148dfc2a bellard
            gen_pop_update(s);
2951 148dfc2a bellard
            /* pop selector */
2952 148dfc2a bellard
            gen_pop_T0(s);
2953 148dfc2a bellard
            gen_movl_seg_T0(s, R_CS);
2954 148dfc2a bellard
            gen_pop_update(s);
2955 148dfc2a bellard
            /* pop eflags */
2956 148dfc2a bellard
            gen_pop_T0(s);
2957 148dfc2a bellard
            if (s->dflag) {
2958 148dfc2a bellard
                gen_op_movl_eflags_T0();
2959 148dfc2a bellard
            } else {
2960 f631ef9b bellard
                gen_op_movw_eflags_T0();
2961 148dfc2a bellard
            }
2962 148dfc2a bellard
            gen_pop_update(s);
2963 148dfc2a bellard
            s->cc_op = CC_OP_EFLAGS;
2964 f631ef9b bellard
        }
2965 f631ef9b bellard
        s->is_jmp = 1;
2966 f631ef9b bellard
        break;
2967 dab2ed99 bellard
    case 0xe8: /* call im */
2968 dab2ed99 bellard
        {
2969 dab2ed99 bellard
            unsigned int next_eip;
2970 dab2ed99 bellard
            ot = dflag ? OT_LONG : OT_WORD;
2971 dab2ed99 bellard
            val = insn_get(s, ot);
2972 dab2ed99 bellard
            next_eip = s->pc - s->cs_base;
2973 dab2ed99 bellard
            val += next_eip;
2974 dab2ed99 bellard
            if (s->dflag == 0)
2975 dab2ed99 bellard
                val &= 0xffff;
2976 dab2ed99 bellard
            gen_op_movl_T0_im(next_eip);
2977 dab2ed99 bellard
            gen_push_T0(s);
2978 d4e8164f bellard
            gen_jmp(s, val);
2979 dab2ed99 bellard
        }
2980 dab2ed99 bellard
        break;
2981 dab2ed99 bellard
    case 0x9a: /* lcall im */
2982 dab2ed99 bellard
        {
2983 dab2ed99 bellard
            unsigned int selector, offset;
2984 dab2ed99 bellard
2985 dab2ed99 bellard
            ot = dflag ? OT_LONG : OT_WORD;
2986 dab2ed99 bellard
            offset = insn_get(s, ot);
2987 dab2ed99 bellard
            selector = insn_get(s, OT_WORD);
2988 dab2ed99 bellard
            
2989 dab2ed99 bellard
            /* push return segment + offset */
2990 dab2ed99 bellard
            gen_op_movl_T0_seg(R_CS);
2991 dab2ed99 bellard
            gen_push_T0(s);
2992 dab2ed99 bellard
            next_eip = s->pc - s->cs_base;
2993 dab2ed99 bellard
            gen_op_movl_T0_im(next_eip);
2994 dab2ed99 bellard
            gen_push_T0(s);
2995 dab2ed99 bellard
2996 dab2ed99 bellard
            /* change cs and pc */
2997 dab2ed99 bellard
            gen_op_movl_T0_im(selector);
2998 dab2ed99 bellard
            gen_movl_seg_T0(s, R_CS);
2999 dab2ed99 bellard
            gen_op_jmp_im((unsigned long)offset);
3000 dab2ed99 bellard
            s->is_jmp = 1;
3001 dab2ed99 bellard
        }
3002 dab2ed99 bellard
        break;
3003 367e86e8 bellard
    case 0xe9: /* jmp */
3004 dab2ed99 bellard
        ot = dflag ? OT_LONG : OT_WORD;
3005 dab2ed99 bellard
        val = insn_get(s, ot);
3006 dab2ed99 bellard
        val += s->pc - s->cs_base;
3007 dab2ed99 bellard
        if (s->dflag == 0)
3008 dab2ed99 bellard
            val = val & 0xffff;
3009 d4e8164f bellard
        gen_jmp(s, val);
3010 367e86e8 bellard
        break;
3011 dab2ed99 bellard
    case 0xea: /* ljmp im */
3012 dab2ed99 bellard
        {
3013 dab2ed99 bellard
            unsigned int selector, offset;
3014 dab2ed99 bellard
3015 dab2ed99 bellard
            ot = dflag ? OT_LONG : OT_WORD;
3016 dab2ed99 bellard
            offset = insn_get(s, ot);
3017 dab2ed99 bellard
            selector = insn_get(s, OT_WORD);
3018 dab2ed99 bellard
            
3019 dab2ed99 bellard
            /* change cs and pc */
3020 dab2ed99 bellard
            gen_op_movl_T0_im(selector);
3021 dab2ed99 bellard
            gen_movl_seg_T0(s, R_CS);
3022 dab2ed99 bellard
            gen_op_jmp_im((unsigned long)offset);
3023 dab2ed99 bellard
            s->is_jmp = 1;
3024 dab2ed99 bellard
        }
3025 dab2ed99 bellard
        break;
3026 367e86e8 bellard
    case 0xeb: /* jmp Jb */
3027 367e86e8 bellard
        val = (int8_t)insn_get(s, OT_BYTE);
3028 dab2ed99 bellard
        val += s->pc - s->cs_base;
3029 dab2ed99 bellard
        if (s->dflag == 0)
3030 dab2ed99 bellard
            val = val & 0xffff;
3031 d4e8164f bellard
        gen_jmp(s, val);
3032 367e86e8 bellard
        break;
3033 367e86e8 bellard
    case 0x70 ... 0x7f: /* jcc Jb */
3034 367e86e8 bellard
        val = (int8_t)insn_get(s, OT_BYTE);
3035 367e86e8 bellard
        goto do_jcc;
3036 367e86e8 bellard
    case 0x180 ... 0x18f: /* jcc Jv */
3037 367e86e8 bellard
        if (dflag) {
3038 367e86e8 bellard
            val = insn_get(s, OT_LONG);
3039 367e86e8 bellard
        } else {
3040 367e86e8 bellard
            val = (int16_t)insn_get(s, OT_WORD); 
3041 367e86e8 bellard
        }
3042 367e86e8 bellard
    do_jcc:
3043 dab2ed99 bellard
        next_eip = s->pc - s->cs_base;
3044 dab2ed99 bellard
        val += next_eip;
3045 dab2ed99 bellard
        if (s->dflag == 0)
3046 dab2ed99 bellard
            val &= 0xffff;
3047 dab2ed99 bellard
        gen_jcc(s, b, val, next_eip);
3048 367e86e8 bellard
        break;
3049 367e86e8 bellard
3050 5dd9488c bellard
    case 0x190 ... 0x19f: /* setcc Gv */
3051 367e86e8 bellard
        modrm = ldub(s->pc++);
3052 367e86e8 bellard
        gen_setcc(s, b);
3053 367e86e8 bellard
        gen_ldst_modrm(s, modrm, OT_BYTE, OR_TMP0, 1);
3054 367e86e8 bellard
        break;
3055 5dd9488c bellard
    case 0x140 ... 0x14f: /* cmov Gv, Ev */
3056 5dd9488c bellard
        ot = dflag ? OT_LONG : OT_WORD;
3057 5dd9488c bellard
        modrm = ldub(s->pc++);
3058 5dd9488c bellard
        reg = (modrm >> 3) & 7;
3059 5dd9488c bellard
        mod = (modrm >> 6) & 3;
3060 5dd9488c bellard
        gen_setcc(s, b);
3061 5dd9488c bellard
        if (mod != 3) {
3062 5dd9488c bellard
            gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3063 5dd9488c bellard
            gen_op_ld_T1_A0[ot]();
3064 5dd9488c bellard
        } else {
3065 5dd9488c bellard
            rm = modrm & 7;
3066 5dd9488c bellard
            gen_op_mov_TN_reg[ot][1][rm]();
3067 5dd9488c bellard
        }
3068 5dd9488c bellard
        gen_op_cmov_reg_T1_T0[ot - OT_WORD][reg]();
3069 5dd9488c bellard
        break;
3070 5dd9488c bellard
        
3071 367e86e8 bellard
        /************************/
3072 367e86e8 bellard
        /* flags */
3073 367e86e8 bellard
    case 0x9c: /* pushf */
3074 148dfc2a bellard
        if (s->vm86 && s->iopl != 3) {
3075 c50c0c3f bellard
            gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
3076 148dfc2a bellard
        } else {
3077 148dfc2a bellard
            if (s->cc_op != CC_OP_DYNAMIC)
3078 148dfc2a bellard
                gen_op_set_cc_op(s->cc_op);
3079 f631ef9b bellard
            gen_op_movl_T0_eflags();
3080 148dfc2a bellard
            gen_push_T0(s);
3081 148dfc2a bellard
        }
3082 367e86e8 bellard
        break;
3083 367e86e8 bellard
    case 0x9d: /* popf */
3084 148dfc2a bellard
        if (s->vm86 && s->iopl != 3) {
3085 c50c0c3f bellard
            gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
3086 f631ef9b bellard
        } else {
3087 148dfc2a bellard
            gen_pop_T0(s);
3088 148dfc2a bellard
            if (s->dflag) {
3089 148dfc2a bellard
                gen_op_movl_eflags_T0();
3090 148dfc2a bellard
            } else {
3091 f631ef9b bellard
                gen_op_movw_eflags_T0();
3092 148dfc2a bellard
            }
3093 148dfc2a bellard
            gen_pop_update(s);
3094 148dfc2a bellard
            s->cc_op = CC_OP_EFLAGS;
3095 c0ad5542 bellard
            s->is_jmp = 2; /* abort translation because TF flag may change */
3096 f631ef9b bellard
        }
3097 367e86e8 bellard
        break;
3098 367e86e8 bellard
    case 0x9e: /* sahf */
3099 367e86e8 bellard
        gen_op_mov_TN_reg[OT_BYTE][0][R_AH]();
3100 367e86e8 bellard
        if (s->cc_op != CC_OP_DYNAMIC)
3101 1017ebe9 bellard
            gen_op_set_cc_op(s->cc_op);
3102 367e86e8 bellard
        gen_op_movb_eflags_T0();
3103 367e86e8 bellard
        s->cc_op = CC_OP_EFLAGS;
3104 367e86e8 bellard
        break;
3105 367e86e8 bellard
    case 0x9f: /* lahf */
3106 367e86e8 bellard
        if (s->cc_op != CC_OP_DYNAMIC)
3107 1017ebe9 bellard
            gen_op_set_cc_op(s->cc_op);
3108 367e86e8 bellard
        gen_op_movl_T0_eflags();
3109 367e86e8 bellard
        gen_op_mov_reg_T0[OT_BYTE][R_AH]();
3110 367e86e8 bellard
        break;
3111 367e86e8 bellard
    case 0xf5: /* cmc */
3112 367e86e8 bellard
        if (s->cc_op != CC_OP_DYNAMIC)
3113 1017ebe9 bellard
            gen_op_set_cc_op(s->cc_op);
3114 367e86e8 bellard
        gen_op_cmc();
3115 367e86e8 bellard
        s->cc_op = CC_OP_EFLAGS;
3116 367e86e8 bellard
        break;
3117 367e86e8 bellard
    case 0xf8: /* clc */
3118 367e86e8 bellard
        if (s->cc_op != CC_OP_DYNAMIC)
3119 1017ebe9 bellard
            gen_op_set_cc_op(s->cc_op);
3120 367e86e8 bellard
        gen_op_clc();
3121 367e86e8 bellard
        s->cc_op = CC_OP_EFLAGS;
3122 367e86e8 bellard
        break;
3123 367e86e8 bellard
    case 0xf9: /* stc */
3124 367e86e8 bellard
        if (s->cc_op != CC_OP_DYNAMIC)
3125 1017ebe9 bellard
            gen_op_set_cc_op(s->cc_op);
3126 367e86e8 bellard
        gen_op_stc();
3127 367e86e8 bellard
        s->cc_op = CC_OP_EFLAGS;
3128 367e86e8 bellard
        break;
3129 367e86e8 bellard
    case 0xfc: /* cld */
3130 367e86e8 bellard
        gen_op_cld();
3131 367e86e8 bellard
        break;
3132 367e86e8 bellard
    case 0xfd: /* std */
3133 367e86e8 bellard
        gen_op_std();
3134 367e86e8 bellard
        break;
3135 367e86e8 bellard
3136 367e86e8 bellard
        /************************/
3137 4b74fe1f bellard
        /* bit operations */
3138 4b74fe1f bellard
    case 0x1ba: /* bt/bts/btr/btc Gv, im */
3139 4b74fe1f bellard
        ot = dflag ? OT_LONG : OT_WORD;
3140 4b74fe1f bellard
        modrm = ldub(s->pc++);
3141 4b74fe1f bellard
        op = (modrm >> 3) & 7;
3142 4b74fe1f bellard
        mod = (modrm >> 6) & 3;
3143 4b74fe1f bellard
        rm = modrm & 7;
3144 4b74fe1f bellard
        if (mod != 3) {
3145 4b74fe1f bellard
            gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3146 4b74fe1f bellard
            gen_op_ld_T0_A0[ot]();
3147 4b74fe1f bellard
        } else {
3148 4b74fe1f bellard
            gen_op_mov_TN_reg[ot][0][rm]();
3149 4b74fe1f bellard
        }
3150 4b74fe1f bellard
        /* load shift */
3151 4b74fe1f bellard
        val = ldub(s->pc++);
3152 4b74fe1f bellard
        gen_op_movl_T1_im(val);
3153 4b74fe1f bellard
        if (op < 4)
3154 1a9353d2 bellard
            goto illegal_op;
3155 4b74fe1f bellard
        op -= 4;
3156 4b74fe1f bellard
        gen_op_btx_T0_T1_cc[ot - OT_WORD][op]();
3157 d57c4e01 bellard
        s->cc_op = CC_OP_SARB + ot;
3158 4b74fe1f bellard
        if (op != 0) {
3159 4b74fe1f bellard
            if (mod != 3)
3160 4b74fe1f bellard
                gen_op_st_T0_A0[ot]();
3161 4b74fe1f bellard
            else
3162 4b74fe1f bellard
                gen_op_mov_reg_T0[ot][rm]();
3163 4b74fe1f bellard
        }
3164 4b74fe1f bellard
        break;
3165 4b74fe1f bellard
    case 0x1a3: /* bt Gv, Ev */
3166 4b74fe1f bellard
        op = 0;
3167 4b74fe1f bellard
        goto do_btx;
3168 4b74fe1f bellard
    case 0x1ab: /* bts */
3169 4b74fe1f bellard
        op = 1;
3170 4b74fe1f bellard
        goto do_btx;
3171 4b74fe1f bellard
    case 0x1b3: /* btr */
3172 4b74fe1f bellard
        op = 2;
3173 4b74fe1f bellard
        goto do_btx;
3174 4b74fe1f bellard
    case 0x1bb: /* btc */
3175 4b74fe1f bellard
        op = 3;
3176 4b74fe1f bellard
    do_btx:
3177 4b74fe1f bellard
        ot = dflag ? OT_LONG : OT_WORD;
3178 4b74fe1f bellard
        modrm = ldub(s->pc++);
3179 4b74fe1f bellard
        reg = (modrm >> 3) & 7;
3180 4b74fe1f bellard
        mod = (modrm >> 6) & 3;
3181 4b74fe1f bellard
        rm = modrm & 7;
3182 4b74fe1f bellard
        gen_op_mov_TN_reg[OT_LONG][1][reg]();
3183 4b74fe1f bellard
        if (mod != 3) {
3184 4b74fe1f bellard
            gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3185 4b74fe1f bellard
            /* specific case: we need to add a displacement */
3186 4b74fe1f bellard
            if (ot == OT_WORD)
3187 4b74fe1f bellard
                gen_op_add_bitw_A0_T1();
3188 4b74fe1f bellard
            else
3189 4b74fe1f bellard
                gen_op_add_bitl_A0_T1();
3190 4b74fe1f bellard
            gen_op_ld_T0_A0[ot]();
3191 4b74fe1f bellard
        } else {
3192 4b74fe1f bellard
            gen_op_mov_TN_reg[ot][0][rm]();
3193 4b74fe1f bellard
        }
3194 4b74fe1f bellard
        gen_op_btx_T0_T1_cc[ot - OT_WORD][op]();
3195 d57c4e01 bellard
        s->cc_op = CC_OP_SARB + ot;
3196 4b74fe1f bellard
        if (op != 0) {
3197 4b74fe1f bellard
            if (mod != 3)
3198 4b74fe1f bellard
                gen_op_st_T0_A0[ot]();
3199 4b74fe1f bellard
            else
3200 4b74fe1f bellard
                gen_op_mov_reg_T0[ot][rm]();
3201 4b74fe1f bellard
        }
3202 4b74fe1f bellard
        break;
3203 77f8dd5a bellard
    case 0x1bc: /* bsf */
3204 77f8dd5a bellard
    case 0x1bd: /* bsr */
3205 77f8dd5a bellard
        ot = dflag ? OT_LONG : OT_WORD;
3206 77f8dd5a bellard
        modrm = ldub(s->pc++);
3207 77f8dd5a bellard
        reg = (modrm >> 3) & 7;
3208 77f8dd5a bellard
        gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0);
3209 77f8dd5a bellard
        gen_op_bsx_T0_cc[ot - OT_WORD][b & 1]();
3210 77f8dd5a bellard
        /* NOTE: we always write back the result. Intel doc says it is
3211 77f8dd5a bellard
           undefined if T0 == 0 */
3212 77f8dd5a bellard
        gen_op_mov_reg_T0[ot][reg]();
3213 77f8dd5a bellard
        s->cc_op = CC_OP_LOGICB + ot;
3214 77f8dd5a bellard
        break;
3215 4b74fe1f bellard
        /************************/
3216 27362c82 bellard
        /* bcd */
3217 27362c82 bellard
    case 0x27: /* daa */
3218 27362c82 bellard
        if (s->cc_op != CC_OP_DYNAMIC)
3219 27362c82 bellard
            gen_op_set_cc_op(s->cc_op);
3220 27362c82 bellard
        gen_op_daa();
3221 27362c82 bellard
        s->cc_op = CC_OP_EFLAGS;
3222 27362c82 bellard
        break;
3223 27362c82 bellard
    case 0x2f: /* das */
3224 27362c82 bellard
        if (s->cc_op != CC_OP_DYNAMIC)
3225 27362c82 bellard
            gen_op_set_cc_op(s->cc_op);
3226 27362c82 bellard
        gen_op_das();
3227 27362c82 bellard
        s->cc_op = CC_OP_EFLAGS;
3228 27362c82 bellard
        break;
3229 27362c82 bellard
    case 0x37: /* aaa */
3230 27362c82 bellard
        if (s->cc_op != CC_OP_DYNAMIC)
3231 27362c82 bellard
            gen_op_set_cc_op(s->cc_op);
3232 27362c82 bellard
        gen_op_aaa();
3233 27362c82 bellard
        s->cc_op = CC_OP_EFLAGS;
3234 27362c82 bellard
        break;
3235 27362c82 bellard
    case 0x3f: /* aas */
3236 27362c82 bellard
        if (s->cc_op != CC_OP_DYNAMIC)
3237 27362c82 bellard
            gen_op_set_cc_op(s->cc_op);
3238 27362c82 bellard
        gen_op_aas();
3239 27362c82 bellard
        s->cc_op = CC_OP_EFLAGS;
3240 27362c82 bellard
        break;
3241 27362c82 bellard
    case 0xd4: /* aam */
3242 27362c82 bellard
        val = ldub(s->pc++);
3243 27362c82 bellard
        gen_op_aam(val);
3244 27362c82 bellard
        s->cc_op = CC_OP_LOGICB;
3245 27362c82 bellard
        break;
3246 27362c82 bellard
    case 0xd5: /* aad */
3247 27362c82 bellard
        val = ldub(s->pc++);
3248 27362c82 bellard
        gen_op_aad(val);
3249 27362c82 bellard
        s->cc_op = CC_OP_LOGICB;
3250 27362c82 bellard
        break;
3251 27362c82 bellard
        /************************/
3252 367e86e8 bellard
        /* misc */
3253 367e86e8 bellard
    case 0x90: /* nop */
3254 367e86e8 bellard
        break;
3255 a37904dd bellard
    case 0x9b: /* fwait */
3256 a37904dd bellard
        break;
3257 0ecfa993 bellard
    case 0xcc: /* int3 */
3258 78c34e98 bellard
        gen_exception(s, EXCP03_INT3, s->pc - s->cs_base);
3259 0ecfa993 bellard
        break;
3260 0ecfa993 bellard
    case 0xcd: /* int N */
3261 0ecfa993 bellard
        val = ldub(s->pc++);
3262 c50c0c3f bellard
        if (s->cc_op != CC_OP_DYNAMIC)
3263 c50c0c3f bellard
            gen_op_set_cc_op(s->cc_op);
3264 982b4315 bellard
        gen_op_int_im(val, pc_start - s->cs_base);
3265 6dbad63e bellard
        s->is_jmp = 1;
3266 0ecfa993 bellard
        break;
3267 0ecfa993 bellard
    case 0xce: /* into */
3268 0ecfa993 bellard
        if (s->cc_op != CC_OP_DYNAMIC)
3269 0ecfa993 bellard
            gen_op_set_cc_op(s->cc_op);
3270 78c34e98 bellard
        gen_op_into(s->pc - s->cs_base);
3271 9c605cb1 bellard
        break;
3272 f631ef9b bellard
    case 0xfa: /* cli */
3273 982b4315 bellard
        if (!s->vm86) {
3274 148dfc2a bellard
            if (s->cpl <= s->iopl) {
3275 982b4315 bellard
                gen_op_cli();
3276 148dfc2a bellard
            } else {
3277 c50c0c3f bellard
                gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
3278 148dfc2a bellard
            }
3279 982b4315 bellard
        } else {
3280 148dfc2a bellard
            if (s->iopl == 3) {
3281 982b4315 bellard
                gen_op_cli();
3282 148dfc2a bellard
            } else {
3283 c50c0c3f bellard
                gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
3284 148dfc2a bellard
            }
3285 982b4315 bellard
        }
3286 f631ef9b bellard
        break;
3287 f631ef9b bellard
    case 0xfb: /* sti */
3288 982b4315 bellard
        if (!s->vm86) {
3289 148dfc2a bellard
            if (s->cpl <= s->iopl) {
3290 982b4315 bellard
                gen_op_sti();
3291 148dfc2a bellard
            } else {
3292 c50c0c3f bellard
                gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
3293 148dfc2a bellard
            }
3294 982b4315 bellard
        } else {
3295 148dfc2a bellard
            if (s->iopl == 3) {
3296 982b4315 bellard
                gen_op_sti();
3297 148dfc2a bellard
            } else {
3298 c50c0c3f bellard
                gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
3299 148dfc2a bellard
            }
3300 982b4315 bellard
        }
3301 f631ef9b bellard
        break;
3302 9c605cb1 bellard
    case 0x62: /* bound */
3303 9c605cb1 bellard
        ot = dflag ? OT_LONG : OT_WORD;
3304 9c605cb1 bellard
        modrm = ldub(s->pc++);
3305 9c605cb1 bellard
        reg = (modrm >> 3) & 7;
3306 9c605cb1 bellard
        mod = (modrm >> 6) & 3;
3307 9c605cb1 bellard
        if (mod == 3)
3308 9c605cb1 bellard
            goto illegal_op;
3309 9c605cb1 bellard
        gen_op_mov_reg_T0[ot][reg]();
3310 9c605cb1 bellard
        gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3311 9c605cb1 bellard
        if (ot == OT_WORD)
3312 9c605cb1 bellard
            gen_op_boundw();
3313 9c605cb1 bellard
        else
3314 9c605cb1 bellard
            gen_op_boundl();
3315 0ecfa993 bellard
        break;
3316 4b74fe1f bellard
    case 0x1c8 ... 0x1cf: /* bswap reg */
3317 27362c82 bellard
        reg = b & 7;
3318 27362c82 bellard
        gen_op_mov_TN_reg[OT_LONG][0][reg]();
3319 27362c82 bellard
        gen_op_bswapl_T0();
3320 27362c82 bellard
        gen_op_mov_reg_T0[OT_LONG][reg]();
3321 27362c82 bellard
        break;
3322 27362c82 bellard
    case 0xd6: /* salc */
3323 27362c82 bellard
        if (s->cc_op != CC_OP_DYNAMIC)
3324 27362c82 bellard
            gen_op_set_cc_op(s->cc_op);
3325 27362c82 bellard
        gen_op_salc();
3326 27362c82 bellard
        break;
3327 1a9353d2 bellard
    case 0xe0: /* loopnz */
3328 1a9353d2 bellard
    case 0xe1: /* loopz */
3329 1a9353d2 bellard
        if (s->cc_op != CC_OP_DYNAMIC)
3330 1a9353d2 bellard
            gen_op_set_cc_op(s->cc_op);
3331 1a9353d2 bellard
        /* FALL THRU */
3332 1a9353d2 bellard
    case 0xe2: /* loop */
3333 1a9353d2 bellard
    case 0xe3: /* jecxz */
3334 1a9353d2 bellard
        val = (int8_t)insn_get(s, OT_BYTE);
3335 dab2ed99 bellard
        next_eip = s->pc - s->cs_base;
3336 dab2ed99 bellard
        val += next_eip;
3337 dab2ed99 bellard
        if (s->dflag == 0)
3338 dab2ed99 bellard
            val &= 0xffff;
3339 dab2ed99 bellard
        gen_op_loop[s->aflag][b & 3](val, next_eip);
3340 1a9353d2 bellard
        s->is_jmp = 1;
3341 1a9353d2 bellard
        break;
3342 5dd9488c bellard
    case 0x131: /* rdtsc */
3343 27362c82 bellard
        gen_op_rdtsc();
3344 27362c82 bellard
        break;
3345 367e86e8 bellard
    case 0x1a2: /* cpuid */
3346 9c605cb1 bellard
        gen_op_cpuid();
3347 367e86e8 bellard
        break;
3348 982b4315 bellard
    case 0xf4: /* hlt */
3349 148dfc2a bellard
        /* XXX: if cpl == 0, then should do something else */
3350 c50c0c3f bellard
        gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
3351 982b4315 bellard
        break;
3352 78c34e98 bellard
    case 0x102: /* lar */
3353 78c34e98 bellard
    case 0x103: /* lsl */
3354 78c34e98 bellard
        if (s->vm86)
3355 78c34e98 bellard
            goto illegal_op;
3356 78c34e98 bellard
        ot = dflag ? OT_LONG : OT_WORD;
3357 78c34e98 bellard
        modrm = ldub(s->pc++);
3358 78c34e98 bellard
        reg = (modrm >> 3) & 7;
3359 78c34e98 bellard
        gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0);
3360 78c34e98 bellard
        gen_op_mov_TN_reg[ot][1][reg]();
3361 78c34e98 bellard
        if (s->cc_op != CC_OP_DYNAMIC)
3362 78c34e98 bellard
            gen_op_set_cc_op(s->cc_op);
3363 78c34e98 bellard
        if (b == 0x102)
3364 78c34e98 bellard
            gen_op_lar();
3365 78c34e98 bellard
        else
3366 78c34e98 bellard
            gen_op_lsl();
3367 78c34e98 bellard
        s->cc_op = CC_OP_EFLAGS;
3368 78c34e98 bellard
        gen_op_mov_reg_T1[ot][reg]();
3369 78c34e98 bellard
        break;
3370 367e86e8 bellard
    default:
3371 1a9353d2 bellard
        goto illegal_op;
3372 367e86e8 bellard
    }
3373 1b6b029e bellard
    /* lock generation */
3374 1b6b029e bellard
    if (s->prefix & PREFIX_LOCK)
3375 1b6b029e bellard
        gen_op_unlock();
3376 367e86e8 bellard
    return (long)s->pc;
3377 6dbad63e bellard
 illegal_op:
3378 1b6b029e bellard
    /* XXX: ensure that no lock was generated */
3379 6dbad63e bellard
    return -1;
3380 367e86e8 bellard
}
3381 367e86e8 bellard
3382 dc99065b bellard
#define CC_OSZAPC (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C)
3383 dc99065b bellard
#define CC_OSZAP (CC_O | CC_S | CC_Z | CC_A | CC_P)
3384 dc99065b bellard
3385 dc99065b bellard
/* flags read by an operation */
3386 dc99065b bellard
static uint16_t opc_read_flags[NB_OPS] = { 
3387 dc99065b bellard
    [INDEX_op_aas] = CC_A,
3388 dc99065b bellard
    [INDEX_op_aaa] = CC_A,
3389 dc99065b bellard
    [INDEX_op_das] = CC_A | CC_C,
3390 dc99065b bellard
    [INDEX_op_daa] = CC_A | CC_C,
3391 dc99065b bellard
3392 dc99065b bellard
    [INDEX_op_adcb_T0_T1_cc] = CC_C,
3393 dc99065b bellard
    [INDEX_op_adcw_T0_T1_cc] = CC_C,
3394 dc99065b bellard
    [INDEX_op_adcl_T0_T1_cc] = CC_C,
3395 dc99065b bellard
    [INDEX_op_sbbb_T0_T1_cc] = CC_C,
3396 dc99065b bellard
    [INDEX_op_sbbw_T0_T1_cc] = CC_C,
3397 dc99065b bellard
    [INDEX_op_sbbl_T0_T1_cc] = CC_C,
3398 dc99065b bellard
3399 982b4315 bellard
    /* subtle: due to the incl/decl implementation, C is used */
3400 982b4315 bellard
    [INDEX_op_incl_T0_cc] = CC_C, 
3401 982b4315 bellard
    [INDEX_op_decl_T0_cc] = CC_C,
3402 982b4315 bellard
3403 dc99065b bellard
    [INDEX_op_into] = CC_O,
3404 dc99065b bellard
3405 dc99065b bellard
    [INDEX_op_jb_subb] = CC_C,
3406 dc99065b bellard
    [INDEX_op_jb_subw] = CC_C,
3407 dc99065b bellard
    [INDEX_op_jb_subl] = CC_C,
3408 dc99065b bellard
3409 dc99065b bellard
    [INDEX_op_jz_subb] = CC_Z,
3410 dc99065b bellard
    [INDEX_op_jz_subw] = CC_Z,
3411 dc99065b bellard
    [INDEX_op_jz_subl] = CC_Z,
3412 dc99065b bellard
3413 dc99065b bellard
    [INDEX_op_jbe_subb] = CC_Z | CC_C,
3414 dc99065b bellard
    [INDEX_op_jbe_subw] = CC_Z | CC_C,
3415 dc99065b bellard
    [INDEX_op_jbe_subl] = CC_Z | CC_C,
3416 dc99065b bellard
3417 dc99065b bellard
    [INDEX_op_js_subb] = CC_S,
3418 dc99065b bellard
    [INDEX_op_js_subw] = CC_S,
3419 dc99065b bellard
    [INDEX_op_js_subl] = CC_S,
3420 dc99065b bellard
3421 dc99065b bellard
    [INDEX_op_jl_subb] = CC_O | CC_S,
3422 dc99065b bellard
    [INDEX_op_jl_subw] = CC_O | CC_S,
3423 dc99065b bellard
    [INDEX_op_jl_subl] = CC_O | CC_S,
3424 dc99065b bellard
3425 dc99065b bellard
    [INDEX_op_jle_subb] = CC_O | CC_S | CC_Z,
3426 dc99065b bellard
    [INDEX_op_jle_subw] = CC_O | CC_S | CC_Z,
3427 dc99065b bellard
    [INDEX_op_jle_subl] = CC_O | CC_S | CC_Z,
3428 dc99065b bellard
3429 dc99065b bellard
    [INDEX_op_loopnzw] = CC_Z,
3430 dc99065b bellard
    [INDEX_op_loopnzl] = CC_Z,
3431 dc99065b bellard
    [INDEX_op_loopzw] = CC_Z,
3432 dc99065b bellard
    [INDEX_op_loopzl] = CC_Z,
3433 dc99065b bellard
3434 dc99065b bellard
    [INDEX_op_seto_T0_cc] = CC_O,
3435 dc99065b bellard
    [INDEX_op_setb_T0_cc] = CC_C,
3436 dc99065b bellard
    [INDEX_op_setz_T0_cc] = CC_Z,
3437 dc99065b bellard
    [INDEX_op_setbe_T0_cc] = CC_Z | CC_C,
3438 dc99065b bellard
    [INDEX_op_sets_T0_cc] = CC_S,
3439 dc99065b bellard
    [INDEX_op_setp_T0_cc] = CC_P,
3440 dc99065b bellard
    [INDEX_op_setl_T0_cc] = CC_O | CC_S,
3441 dc99065b bellard
    [INDEX_op_setle_T0_cc] = CC_O | CC_S | CC_Z,
3442 dc99065b bellard
3443 dc99065b bellard
    [INDEX_op_setb_T0_subb] = CC_C,
3444 dc99065b bellard
    [INDEX_op_setb_T0_subw] = CC_C,
3445 dc99065b bellard
    [INDEX_op_setb_T0_subl] = CC_C,
3446 dc99065b bellard
3447 dc99065b bellard
    [INDEX_op_setz_T0_subb] = CC_Z,
3448 dc99065b bellard
    [INDEX_op_setz_T0_subw] = CC_Z,
3449 dc99065b bellard
    [INDEX_op_setz_T0_subl] = CC_Z,
3450 dc99065b bellard
3451 dc99065b bellard
    [INDEX_op_setbe_T0_subb] = CC_Z | CC_C,
3452 dc99065b bellard
    [INDEX_op_setbe_T0_subw] = CC_Z | CC_C,
3453 dc99065b bellard
    [INDEX_op_setbe_T0_subl] = CC_Z | CC_C,
3454 dc99065b bellard
3455 dc99065b bellard
    [INDEX_op_sets_T0_subb] = CC_S,
3456 dc99065b bellard
    [INDEX_op_sets_T0_subw] = CC_S,
3457 dc99065b bellard
    [INDEX_op_sets_T0_subl] = CC_S,
3458 dc99065b bellard
3459 dc99065b bellard
    [INDEX_op_setl_T0_subb] = CC_O | CC_S,
3460 dc99065b bellard
    [INDEX_op_setl_T0_subw] = CC_O | CC_S,
3461 dc99065b bellard
    [INDEX_op_setl_T0_subl] = CC_O | CC_S,
3462 dc99065b bellard
3463 dc99065b bellard
    [INDEX_op_setle_T0_subb] = CC_O | CC_S | CC_Z,
3464 dc99065b bellard
    [INDEX_op_setle_T0_subw] = CC_O | CC_S | CC_Z,
3465 dc99065b bellard
    [INDEX_op_setle_T0_subl] = CC_O | CC_S | CC_Z,
3466 dc99065b bellard
3467 dc99065b bellard
    [INDEX_op_movl_T0_eflags] = CC_OSZAPC,
3468 dc99065b bellard
    [INDEX_op_cmc] = CC_C,
3469 dc99065b bellard
    [INDEX_op_salc] = CC_C,
3470 dc99065b bellard
3471 dc99065b bellard
    [INDEX_op_rclb_T0_T1_cc] = CC_C,
3472 dc99065b bellard
    [INDEX_op_rclw_T0_T1_cc] = CC_C,
3473 dc99065b bellard
    [INDEX_op_rcll_T0_T1_cc] = CC_C,
3474 dc99065b bellard
    [INDEX_op_rcrb_T0_T1_cc] = CC_C,
3475 dc99065b bellard
    [INDEX_op_rcrw_T0_T1_cc] = CC_C,
3476 dc99065b bellard
    [INDEX_op_rcrl_T0_T1_cc] = CC_C,
3477 dc99065b bellard
};
3478 dc99065b bellard
3479 dc99065b bellard
/* flags written by an operation */
3480 dc99065b bellard
static uint16_t opc_write_flags[NB_OPS] = { 
3481 dc99065b bellard
    [INDEX_op_addl_T0_T1_cc] = CC_OSZAPC,
3482 dc99065b bellard
    [INDEX_op_orl_T0_T1_cc] = CC_OSZAPC,
3483 dc99065b bellard
    [INDEX_op_adcb_T0_T1_cc] = CC_OSZAPC,
3484 dc99065b bellard
    [INDEX_op_adcw_T0_T1_cc] = CC_OSZAPC,
3485 dc99065b bellard
    [INDEX_op_adcl_T0_T1_cc] = CC_OSZAPC,
3486 dc99065b bellard
    [INDEX_op_sbbb_T0_T1_cc] = CC_OSZAPC,
3487 dc99065b bellard
    [INDEX_op_sbbw_T0_T1_cc] = CC_OSZAPC,
3488 dc99065b bellard
    [INDEX_op_sbbl_T0_T1_cc] = CC_OSZAPC,
3489 dc99065b bellard
    [INDEX_op_andl_T0_T1_cc] = CC_OSZAPC,
3490 dc99065b bellard
    [INDEX_op_subl_T0_T1_cc] = CC_OSZAPC,
3491 dc99065b bellard
    [INDEX_op_xorl_T0_T1_cc] = CC_OSZAPC,
3492 dc99065b bellard
    [INDEX_op_cmpl_T0_T1_cc] = CC_OSZAPC,
3493 dc99065b bellard
    [INDEX_op_negl_T0_cc] = CC_OSZAPC,
3494 982b4315 bellard
    /* subtle: due to the incl/decl implementation, C is used */
3495 982b4315 bellard
    [INDEX_op_incl_T0_cc] = CC_OSZAPC, 
3496 982b4315 bellard
    [INDEX_op_decl_T0_cc] = CC_OSZAPC,
3497 dc99065b bellard
    [INDEX_op_testl_T0_T1_cc] = CC_OSZAPC,
3498 dc99065b bellard
3499 dc99065b bellard
    [INDEX_op_mulb_AL_T0] = CC_OSZAPC,
3500 dc99065b bellard
    [INDEX_op_imulb_AL_T0] = CC_OSZAPC,
3501 dc99065b bellard
    [INDEX_op_mulw_AX_T0] = CC_OSZAPC,
3502 dc99065b bellard
    [INDEX_op_imulw_AX_T0] = CC_OSZAPC,
3503 dc99065b bellard
    [INDEX_op_mull_EAX_T0] = CC_OSZAPC,
3504 dc99065b bellard
    [INDEX_op_imull_EAX_T0] = CC_OSZAPC,
3505 dc99065b bellard
    [INDEX_op_imulw_T0_T1] = CC_OSZAPC,
3506 dc99065b bellard
    [INDEX_op_imull_T0_T1] = CC_OSZAPC,
3507 dc99065b bellard
    
3508 dc99065b bellard
    /* bcd */
3509 dc99065b bellard
    [INDEX_op_aam] = CC_OSZAPC,
3510 dc99065b bellard
    [INDEX_op_aad] = CC_OSZAPC,
3511 dc99065b bellard
    [INDEX_op_aas] = CC_OSZAPC,
3512 dc99065b bellard
    [INDEX_op_aaa] = CC_OSZAPC,
3513 dc99065b bellard
    [INDEX_op_das] = CC_OSZAPC,
3514 dc99065b bellard
    [INDEX_op_daa] = CC_OSZAPC,
3515 dc99065b bellard
3516 dc99065b bellard
    [INDEX_op_movb_eflags_T0] = CC_S | CC_Z | CC_A | CC_P | CC_C,
3517 f631ef9b bellard
    [INDEX_op_movw_eflags_T0] = CC_OSZAPC,
3518 dc99065b bellard
    [INDEX_op_movl_eflags_T0] = CC_OSZAPC,
3519 dc99065b bellard
    [INDEX_op_clc] = CC_C,
3520 dc99065b bellard
    [INDEX_op_stc] = CC_C,
3521 dc99065b bellard
    [INDEX_op_cmc] = CC_C,
3522 dc99065b bellard
3523 dc99065b bellard
    [INDEX_op_rolb_T0_T1_cc] = CC_O | CC_C,
3524 dc99065b bellard
    [INDEX_op_rolw_T0_T1_cc] = CC_O | CC_C,
3525 dc99065b bellard
    [INDEX_op_roll_T0_T1_cc] = CC_O | CC_C,
3526 dc99065b bellard
    [INDEX_op_rorb_T0_T1_cc] = CC_O | CC_C,
3527 dc99065b bellard
    [INDEX_op_rorw_T0_T1_cc] = CC_O | CC_C,
3528 dc99065b bellard
    [INDEX_op_rorl_T0_T1_cc] = CC_O | CC_C,
3529 dc99065b bellard
3530 dc99065b bellard
    [INDEX_op_rclb_T0_T1_cc] = CC_O | CC_C,
3531 dc99065b bellard
    [INDEX_op_rclw_T0_T1_cc] = CC_O | CC_C,
3532 dc99065b bellard
    [INDEX_op_rcll_T0_T1_cc] = CC_O | CC_C,
3533 dc99065b bellard
    [INDEX_op_rcrb_T0_T1_cc] = CC_O | CC_C,
3534 dc99065b bellard
    [INDEX_op_rcrw_T0_T1_cc] = CC_O | CC_C,
3535 dc99065b bellard
    [INDEX_op_rcrl_T0_T1_cc] = CC_O | CC_C,
3536 dc99065b bellard
3537 dc99065b bellard
    [INDEX_op_shlb_T0_T1_cc] = CC_OSZAPC,
3538 dc99065b bellard
    [INDEX_op_shlw_T0_T1_cc] = CC_OSZAPC,
3539 dc99065b bellard
    [INDEX_op_shll_T0_T1_cc] = CC_OSZAPC,
3540 dc99065b bellard
3541 dc99065b bellard
    [INDEX_op_shrb_T0_T1_cc] = CC_OSZAPC,
3542 dc99065b bellard
    [INDEX_op_shrw_T0_T1_cc] = CC_OSZAPC,
3543 dc99065b bellard
    [INDEX_op_shrl_T0_T1_cc] = CC_OSZAPC,
3544 dc99065b bellard
3545 dc99065b bellard
    [INDEX_op_sarb_T0_T1_cc] = CC_OSZAPC,
3546 dc99065b bellard
    [INDEX_op_sarw_T0_T1_cc] = CC_OSZAPC,
3547 dc99065b bellard
    [INDEX_op_sarl_T0_T1_cc] = CC_OSZAPC,
3548 dc99065b bellard
3549 dc99065b bellard
    [INDEX_op_shldw_T0_T1_ECX_cc] = CC_OSZAPC,
3550 dc99065b bellard
    [INDEX_op_shldl_T0_T1_ECX_cc] = CC_OSZAPC,
3551 dc99065b bellard
    [INDEX_op_shldw_T0_T1_im_cc] = CC_OSZAPC,
3552 dc99065b bellard
    [INDEX_op_shldl_T0_T1_im_cc] = CC_OSZAPC,
3553 dc99065b bellard
3554 dc99065b bellard
    [INDEX_op_shrdw_T0_T1_ECX_cc] = CC_OSZAPC,
3555 dc99065b bellard
    [INDEX_op_shrdl_T0_T1_ECX_cc] = CC_OSZAPC,
3556 dc99065b bellard
    [INDEX_op_shrdw_T0_T1_im_cc] = CC_OSZAPC,
3557 dc99065b bellard
    [INDEX_op_shrdl_T0_T1_im_cc] = CC_OSZAPC,
3558 dc99065b bellard
3559 dc99065b bellard
    [INDEX_op_btw_T0_T1_cc] = CC_OSZAPC,
3560 dc99065b bellard
    [INDEX_op_btl_T0_T1_cc] = CC_OSZAPC,
3561 dc99065b bellard
    [INDEX_op_btsw_T0_T1_cc] = CC_OSZAPC,
3562 dc99065b bellard
    [INDEX_op_btsl_T0_T1_cc] = CC_OSZAPC,
3563 dc99065b bellard
    [INDEX_op_btrw_T0_T1_cc] = CC_OSZAPC,
3564 dc99065b bellard
    [INDEX_op_btrl_T0_T1_cc] = CC_OSZAPC,
3565 dc99065b bellard
    [INDEX_op_btcw_T0_T1_cc] = CC_OSZAPC,
3566 dc99065b bellard
    [INDEX_op_btcl_T0_T1_cc] = CC_OSZAPC,
3567 dc99065b bellard
3568 dc99065b bellard
    [INDEX_op_bsfw_T0_cc] = CC_OSZAPC,
3569 dc99065b bellard
    [INDEX_op_bsfl_T0_cc] = CC_OSZAPC,
3570 dc99065b bellard
    [INDEX_op_bsrw_T0_cc] = CC_OSZAPC,
3571 dc99065b bellard
    [INDEX_op_bsrl_T0_cc] = CC_OSZAPC,
3572 dc99065b bellard
3573 9c605cb1 bellard
#undef STRINGOP
3574 9c605cb1 bellard
#define STRINGOP(x) \
3575 9c605cb1 bellard
    [INDEX_op_ ## x ## b_fast] = CC_OSZAPC, \
3576 9c605cb1 bellard
    [INDEX_op_ ## x ## w_fast] = CC_OSZAPC, \
3577 9c605cb1 bellard
    [INDEX_op_ ## x ## l_fast] = CC_OSZAPC, \
3578 9c605cb1 bellard
    [INDEX_op_ ## x ## b_a32] = CC_OSZAPC, \
3579 9c605cb1 bellard
    [INDEX_op_ ## x ## w_a32] = CC_OSZAPC, \
3580 9c605cb1 bellard
    [INDEX_op_ ## x ## l_a32] = CC_OSZAPC, \
3581 9c605cb1 bellard
    [INDEX_op_ ## x ## b_a16] = CC_OSZAPC, \
3582 9c605cb1 bellard
    [INDEX_op_ ## x ## w_a16] = CC_OSZAPC, \
3583 9c605cb1 bellard
    [INDEX_op_ ## x ## l_a16] = CC_OSZAPC,
3584 9c605cb1 bellard
3585 9c605cb1 bellard
    STRINGOP(scas)
3586 9c605cb1 bellard
    STRINGOP(repz_scas)
3587 9c605cb1 bellard
    STRINGOP(repnz_scas)
3588 9c605cb1 bellard
    STRINGOP(cmps)
3589 9c605cb1 bellard
    STRINGOP(repz_cmps)
3590 9c605cb1 bellard
    STRINGOP(repnz_cmps)
3591 9c605cb1 bellard
3592 9c605cb1 bellard
    [INDEX_op_cmpxchgb_T0_T1_EAX_cc] = CC_OSZAPC,
3593 dc99065b bellard
    [INDEX_op_cmpxchgw_T0_T1_EAX_cc] = CC_OSZAPC,
3594 dc99065b bellard
    [INDEX_op_cmpxchgl_T0_T1_EAX_cc] = CC_OSZAPC,
3595 9c605cb1 bellard
3596 9c605cb1 bellard
    [INDEX_op_cmpxchg8b] = CC_Z,
3597 78c34e98 bellard
    [INDEX_op_lar] = CC_Z,
3598 78c34e98 bellard
    [INDEX_op_lsl] = CC_Z,
3599 dc99065b bellard
};
3600 dc99065b bellard
3601 dc99065b bellard
/* simpler form of an operation if no flags need to be generated */
3602 dc99065b bellard
static uint16_t opc_simpler[NB_OPS] = { 
3603 dc99065b bellard
    [INDEX_op_addl_T0_T1_cc] = INDEX_op_addl_T0_T1,
3604 dc99065b bellard
    [INDEX_op_orl_T0_T1_cc] = INDEX_op_orl_T0_T1,
3605 dc99065b bellard
    [INDEX_op_andl_T0_T1_cc] = INDEX_op_andl_T0_T1,
3606 dc99065b bellard
    [INDEX_op_subl_T0_T1_cc] = INDEX_op_subl_T0_T1,
3607 dc99065b bellard
    [INDEX_op_xorl_T0_T1_cc] = INDEX_op_xorl_T0_T1,
3608 dc99065b bellard
    [INDEX_op_negl_T0_cc] = INDEX_op_negl_T0,
3609 dc99065b bellard
    [INDEX_op_incl_T0_cc] = INDEX_op_incl_T0,
3610 dc99065b bellard
    [INDEX_op_decl_T0_cc] = INDEX_op_decl_T0,
3611 dc99065b bellard
3612 dc99065b bellard
    [INDEX_op_rolb_T0_T1_cc] = INDEX_op_rolb_T0_T1,
3613 dc99065b bellard
    [INDEX_op_rolw_T0_T1_cc] = INDEX_op_rolw_T0_T1,
3614 dc99065b bellard
    [INDEX_op_roll_T0_T1_cc] = INDEX_op_roll_T0_T1,
3615 dc99065b bellard
3616 dc99065b bellard
    [INDEX_op_rorb_T0_T1_cc] = INDEX_op_rorb_T0_T1,
3617 dc99065b bellard
    [INDEX_op_rorw_T0_T1_cc] = INDEX_op_rorw_T0_T1,
3618 dc99065b bellard
    [INDEX_op_rorl_T0_T1_cc] = INDEX_op_rorl_T0_T1,
3619 dc99065b bellard
3620 dc99065b bellard
    [INDEX_op_shlb_T0_T1_cc] = INDEX_op_shlb_T0_T1,
3621 dc99065b bellard
    [INDEX_op_shlw_T0_T1_cc] = INDEX_op_shlw_T0_T1,
3622 dc99065b bellard
    [INDEX_op_shll_T0_T1_cc] = INDEX_op_shll_T0_T1,
3623 dc99065b bellard
3624 dc99065b bellard
    [INDEX_op_shrb_T0_T1_cc] = INDEX_op_shrb_T0_T1,
3625 dc99065b bellard
    [INDEX_op_shrw_T0_T1_cc] = INDEX_op_shrw_T0_T1,
3626 dc99065b bellard
    [INDEX_op_shrl_T0_T1_cc] = INDEX_op_shrl_T0_T1,
3627 dc99065b bellard
3628 dc99065b bellard
    [INDEX_op_sarb_T0_T1_cc] = INDEX_op_sarb_T0_T1,
3629 dc99065b bellard
    [INDEX_op_sarw_T0_T1_cc] = INDEX_op_sarw_T0_T1,
3630 dc99065b bellard
    [INDEX_op_sarl_T0_T1_cc] = INDEX_op_sarl_T0_T1,
3631 dc99065b bellard
};
3632 dc99065b bellard
3633 dc99065b bellard
static void optimize_flags_init(void)
3634 dc99065b bellard
{
3635 dc99065b bellard
    int i;
3636 dc99065b bellard
    /* put default values in arrays */
3637 dc99065b bellard
    for(i = 0; i < NB_OPS; i++) {
3638 dc99065b bellard
        if (opc_simpler[i] == 0)
3639 dc99065b bellard
            opc_simpler[i] = i;
3640 dc99065b bellard
    }
3641 dc99065b bellard
}
3642 dc99065b bellard
3643 dc99065b bellard
/* CPU flags computation optimization: we move backward thru the
3644 dc99065b bellard
   generated code to see which flags are needed. The operation is
3645 dc99065b bellard
   modified if suitable */
3646 dc99065b bellard
static void optimize_flags(uint16_t *opc_buf, int opc_buf_len)
3647 dc99065b bellard
{
3648 dc99065b bellard
    uint16_t *opc_ptr;
3649 dc99065b bellard
    int live_flags, write_flags, op;
3650 dc99065b bellard
3651 dc99065b bellard
    opc_ptr = opc_buf + opc_buf_len;
3652 dc99065b bellard
    /* live_flags contains the flags needed by the next instructions
3653 dc99065b bellard
       in the code. At the end of the bloc, we consider that all the
3654 dc99065b bellard
       flags are live. */
3655 dc99065b bellard
    live_flags = CC_OSZAPC;
3656 dc99065b bellard
    while (opc_ptr > opc_buf) {
3657 dc99065b bellard
        op = *--opc_ptr;
3658 dc99065b bellard
        /* if none of the flags written by the instruction is used,
3659 dc99065b bellard
           then we can try to find a simpler instruction */
3660 dc99065b bellard
        write_flags = opc_write_flags[op];
3661 dc99065b bellard
        if ((live_flags & write_flags) == 0) {
3662 dc99065b bellard
            *opc_ptr = opc_simpler[op];
3663 dc99065b bellard
        }
3664 dc99065b bellard
        /* compute the live flags before the instruction */
3665 dc99065b bellard
        live_flags &= ~write_flags;
3666 dc99065b bellard
        live_flags |= opc_read_flags[op];
3667 dc99065b bellard
    }
3668 dc99065b bellard
}
3669 dc99065b bellard
3670 dc99065b bellard
3671 dc99065b bellard
#ifdef DEBUG_DISAS
3672 dc99065b bellard
static const char *op_str[] = {
3673 9c605cb1 bellard
#define DEF(s, n) #s,
3674 9c605cb1 bellard
#include "opc-i386.h"
3675 9c605cb1 bellard
#undef DEF
3676 9c605cb1 bellard
};
3677 9c605cb1 bellard
3678 9c605cb1 bellard
static uint8_t op_nb_args[] = {
3679 9c605cb1 bellard
#define DEF(s, n) n,
3680 dc99065b bellard
#include "opc-i386.h"
3681 dc99065b bellard
#undef DEF
3682 dc99065b bellard
};
3683 dc99065b bellard
3684 9c605cb1 bellard
static void dump_ops(const uint16_t *opc_buf, const uint32_t *opparam_buf)
3685 dc99065b bellard
{
3686 dc99065b bellard
    const uint16_t *opc_ptr;
3687 9c605cb1 bellard
    const uint32_t *opparam_ptr;
3688 9c605cb1 bellard
    int c, n, i;
3689 9c605cb1 bellard
3690 dc99065b bellard
    opc_ptr = opc_buf;
3691 9c605cb1 bellard
    opparam_ptr = opparam_buf;
3692 dc99065b bellard
    for(;;) {
3693 dc99065b bellard
        c = *opc_ptr++;
3694 9c605cb1 bellard
        n = op_nb_args[c];
3695 366c1b8b bellard
        fprintf(logfile, "0x%04x: %s", 
3696 366c1b8b bellard
                (int)(opc_ptr - opc_buf - 1), op_str[c]);
3697 9c605cb1 bellard
        for(i = 0; i < n; i++) {
3698 9c605cb1 bellard
            fprintf(logfile, " 0x%x", opparam_ptr[i]);
3699 9c605cb1 bellard
        }
3700 9c605cb1 bellard
        fprintf(logfile, "\n");
3701 dc99065b bellard
        if (c == INDEX_op_end)
3702 dc99065b bellard
            break;
3703 9c605cb1 bellard
        opparam_ptr += n;
3704 dc99065b bellard
    }
3705 dc99065b bellard
}
3706 dc99065b bellard
3707 dc99065b bellard
#endif
3708 dc99065b bellard
3709 dc99065b bellard
/* XXX: make this buffer thread safe */
3710 dc99065b bellard
/* XXX: make safe guess about sizes */
3711 dc99065b bellard
#define MAX_OP_PER_INSTR 32
3712 dc99065b bellard
#define OPC_BUF_SIZE 512
3713 dc99065b bellard
#define OPC_MAX_SIZE (OPC_BUF_SIZE - MAX_OP_PER_INSTR)
3714 dc99065b bellard
3715 dc99065b bellard
#define OPPARAM_BUF_SIZE (OPC_BUF_SIZE * 3)
3716 dc99065b bellard
3717 dc99065b bellard
static uint16_t gen_opc_buf[OPC_BUF_SIZE];
3718 dc99065b bellard
static uint32_t gen_opparam_buf[OPPARAM_BUF_SIZE];
3719 dc99065b bellard
3720 9de5e440 bellard
/* return non zero if the very first instruction is invalid so that
3721 727d01d4 bellard
   the virtual CPU can trigger an exception. 
3722 727d01d4 bellard

3723 727d01d4 bellard
   '*code_size_ptr' contains the target code size including the
3724 727d01d4 bellard
   instruction which triggered an exception, except in case of invalid
3725 727d01d4 bellard
   illegal opcode. It must never exceed one target page. 
3726 727d01d4 bellard
   
3727 727d01d4 bellard
   '*gen_code_size_ptr' contains the size of the generated code (host
3728 727d01d4 bellard
   code).
3729 727d01d4 bellard
*/
3730 1017ebe9 bellard
int cpu_x86_gen_code(uint8_t *gen_code_buf, int max_code_size, 
3731 dab2ed99 bellard
                     int *gen_code_size_ptr,
3732 727d01d4 bellard
                     uint8_t *pc_start,  uint8_t *cs_base, int flags,
3733 d4e8164f bellard
                     int *code_size_ptr, TranslationBlock *tb)
3734 ba1c6e37 bellard
{
3735 ba1c6e37 bellard
    DisasContext dc1, *dc = &dc1;
3736 dc99065b bellard
    uint8_t *pc_ptr;
3737 dc99065b bellard
    uint16_t *gen_opc_end;
3738 04369ff2 bellard
    int gen_code_size;
3739 ba1c6e37 bellard
    long ret;
3740 dc99065b bellard
    
3741 dc99065b bellard
    /* generate intermediate code */
3742 dc99065b bellard
3743 6dbad63e bellard
    dc->code32 = (flags >> GEN_FLAG_CODE32_SHIFT) & 1;
3744 dab2ed99 bellard
    dc->ss32 = (flags >> GEN_FLAG_SS32_SHIFT) & 1;
3745 6dbad63e bellard
    dc->addseg = (flags >> GEN_FLAG_ADDSEG_SHIFT) & 1;
3746 6dbad63e bellard
    dc->f_st = (flags >> GEN_FLAG_ST_SHIFT) & 7;
3747 9c605cb1 bellard
    dc->vm86 = (flags >> GEN_FLAG_VM_SHIFT) & 1;
3748 982b4315 bellard
    dc->cpl = (flags >> GEN_FLAG_CPL_SHIFT) & 3;
3749 982b4315 bellard
    dc->iopl = (flags >> GEN_FLAG_IOPL_SHIFT) & 3;
3750 c50c0c3f bellard
    dc->tf = (flags >> GEN_FLAG_TF_SHIFT) & 1;
3751 ba1c6e37 bellard
    dc->cc_op = CC_OP_DYNAMIC;
3752 dab2ed99 bellard
    dc->cs_base = cs_base;
3753 d4e8164f bellard
    dc->tb = tb;
3754 dc99065b bellard
3755 dc99065b bellard
    gen_opc_ptr = gen_opc_buf;
3756 dc99065b bellard
    gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
3757 dc99065b bellard
    gen_opparam_ptr = gen_opparam_buf;
3758 0ecfa993 bellard
3759 6dbad63e bellard
    dc->is_jmp = 0;
3760 1017ebe9 bellard
    pc_ptr = pc_start;
3761 1017ebe9 bellard
    do {
3762 6dbad63e bellard
        ret = disas_insn(dc, pc_ptr);
3763 1a9353d2 bellard
        if (ret == -1) {
3764 9de5e440 bellard
            /* we trigger an illegal instruction operation only if it
3765 9de5e440 bellard
               is the first instruction. Otherwise, we simply stop
3766 9de5e440 bellard
               generating the code just before it */
3767 9de5e440 bellard
            if (pc_ptr == pc_start)
3768 9de5e440 bellard
                return -1;
3769 9de5e440 bellard
            else
3770 9de5e440 bellard
                break;
3771 1a9353d2 bellard
        }
3772 1017ebe9 bellard
        pc_ptr = (void *)ret;
3773 c50c0c3f bellard
        /* if single step mode, we generate only one instruction and
3774 c50c0c3f bellard
           generate an exception */
3775 c50c0c3f bellard
        if (dc->tf)
3776 c50c0c3f bellard
            break;
3777 727d01d4 bellard
    } while (!dc->is_jmp && gen_opc_ptr < gen_opc_end && 
3778 727d01d4 bellard
             (pc_ptr - pc_start) < (TARGET_PAGE_SIZE - 32));
3779 0ecfa993 bellard
    /* we must store the eflags state if it is not already done */
3780 d4e8164f bellard
    if (dc->is_jmp != 3) {
3781 d4e8164f bellard
        if (dc->cc_op != CC_OP_DYNAMIC)
3782 d4e8164f bellard
            gen_op_set_cc_op(dc->cc_op);
3783 d4e8164f bellard
        if (dc->is_jmp != 1) {
3784 d4e8164f bellard
            /* we add an additionnal jmp to update the simulated PC */
3785 d4e8164f bellard
            gen_op_jmp_im(ret - (unsigned long)dc->cs_base);
3786 d4e8164f bellard
        }
3787 0ecfa993 bellard
    }
3788 c50c0c3f bellard
    if (dc->tf) {
3789 c50c0c3f bellard
        gen_op_raise_exception(EXCP01_SSTP);
3790 c50c0c3f bellard
    }
3791 d4e8164f bellard
    if (dc->is_jmp != 3) {
3792 d4e8164f bellard
        /* indicate that the hash table must be used to find the next TB */
3793 d4e8164f bellard
        gen_op_movl_T0_0();
3794 d4e8164f bellard
    }
3795 c50c0c3f bellard
3796 dc99065b bellard
    *gen_opc_ptr = INDEX_op_end;
3797 0ecfa993 bellard
3798 0ecfa993 bellard
#ifdef DEBUG_DISAS
3799 586314f2 bellard
    if (loglevel) {
3800 dc99065b bellard
        fprintf(logfile, "----------------\n");
3801 b9adb4a6 bellard
        fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start));
3802 b9adb4a6 bellard
        disas(logfile, pc_start, pc_ptr - pc_start,
3803 b9adb4a6 bellard
              dc->code32 ? DISAS_I386_I386 : DISAS_I386_I8086);
3804 1017ebe9 bellard
        fprintf(logfile, "\n");
3805 982b4315 bellard
3806 dc99065b bellard
        fprintf(logfile, "OP:\n");
3807 9c605cb1 bellard
        dump_ops(gen_opc_buf, gen_opparam_buf);
3808 dc99065b bellard
        fprintf(logfile, "\n");
3809 dc99065b bellard
    }
3810 dc99065b bellard
#endif
3811 dc99065b bellard
3812 dc99065b bellard
    /* optimize flag computations */
3813 dc99065b bellard
    optimize_flags(gen_opc_buf, gen_opc_ptr - gen_opc_buf);
3814 dc99065b bellard
3815 dc99065b bellard
#ifdef DEBUG_DISAS
3816 dc99065b bellard
    if (loglevel) {
3817 dc99065b bellard
        fprintf(logfile, "AFTER FLAGS OPT:\n");
3818 9c605cb1 bellard
        dump_ops(gen_opc_buf, gen_opparam_buf);
3819 dc99065b bellard
        fprintf(logfile, "\n");
3820 dc99065b bellard
    }
3821 dc99065b bellard
#endif
3822 dc99065b bellard
3823 dc99065b bellard
    /* generate machine code */
3824 d4e8164f bellard
    tb->tb_next_offset[0] = 0xffff;
3825 d4e8164f bellard
    tb->tb_next_offset[1] = 0xffff;
3826 d4e8164f bellard
    gen_code_size = dyngen_code(gen_code_buf, tb->tb_next_offset,
3827 d4e8164f bellard
#ifdef USE_DIRECT_JUMP
3828 d4e8164f bellard
                                tb->tb_jmp_offset,
3829 d4e8164f bellard
#else
3830 d4e8164f bellard
                                NULL,
3831 d4e8164f bellard
#endif
3832 d4e8164f bellard
                                gen_opc_buf, gen_opparam_buf);
3833 04369ff2 bellard
    flush_icache_range((unsigned long)gen_code_buf, (unsigned long)(gen_code_buf + gen_code_size));
3834 d4e8164f bellard
3835 04369ff2 bellard
    *gen_code_size_ptr = gen_code_size;
3836 727d01d4 bellard
    *code_size_ptr = pc_ptr - pc_start;
3837 dc99065b bellard
#ifdef DEBUG_DISAS
3838 dc99065b bellard
    if (loglevel) {
3839 0ecfa993 bellard
        fprintf(logfile, "OUT: [size=%d]\n", *gen_code_size_ptr);
3840 b9adb4a6 bellard
        disas(logfile, gen_code_buf, *gen_code_size_ptr, DISAS_TARGET);
3841 0ecfa993 bellard
        fprintf(logfile, "\n");
3842 1b6b029e bellard
        fflush(logfile);
3843 0ecfa993 bellard
    }
3844 0ecfa993 bellard
#endif
3845 ba1c6e37 bellard
    return 0;
3846 ba1c6e37 bellard
}
3847 ba1c6e37 bellard
3848 ba1c6e37 bellard
CPUX86State *cpu_x86_init(void)
3849 ba1c6e37 bellard
{
3850 ba1c6e37 bellard
    CPUX86State *env;
3851 ba1c6e37 bellard
    int i;
3852 dc99065b bellard
    static int inited;
3853 ba1c6e37 bellard
3854 7d13299d bellard
    cpu_x86_tblocks_init();
3855 7d13299d bellard
3856 ba1c6e37 bellard
    env = malloc(sizeof(CPUX86State));
3857 ba1c6e37 bellard
    if (!env)
3858 ba1c6e37 bellard
        return NULL;
3859 ba1c6e37 bellard
    memset(env, 0, sizeof(CPUX86State));
3860 ba1c6e37 bellard
    /* basic FPU init */
3861 ba1c6e37 bellard
    for(i = 0;i < 8; i++)
3862 ba1c6e37 bellard
        env->fptags[i] = 1;
3863 ba1c6e37 bellard
    env->fpuc = 0x37f;
3864 9c605cb1 bellard
    /* flags setup : we activate the IRQs by default as in user mode */
3865 9c605cb1 bellard
    env->eflags = 0x2 | IF_MASK;
3866 dc99065b bellard
3867 dc99065b bellard
    /* init various static tables */
3868 dc99065b bellard
    if (!inited) {
3869 dc99065b bellard
        inited = 1;
3870 dc99065b bellard
        optimize_flags_init();
3871 54936004 bellard
        page_init();
3872 dc99065b bellard
    }
3873 ba1c6e37 bellard
    return env;
3874 ba1c6e37 bellard
}
3875 ba1c6e37 bellard
3876 ba1c6e37 bellard
void cpu_x86_close(CPUX86State *env)
3877 ba1c6e37 bellard
{
3878 ba1c6e37 bellard
    free(env);
3879 ba1c6e37 bellard
}
3880 148dfc2a bellard
3881 148dfc2a bellard
static const char *cc_op_str[] = {
3882 148dfc2a bellard
    "DYNAMIC",
3883 148dfc2a bellard
    "EFLAGS",
3884 148dfc2a bellard
    "MUL",
3885 148dfc2a bellard
    "ADDB",
3886 148dfc2a bellard
    "ADDW",
3887 148dfc2a bellard
    "ADDL",
3888 148dfc2a bellard
    "ADCB",
3889 148dfc2a bellard
    "ADCW",
3890 148dfc2a bellard
    "ADCL",
3891 148dfc2a bellard
    "SUBB",
3892 148dfc2a bellard
    "SUBW",
3893 148dfc2a bellard
    "SUBL",
3894 148dfc2a bellard
    "SBBB",
3895 148dfc2a bellard
    "SBBW",
3896 148dfc2a bellard
    "SBBL",
3897 148dfc2a bellard
    "LOGICB",
3898 148dfc2a bellard
    "LOGICW",
3899 148dfc2a bellard
    "LOGICL",
3900 148dfc2a bellard
    "INCB",
3901 148dfc2a bellard
    "INCW",
3902 148dfc2a bellard
    "INCL",
3903 148dfc2a bellard
    "DECB",
3904 148dfc2a bellard
    "DECW",
3905 148dfc2a bellard
    "DECL",
3906 148dfc2a bellard
    "SHLB",
3907 148dfc2a bellard
    "SHLW",
3908 148dfc2a bellard
    "SHLL",
3909 148dfc2a bellard
    "SARB",
3910 148dfc2a bellard
    "SARW",
3911 148dfc2a bellard
    "SARL",
3912 148dfc2a bellard
};
3913 148dfc2a bellard
3914 148dfc2a bellard
void cpu_x86_dump_state(CPUX86State *env, FILE *f, int flags)
3915 148dfc2a bellard
{
3916 148dfc2a bellard
    int eflags;
3917 148dfc2a bellard
    char cc_op_name[32];
3918 148dfc2a bellard
3919 148dfc2a bellard
    eflags = env->eflags;
3920 148dfc2a bellard
    fprintf(f, "EAX=%08x EBX=%08x ECX=%08x EDX=%08x\n"
3921 148dfc2a bellard
            "ESI=%08x EDI=%08x EBP=%08x ESP=%08x\n"
3922 148dfc2a bellard
            "EIP=%08x EFL=%08x [%c%c%c%c%c%c%c]\n",
3923 148dfc2a bellard
            env->regs[R_EAX], env->regs[R_EBX], env->regs[R_ECX], env->regs[R_EDX], 
3924 148dfc2a bellard
            env->regs[R_ESI], env->regs[R_EDI], env->regs[R_EBP], env->regs[R_ESP], 
3925 148dfc2a bellard
            env->eip, eflags,
3926 148dfc2a bellard
            eflags & DF_MASK ? 'D' : '-',
3927 148dfc2a bellard
            eflags & CC_O ? 'O' : '-',
3928 148dfc2a bellard
            eflags & CC_S ? 'S' : '-',
3929 148dfc2a bellard
            eflags & CC_Z ? 'Z' : '-',
3930 148dfc2a bellard
            eflags & CC_A ? 'A' : '-',
3931 148dfc2a bellard
            eflags & CC_P ? 'P' : '-',
3932 148dfc2a bellard
            eflags & CC_C ? 'C' : '-');
3933 148dfc2a bellard
    fprintf(f, "CS=%04x SS=%04x DS=%04x ES=%04x FS=%04x GS=%04x\n",
3934 148dfc2a bellard
            env->segs[R_CS],
3935 148dfc2a bellard
            env->segs[R_SS],
3936 148dfc2a bellard
            env->segs[R_DS],
3937 148dfc2a bellard
            env->segs[R_ES],
3938 148dfc2a bellard
            env->segs[R_FS],
3939 148dfc2a bellard
            env->segs[R_GS]);
3940 148dfc2a bellard
    if (flags & X86_DUMP_CCOP) {
3941 148dfc2a bellard
        if ((unsigned)env->cc_op < CC_OP_NB)
3942 148dfc2a bellard
            strcpy(cc_op_name, cc_op_str[env->cc_op]);
3943 148dfc2a bellard
        else
3944 148dfc2a bellard
            snprintf(cc_op_name, sizeof(cc_op_name), "[%d]", env->cc_op);
3945 148dfc2a bellard
        fprintf(f, "CCS=%08x CCD=%08x CCO=%-8s\n",
3946 148dfc2a bellard
                env->cc_src, env->cc_dst, cc_op_name);
3947 148dfc2a bellard
    }
3948 148dfc2a bellard
    if (flags & X86_DUMP_FPU) {
3949 148dfc2a bellard
        fprintf(f, "ST0=%f ST1=%f ST2=%f ST3=%f\n", 
3950 148dfc2a bellard
                (double)env->fpregs[0], 
3951 148dfc2a bellard
                (double)env->fpregs[1], 
3952 148dfc2a bellard
                (double)env->fpregs[2], 
3953 148dfc2a bellard
                (double)env->fpregs[3]);
3954 148dfc2a bellard
        fprintf(f, "ST4=%f ST5=%f ST6=%f ST7=%f\n", 
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                (double)env->fpregs[4], 
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                (double)env->fpregs[5], 
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                (double)env->fpregs[7], 
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                (double)env->fpregs[8]);
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    }
3960 148dfc2a bellard
}