root / hw / sh_timer.c @ a3867ed2
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1 | cd1a3f68 | ths | /*
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2 | cd1a3f68 | ths | * SuperH Timer modules.
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3 | cd1a3f68 | ths | *
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4 | cd1a3f68 | ths | * Copyright (c) 2007 Magnus Damm
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5 | cd1a3f68 | ths | * Based on arm_timer.c by Paul Brook
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6 | cd1a3f68 | ths | * Copyright (c) 2005-2006 CodeSourcery.
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7 | cd1a3f68 | ths | *
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8 | cd1a3f68 | ths | * This code is licenced under the GPL.
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9 | cd1a3f68 | ths | */
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10 | cd1a3f68 | ths | |
11 | 87ecb68b | pbrook | #include "hw.h" |
12 | 87ecb68b | pbrook | #include "sh.h" |
13 | 87ecb68b | pbrook | #include "qemu-timer.h" |
14 | cd1a3f68 | ths | |
15 | cd1a3f68 | ths | //#define DEBUG_TIMER
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16 | cd1a3f68 | ths | |
17 | cd1a3f68 | ths | #define TIMER_TCR_TPSC (7 << 0) |
18 | cd1a3f68 | ths | #define TIMER_TCR_CKEG (3 << 3) |
19 | cd1a3f68 | ths | #define TIMER_TCR_UNIE (1 << 5) |
20 | cd1a3f68 | ths | #define TIMER_TCR_ICPE (3 << 6) |
21 | cd1a3f68 | ths | #define TIMER_TCR_UNF (1 << 8) |
22 | cd1a3f68 | ths | #define TIMER_TCR_ICPF (1 << 9) |
23 | cd1a3f68 | ths | #define TIMER_TCR_RESERVED (0x3f << 10) |
24 | cd1a3f68 | ths | |
25 | cd1a3f68 | ths | #define TIMER_FEAT_CAPT (1 << 0) |
26 | cd1a3f68 | ths | #define TIMER_FEAT_EXTCLK (1 << 1) |
27 | cd1a3f68 | ths | |
28 | e7786f27 | aurel32 | #define OFFSET_TCOR 0 |
29 | e7786f27 | aurel32 | #define OFFSET_TCNT 1 |
30 | e7786f27 | aurel32 | #define OFFSET_TCR 2 |
31 | e7786f27 | aurel32 | #define OFFSET_TCPR 3 |
32 | e7786f27 | aurel32 | |
33 | cd1a3f68 | ths | typedef struct { |
34 | cd1a3f68 | ths | ptimer_state *timer; |
35 | cd1a3f68 | ths | uint32_t tcnt; |
36 | cd1a3f68 | ths | uint32_t tcor; |
37 | cd1a3f68 | ths | uint32_t tcr; |
38 | cd1a3f68 | ths | uint32_t tcpr; |
39 | cd1a3f68 | ths | int freq;
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40 | cd1a3f68 | ths | int int_level;
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41 | 703243a0 | balrog | int old_level;
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42 | cd1a3f68 | ths | int feat;
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43 | cd1a3f68 | ths | int enabled;
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44 | 96e2fc41 | aurel32 | qemu_irq irq; |
45 | cd1a3f68 | ths | } sh_timer_state; |
46 | cd1a3f68 | ths | |
47 | cd1a3f68 | ths | /* Check all active timers, and schedule the next timer interrupt. */
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48 | cd1a3f68 | ths | |
49 | cd1a3f68 | ths | static void sh_timer_update(sh_timer_state *s) |
50 | cd1a3f68 | ths | { |
51 | 703243a0 | balrog | int new_level = s->int_level && (s->tcr & TIMER_TCR_UNIE);
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52 | 703243a0 | balrog | |
53 | 703243a0 | balrog | if (new_level != s->old_level)
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54 | 96e2fc41 | aurel32 | qemu_set_irq (s->irq, new_level); |
55 | 703243a0 | balrog | |
56 | 703243a0 | balrog | s->old_level = s->int_level; |
57 | 703243a0 | balrog | s->int_level = new_level; |
58 | cd1a3f68 | ths | } |
59 | cd1a3f68 | ths | |
60 | 9596ebb7 | pbrook | static uint32_t sh_timer_read(void *opaque, target_phys_addr_t offset) |
61 | cd1a3f68 | ths | { |
62 | cd1a3f68 | ths | sh_timer_state *s = (sh_timer_state *)opaque; |
63 | cd1a3f68 | ths | |
64 | cd1a3f68 | ths | switch (offset >> 2) { |
65 | e7786f27 | aurel32 | case OFFSET_TCOR:
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66 | cd1a3f68 | ths | return s->tcor;
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67 | e7786f27 | aurel32 | case OFFSET_TCNT:
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68 | cd1a3f68 | ths | return ptimer_get_count(s->timer);
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69 | e7786f27 | aurel32 | case OFFSET_TCR:
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70 | cd1a3f68 | ths | return s->tcr | (s->int_level ? TIMER_TCR_UNF : 0); |
71 | e7786f27 | aurel32 | case OFFSET_TCPR:
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72 | cd1a3f68 | ths | if (s->feat & TIMER_FEAT_CAPT)
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73 | cd1a3f68 | ths | return s->tcpr;
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74 | cd1a3f68 | ths | default:
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75 | cd1a3f68 | ths | cpu_abort (cpu_single_env, "sh_timer_read: Bad offset %x\n",
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76 | cd1a3f68 | ths | (int)offset);
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77 | cd1a3f68 | ths | return 0; |
78 | cd1a3f68 | ths | } |
79 | cd1a3f68 | ths | } |
80 | cd1a3f68 | ths | |
81 | cd1a3f68 | ths | static void sh_timer_write(void *opaque, target_phys_addr_t offset, |
82 | cd1a3f68 | ths | uint32_t value) |
83 | cd1a3f68 | ths | { |
84 | cd1a3f68 | ths | sh_timer_state *s = (sh_timer_state *)opaque; |
85 | cd1a3f68 | ths | int freq;
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86 | cd1a3f68 | ths | |
87 | cd1a3f68 | ths | switch (offset >> 2) { |
88 | e7786f27 | aurel32 | case OFFSET_TCOR:
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89 | cd1a3f68 | ths | s->tcor = value; |
90 | cd1a3f68 | ths | ptimer_set_limit(s->timer, s->tcor, 0);
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91 | cd1a3f68 | ths | break;
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92 | e7786f27 | aurel32 | case OFFSET_TCNT:
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93 | cd1a3f68 | ths | s->tcnt = value; |
94 | cd1a3f68 | ths | ptimer_set_count(s->timer, s->tcnt); |
95 | cd1a3f68 | ths | break;
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96 | e7786f27 | aurel32 | case OFFSET_TCR:
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97 | cd1a3f68 | ths | if (s->enabled) {
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98 | cd1a3f68 | ths | /* Pause the timer if it is running. This may cause some
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99 | cd1a3f68 | ths | inaccuracy dure to rounding, but avoids a whole lot of other
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100 | cd1a3f68 | ths | messyness. */
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101 | cd1a3f68 | ths | ptimer_stop(s->timer); |
102 | cd1a3f68 | ths | } |
103 | cd1a3f68 | ths | freq = s->freq; |
104 | cd1a3f68 | ths | /* ??? Need to recalculate expiry time after changing divisor. */
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105 | cd1a3f68 | ths | switch (value & TIMER_TCR_TPSC) {
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106 | cd1a3f68 | ths | case 0: freq >>= 2; break; |
107 | cd1a3f68 | ths | case 1: freq >>= 4; break; |
108 | cd1a3f68 | ths | case 2: freq >>= 6; break; |
109 | cd1a3f68 | ths | case 3: freq >>= 8; break; |
110 | cd1a3f68 | ths | case 4: freq >>= 10; break; |
111 | cd1a3f68 | ths | case 6: |
112 | cd1a3f68 | ths | case 7: if (s->feat & TIMER_FEAT_EXTCLK) break; |
113 | cd1a3f68 | ths | default: cpu_abort (cpu_single_env,
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114 | cd1a3f68 | ths | "sh_timer_write: Reserved TPSC value\n"); break; |
115 | cd1a3f68 | ths | } |
116 | cd1a3f68 | ths | switch ((value & TIMER_TCR_CKEG) >> 3) { |
117 | cd1a3f68 | ths | case 0: break; |
118 | cd1a3f68 | ths | case 1: |
119 | cd1a3f68 | ths | case 2: |
120 | cd1a3f68 | ths | case 3: if (s->feat & TIMER_FEAT_EXTCLK) break; |
121 | cd1a3f68 | ths | default: cpu_abort (cpu_single_env,
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122 | cd1a3f68 | ths | "sh_timer_write: Reserved CKEG value\n"); break; |
123 | cd1a3f68 | ths | } |
124 | cd1a3f68 | ths | switch ((value & TIMER_TCR_ICPE) >> 6) { |
125 | cd1a3f68 | ths | case 0: break; |
126 | cd1a3f68 | ths | case 2: |
127 | cd1a3f68 | ths | case 3: if (s->feat & TIMER_FEAT_CAPT) break; |
128 | cd1a3f68 | ths | default: cpu_abort (cpu_single_env,
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129 | cd1a3f68 | ths | "sh_timer_write: Reserved ICPE value\n"); break; |
130 | cd1a3f68 | ths | } |
131 | cd1a3f68 | ths | if ((value & TIMER_TCR_UNF) == 0) |
132 | cd1a3f68 | ths | s->int_level = 0;
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133 | cd1a3f68 | ths | |
134 | cd1a3f68 | ths | value &= ~TIMER_TCR_UNF; |
135 | cd1a3f68 | ths | |
136 | cd1a3f68 | ths | if ((value & TIMER_TCR_ICPF) && (!(s->feat & TIMER_FEAT_CAPT)))
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137 | cd1a3f68 | ths | cpu_abort (cpu_single_env, |
138 | cd1a3f68 | ths | "sh_timer_write: Reserved ICPF value\n");
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139 | cd1a3f68 | ths | |
140 | cd1a3f68 | ths | value &= ~TIMER_TCR_ICPF; /* capture not supported */
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141 | cd1a3f68 | ths | |
142 | cd1a3f68 | ths | if (value & TIMER_TCR_RESERVED)
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143 | cd1a3f68 | ths | cpu_abort (cpu_single_env, |
144 | cd1a3f68 | ths | "sh_timer_write: Reserved TCR bits set\n");
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145 | cd1a3f68 | ths | s->tcr = value; |
146 | cd1a3f68 | ths | ptimer_set_limit(s->timer, s->tcor, 0);
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147 | cd1a3f68 | ths | ptimer_set_freq(s->timer, freq); |
148 | cd1a3f68 | ths | if (s->enabled) {
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149 | cd1a3f68 | ths | /* Restart the timer if still enabled. */
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150 | cd1a3f68 | ths | ptimer_run(s->timer, 0);
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151 | cd1a3f68 | ths | } |
152 | cd1a3f68 | ths | break;
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153 | e7786f27 | aurel32 | case OFFSET_TCPR:
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154 | cd1a3f68 | ths | if (s->feat & TIMER_FEAT_CAPT) {
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155 | cd1a3f68 | ths | s->tcpr = value; |
156 | cd1a3f68 | ths | break;
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157 | cd1a3f68 | ths | } |
158 | cd1a3f68 | ths | default:
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159 | cd1a3f68 | ths | cpu_abort (cpu_single_env, "sh_timer_write: Bad offset %x\n",
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160 | cd1a3f68 | ths | (int)offset);
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161 | cd1a3f68 | ths | } |
162 | cd1a3f68 | ths | sh_timer_update(s); |
163 | cd1a3f68 | ths | } |
164 | cd1a3f68 | ths | |
165 | cd1a3f68 | ths | static void sh_timer_start_stop(void *opaque, int enable) |
166 | cd1a3f68 | ths | { |
167 | cd1a3f68 | ths | sh_timer_state *s = (sh_timer_state *)opaque; |
168 | cd1a3f68 | ths | |
169 | cd1a3f68 | ths | #ifdef DEBUG_TIMER
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170 | cd1a3f68 | ths | printf("sh_timer_start_stop %d (%d)\n", enable, s->enabled);
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171 | cd1a3f68 | ths | #endif
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172 | cd1a3f68 | ths | |
173 | cd1a3f68 | ths | if (s->enabled && !enable) {
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174 | cd1a3f68 | ths | ptimer_stop(s->timer); |
175 | cd1a3f68 | ths | } |
176 | cd1a3f68 | ths | if (!s->enabled && enable) {
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177 | cd1a3f68 | ths | ptimer_run(s->timer, 0);
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178 | cd1a3f68 | ths | } |
179 | cd1a3f68 | ths | s->enabled = !!enable; |
180 | cd1a3f68 | ths | |
181 | cd1a3f68 | ths | #ifdef DEBUG_TIMER
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182 | cd1a3f68 | ths | printf("sh_timer_start_stop done %d\n", s->enabled);
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183 | cd1a3f68 | ths | #endif
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184 | cd1a3f68 | ths | } |
185 | cd1a3f68 | ths | |
186 | cd1a3f68 | ths | static void sh_timer_tick(void *opaque) |
187 | cd1a3f68 | ths | { |
188 | cd1a3f68 | ths | sh_timer_state *s = (sh_timer_state *)opaque; |
189 | cd1a3f68 | ths | s->int_level = s->enabled; |
190 | cd1a3f68 | ths | sh_timer_update(s); |
191 | cd1a3f68 | ths | } |
192 | cd1a3f68 | ths | |
193 | 96e2fc41 | aurel32 | static void *sh_timer_init(uint32_t freq, int feat, qemu_irq irq) |
194 | cd1a3f68 | ths | { |
195 | cd1a3f68 | ths | sh_timer_state *s; |
196 | cd1a3f68 | ths | QEMUBH *bh; |
197 | cd1a3f68 | ths | |
198 | cd1a3f68 | ths | s = (sh_timer_state *)qemu_mallocz(sizeof(sh_timer_state));
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199 | cd1a3f68 | ths | s->freq = freq; |
200 | cd1a3f68 | ths | s->feat = feat; |
201 | cd1a3f68 | ths | s->tcor = 0xffffffff;
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202 | cd1a3f68 | ths | s->tcnt = 0xffffffff;
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203 | cd1a3f68 | ths | s->tcpr = 0xdeadbeef;
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204 | e7786f27 | aurel32 | s->tcr = 0;
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205 | cd1a3f68 | ths | s->enabled = 0;
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206 | 703243a0 | balrog | s->irq = irq; |
207 | cd1a3f68 | ths | |
208 | cd1a3f68 | ths | bh = qemu_bh_new(sh_timer_tick, s); |
209 | cd1a3f68 | ths | s->timer = ptimer_init(bh); |
210 | e7786f27 | aurel32 | |
211 | e7786f27 | aurel32 | sh_timer_write(s, OFFSET_TCOR >> 2, s->tcor);
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212 | e7786f27 | aurel32 | sh_timer_write(s, OFFSET_TCNT >> 2, s->tcnt);
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213 | e7786f27 | aurel32 | sh_timer_write(s, OFFSET_TCPR >> 2, s->tcpr);
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214 | e7786f27 | aurel32 | sh_timer_write(s, OFFSET_TCR >> 2, s->tcpr);
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215 | cd1a3f68 | ths | /* ??? Save/restore. */
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216 | cd1a3f68 | ths | return s;
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217 | cd1a3f68 | ths | } |
218 | cd1a3f68 | ths | |
219 | cd1a3f68 | ths | typedef struct { |
220 | cd1a3f68 | ths | void *timer[3]; |
221 | cd1a3f68 | ths | int level[3]; |
222 | cd1a3f68 | ths | uint32_t tocr; |
223 | cd1a3f68 | ths | uint32_t tstr; |
224 | cd1a3f68 | ths | int feat;
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225 | cd1a3f68 | ths | } tmu012_state; |
226 | cd1a3f68 | ths | |
227 | cd1a3f68 | ths | static uint32_t tmu012_read(void *opaque, target_phys_addr_t offset) |
228 | cd1a3f68 | ths | { |
229 | cd1a3f68 | ths | tmu012_state *s = (tmu012_state *)opaque; |
230 | cd1a3f68 | ths | |
231 | cd1a3f68 | ths | #ifdef DEBUG_TIMER
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232 | cd1a3f68 | ths | printf("tmu012_read 0x%lx\n", (unsigned long) offset); |
233 | cd1a3f68 | ths | #endif
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234 | cd1a3f68 | ths | |
235 | cd1a3f68 | ths | if (offset >= 0x20) { |
236 | cd1a3f68 | ths | if (!(s->feat & TMU012_FEAT_3CHAN))
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237 | cd1a3f68 | ths | cpu_abort (cpu_single_env, "tmu012_write: Bad channel offset %x\n",
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238 | cd1a3f68 | ths | (int)offset);
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239 | cd1a3f68 | ths | return sh_timer_read(s->timer[2], offset - 0x20); |
240 | cd1a3f68 | ths | } |
241 | cd1a3f68 | ths | |
242 | cd1a3f68 | ths | if (offset >= 0x14) |
243 | cd1a3f68 | ths | return sh_timer_read(s->timer[1], offset - 0x14); |
244 | cd1a3f68 | ths | |
245 | cd1a3f68 | ths | if (offset >= 0x08) |
246 | cd1a3f68 | ths | return sh_timer_read(s->timer[0], offset - 0x08); |
247 | cd1a3f68 | ths | |
248 | cd1a3f68 | ths | if (offset == 4) |
249 | cd1a3f68 | ths | return s->tstr;
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250 | cd1a3f68 | ths | |
251 | cd1a3f68 | ths | if ((s->feat & TMU012_FEAT_TOCR) && offset == 0) |
252 | cd1a3f68 | ths | return s->tocr;
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253 | cd1a3f68 | ths | |
254 | cd1a3f68 | ths | cpu_abort (cpu_single_env, "tmu012_write: Bad offset %x\n",
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255 | cd1a3f68 | ths | (int)offset);
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256 | cd1a3f68 | ths | return 0; |
257 | cd1a3f68 | ths | } |
258 | cd1a3f68 | ths | |
259 | cd1a3f68 | ths | static void tmu012_write(void *opaque, target_phys_addr_t offset, |
260 | cd1a3f68 | ths | uint32_t value) |
261 | cd1a3f68 | ths | { |
262 | cd1a3f68 | ths | tmu012_state *s = (tmu012_state *)opaque; |
263 | cd1a3f68 | ths | |
264 | cd1a3f68 | ths | #ifdef DEBUG_TIMER
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265 | cd1a3f68 | ths | printf("tmu012_write 0x%lx 0x%08x\n", (unsigned long) offset, value); |
266 | cd1a3f68 | ths | #endif
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267 | cd1a3f68 | ths | |
268 | cd1a3f68 | ths | if (offset >= 0x20) { |
269 | cd1a3f68 | ths | if (!(s->feat & TMU012_FEAT_3CHAN))
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270 | cd1a3f68 | ths | cpu_abort (cpu_single_env, "tmu012_write: Bad channel offset %x\n",
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271 | cd1a3f68 | ths | (int)offset);
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272 | cd1a3f68 | ths | sh_timer_write(s->timer[2], offset - 0x20, value); |
273 | cd1a3f68 | ths | return;
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274 | cd1a3f68 | ths | } |
275 | cd1a3f68 | ths | |
276 | cd1a3f68 | ths | if (offset >= 0x14) { |
277 | cd1a3f68 | ths | sh_timer_write(s->timer[1], offset - 0x14, value); |
278 | cd1a3f68 | ths | return;
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279 | cd1a3f68 | ths | } |
280 | cd1a3f68 | ths | |
281 | cd1a3f68 | ths | if (offset >= 0x08) { |
282 | cd1a3f68 | ths | sh_timer_write(s->timer[0], offset - 0x08, value); |
283 | cd1a3f68 | ths | return;
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284 | cd1a3f68 | ths | } |
285 | cd1a3f68 | ths | |
286 | cd1a3f68 | ths | if (offset == 4) { |
287 | cd1a3f68 | ths | sh_timer_start_stop(s->timer[0], value & (1 << 0)); |
288 | cd1a3f68 | ths | sh_timer_start_stop(s->timer[1], value & (1 << 1)); |
289 | cd1a3f68 | ths | if (s->feat & TMU012_FEAT_3CHAN)
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290 | cd1a3f68 | ths | sh_timer_start_stop(s->timer[2], value & (1 << 2)); |
291 | cd1a3f68 | ths | else
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292 | cd1a3f68 | ths | if (value & (1 << 2)) |
293 | cd1a3f68 | ths | cpu_abort (cpu_single_env, "tmu012_write: Bad channel\n");
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294 | cd1a3f68 | ths | |
295 | cd1a3f68 | ths | s->tstr = value; |
296 | cd1a3f68 | ths | return;
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297 | cd1a3f68 | ths | } |
298 | cd1a3f68 | ths | |
299 | cd1a3f68 | ths | if ((s->feat & TMU012_FEAT_TOCR) && offset == 0) { |
300 | cd1a3f68 | ths | s->tocr = value & (1 << 0); |
301 | cd1a3f68 | ths | } |
302 | cd1a3f68 | ths | } |
303 | cd1a3f68 | ths | |
304 | cd1a3f68 | ths | static CPUReadMemoryFunc *tmu012_readfn[] = {
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305 | cd1a3f68 | ths | tmu012_read, |
306 | cd1a3f68 | ths | tmu012_read, |
307 | cd1a3f68 | ths | tmu012_read |
308 | cd1a3f68 | ths | }; |
309 | cd1a3f68 | ths | |
310 | cd1a3f68 | ths | static CPUWriteMemoryFunc *tmu012_writefn[] = {
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311 | cd1a3f68 | ths | tmu012_write, |
312 | cd1a3f68 | ths | tmu012_write, |
313 | cd1a3f68 | ths | tmu012_write |
314 | cd1a3f68 | ths | }; |
315 | cd1a3f68 | ths | |
316 | 703243a0 | balrog | void tmu012_init(target_phys_addr_t base, int feat, uint32_t freq, |
317 | 96e2fc41 | aurel32 | qemu_irq ch0_irq, qemu_irq ch1_irq, |
318 | 96e2fc41 | aurel32 | qemu_irq ch2_irq0, qemu_irq ch2_irq1) |
319 | cd1a3f68 | ths | { |
320 | cd1a3f68 | ths | int iomemtype;
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321 | cd1a3f68 | ths | tmu012_state *s; |
322 | cd1a3f68 | ths | int timer_feat = (feat & TMU012_FEAT_EXTCLK) ? TIMER_FEAT_EXTCLK : 0; |
323 | cd1a3f68 | ths | |
324 | cd1a3f68 | ths | s = (tmu012_state *)qemu_mallocz(sizeof(tmu012_state));
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325 | cd1a3f68 | ths | s->feat = feat; |
326 | 703243a0 | balrog | s->timer[0] = sh_timer_init(freq, timer_feat, ch0_irq);
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327 | 703243a0 | balrog | s->timer[1] = sh_timer_init(freq, timer_feat, ch1_irq);
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328 | cd1a3f68 | ths | if (feat & TMU012_FEAT_3CHAN)
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329 | 703243a0 | balrog | s->timer[2] = sh_timer_init(freq, timer_feat | TIMER_FEAT_CAPT,
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330 | 703243a0 | balrog | ch2_irq0); /* ch2_irq1 not supported */
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331 | cd1a3f68 | ths | iomemtype = cpu_register_io_memory(0, tmu012_readfn,
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332 | cd1a3f68 | ths | tmu012_writefn, s); |
333 | 5c16736a | balrog | cpu_register_physical_memory(P4ADDR(base), 0x00001000, iomemtype);
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334 | 5c16736a | balrog | cpu_register_physical_memory(A7ADDR(base), 0x00001000, iomemtype);
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335 | cd1a3f68 | ths | /* ??? Save/restore. */
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336 | cd1a3f68 | ths | } |