root / hw / integratorcp.c @ a3867ed2
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/*
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* ARM Integrator CP System emulation.
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*
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* Copyright (c) 2005-2007 CodeSourcery.
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* Written by Paul Brook
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*
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* This code is licenced under the GPL
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*/
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|
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#include "hw.h" |
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#include "primecell.h" |
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#include "devices.h" |
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#include "sysemu.h" |
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#include "boards.h" |
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#include "arm-misc.h" |
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#include "net.h" |
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|
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typedef struct { |
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uint32_t flash_offset; |
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uint32_t cm_osc; |
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uint32_t cm_ctrl; |
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uint32_t cm_lock; |
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uint32_t cm_auxosc; |
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uint32_t cm_sdram; |
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uint32_t cm_init; |
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uint32_t cm_flags; |
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uint32_t cm_nvflags; |
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uint32_t int_level; |
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uint32_t irq_enabled; |
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uint32_t fiq_enabled; |
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} integratorcm_state; |
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|
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static uint8_t integrator_spd[128] = { |
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128, 8, 4, 11, 9, 1, 64, 0, 2, 0xa0, 0xa0, 0, 0, 8, 0, 1, |
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0xe, 4, 0x1c, 1, 2, 0x20, 0xc0, 0, 0, 0, 0, 0x30, 0x28, 0x30, 0x28, 0x40 |
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}; |
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|
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static uint32_t integratorcm_read(void *opaque, target_phys_addr_t offset) |
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{ |
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integratorcm_state *s = (integratorcm_state *)opaque; |
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if (offset >= 0x100 && offset < 0x200) { |
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/* CM_SPD */
|
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if (offset >= 0x180) |
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return 0; |
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return integrator_spd[offset >> 2]; |
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} |
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switch (offset >> 2) { |
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case 0: /* CM_ID */ |
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return 0x411a3001; |
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case 1: /* CM_PROC */ |
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return 0; |
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case 2: /* CM_OSC */ |
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return s->cm_osc;
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case 3: /* CM_CTRL */ |
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return s->cm_ctrl;
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case 4: /* CM_STAT */ |
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return 0x00100000; |
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case 5: /* CM_LOCK */ |
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if (s->cm_lock == 0xa05f) { |
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return 0x1a05f; |
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} else {
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return s->cm_lock;
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} |
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case 6: /* CM_LMBUSCNT */ |
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/* ??? High frequency timer. */
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cpu_abort(cpu_single_env, "integratorcm_read: CM_LMBUSCNT");
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case 7: /* CM_AUXOSC */ |
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return s->cm_auxosc;
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case 8: /* CM_SDRAM */ |
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return s->cm_sdram;
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case 9: /* CM_INIT */ |
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return s->cm_init;
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case 10: /* CM_REFCT */ |
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/* ??? High frequency timer. */
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cpu_abort(cpu_single_env, "integratorcm_read: CM_REFCT");
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case 12: /* CM_FLAGS */ |
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return s->cm_flags;
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case 14: /* CM_NVFLAGS */ |
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return s->cm_nvflags;
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case 16: /* CM_IRQ_STAT */ |
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return s->int_level & s->irq_enabled;
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case 17: /* CM_IRQ_RSTAT */ |
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return s->int_level;
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case 18: /* CM_IRQ_ENSET */ |
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return s->irq_enabled;
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case 20: /* CM_SOFT_INTSET */ |
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return s->int_level & 1; |
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case 24: /* CM_FIQ_STAT */ |
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return s->int_level & s->fiq_enabled;
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case 25: /* CM_FIQ_RSTAT */ |
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return s->int_level;
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case 26: /* CM_FIQ_ENSET */ |
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return s->fiq_enabled;
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case 32: /* CM_VOLTAGE_CTL0 */ |
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case 33: /* CM_VOLTAGE_CTL1 */ |
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case 34: /* CM_VOLTAGE_CTL2 */ |
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case 35: /* CM_VOLTAGE_CTL3 */ |
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/* ??? Voltage control unimplemented. */
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return 0; |
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default:
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cpu_abort (cpu_single_env, |
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"integratorcm_read: Unimplemented offset 0x%x\n", (int)offset); |
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return 0; |
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} |
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} |
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|
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static void integratorcm_do_remap(integratorcm_state *s, int flash) |
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{ |
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if (flash) {
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cpu_register_physical_memory(0, 0x100000, IO_MEM_RAM); |
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} else {
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cpu_register_physical_memory(0, 0x100000, s->flash_offset | IO_MEM_RAM); |
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} |
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//??? tlb_flush (cpu_single_env, 1);
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} |
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|
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static void integratorcm_set_ctrl(integratorcm_state *s, uint32_t value) |
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{ |
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if (value & 8) { |
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cpu_abort(cpu_single_env, "Board reset\n");
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} |
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if ((s->cm_init ^ value) & 4) { |
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integratorcm_do_remap(s, (value & 4) == 0); |
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} |
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if ((s->cm_init ^ value) & 1) { |
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printf("Green LED %s\n", (value & 1) ? "on" : "off"); |
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} |
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s->cm_init = (s->cm_init & ~ 5) | (value ^ 5); |
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} |
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|
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static void integratorcm_update(integratorcm_state *s) |
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{ |
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/* ??? The CPU irq/fiq is raised when either the core module or base PIC
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are active. */
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if (s->int_level & (s->irq_enabled | s->fiq_enabled))
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cpu_abort(cpu_single_env, "Core module interrupt\n");
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} |
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|
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static void integratorcm_write(void *opaque, target_phys_addr_t offset, |
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uint32_t value) |
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{ |
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integratorcm_state *s = (integratorcm_state *)opaque; |
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switch (offset >> 2) { |
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case 2: /* CM_OSC */ |
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if (s->cm_lock == 0xa05f) |
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s->cm_osc = value; |
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break;
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case 3: /* CM_CTRL */ |
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integratorcm_set_ctrl(s, value); |
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break;
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case 5: /* CM_LOCK */ |
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s->cm_lock = value & 0xffff;
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break;
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case 7: /* CM_AUXOSC */ |
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if (s->cm_lock == 0xa05f) |
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s->cm_auxosc = value; |
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break;
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case 8: /* CM_SDRAM */ |
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s->cm_sdram = value; |
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break;
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case 9: /* CM_INIT */ |
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/* ??? This can change the memory bus frequency. */
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s->cm_init = value; |
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break;
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case 12: /* CM_FLAGSS */ |
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s->cm_flags |= value; |
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break;
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case 13: /* CM_FLAGSC */ |
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s->cm_flags &= ~value; |
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break;
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case 14: /* CM_NVFLAGSS */ |
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s->cm_nvflags |= value; |
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break;
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case 15: /* CM_NVFLAGSS */ |
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s->cm_nvflags &= ~value; |
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break;
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case 18: /* CM_IRQ_ENSET */ |
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s->irq_enabled |= value; |
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integratorcm_update(s); |
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break;
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case 19: /* CM_IRQ_ENCLR */ |
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s->irq_enabled &= ~value; |
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integratorcm_update(s); |
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break;
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case 20: /* CM_SOFT_INTSET */ |
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s->int_level |= (value & 1);
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integratorcm_update(s); |
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break;
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case 21: /* CM_SOFT_INTCLR */ |
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s->int_level &= ~(value & 1);
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integratorcm_update(s); |
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break;
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case 26: /* CM_FIQ_ENSET */ |
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s->fiq_enabled |= value; |
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integratorcm_update(s); |
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break;
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case 27: /* CM_FIQ_ENCLR */ |
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s->fiq_enabled &= ~value; |
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integratorcm_update(s); |
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break;
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case 32: /* CM_VOLTAGE_CTL0 */ |
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case 33: /* CM_VOLTAGE_CTL1 */ |
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case 34: /* CM_VOLTAGE_CTL2 */ |
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case 35: /* CM_VOLTAGE_CTL3 */ |
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/* ??? Voltage control unimplemented. */
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break;
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default:
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cpu_abort (cpu_single_env, |
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"integratorcm_write: Unimplemented offset 0x%x\n", (int)offset); |
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break;
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} |
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} |
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|
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/* Integrator/CM control registers. */
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|
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static CPUReadMemoryFunc *integratorcm_readfn[] = {
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integratorcm_read, |
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integratorcm_read, |
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integratorcm_read |
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}; |
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|
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static CPUWriteMemoryFunc *integratorcm_writefn[] = {
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integratorcm_write, |
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integratorcm_write, |
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integratorcm_write |
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}; |
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|
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static void integratorcm_init(int memsz) |
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{ |
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int iomemtype;
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integratorcm_state *s; |
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s = (integratorcm_state *)qemu_mallocz(sizeof(integratorcm_state));
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s->cm_osc = 0x01000048;
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/* ??? What should the high bits of this value be? */
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s->cm_auxosc = 0x0007feff;
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s->cm_sdram = 0x00011122;
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if (memsz >= 256) { |
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integrator_spd[31] = 64; |
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s->cm_sdram |= 0x10;
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} else if (memsz >= 128) { |
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integrator_spd[31] = 32; |
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s->cm_sdram |= 0x0c;
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} else if (memsz >= 64) { |
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integrator_spd[31] = 16; |
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s->cm_sdram |= 0x08;
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} else if (memsz >= 32) { |
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integrator_spd[31] = 4; |
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s->cm_sdram |= 0x04;
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} else {
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integrator_spd[31] = 2; |
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} |
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memcpy(integrator_spd + 73, "QEMU-MEMORY", 11); |
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s->cm_init = 0x00000112;
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s->flash_offset = qemu_ram_alloc(0x100000);
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iomemtype = cpu_register_io_memory(0, integratorcm_readfn,
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integratorcm_writefn, s); |
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cpu_register_physical_memory(0x10000000, 0x00800000, iomemtype); |
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integratorcm_do_remap(s, 1);
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/* ??? Save/restore. */
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} |
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|
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/* Integrator/CP hardware emulation. */
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/* Primary interrupt controller. */
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|
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typedef struct icp_pic_state |
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{ |
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uint32_t level; |
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uint32_t irq_enabled; |
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uint32_t fiq_enabled; |
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qemu_irq parent_irq; |
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qemu_irq parent_fiq; |
274 |
} icp_pic_state; |
275 |
|
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static void icp_pic_update(icp_pic_state *s) |
277 |
{ |
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uint32_t flags; |
279 |
|
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flags = (s->level & s->irq_enabled); |
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qemu_set_irq(s->parent_irq, flags != 0);
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flags = (s->level & s->fiq_enabled); |
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qemu_set_irq(s->parent_fiq, flags != 0);
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} |
285 |
|
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static void icp_pic_set_irq(void *opaque, int irq, int level) |
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{ |
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icp_pic_state *s = (icp_pic_state *)opaque; |
289 |
if (level)
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s->level |= 1 << irq;
|
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else
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s->level &= ~(1 << irq);
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icp_pic_update(s); |
294 |
} |
295 |
|
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static uint32_t icp_pic_read(void *opaque, target_phys_addr_t offset) |
297 |
{ |
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icp_pic_state *s = (icp_pic_state *)opaque; |
299 |
|
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switch (offset >> 2) { |
301 |
case 0: /* IRQ_STATUS */ |
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return s->level & s->irq_enabled;
|
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case 1: /* IRQ_RAWSTAT */ |
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return s->level;
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case 2: /* IRQ_ENABLESET */ |
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return s->irq_enabled;
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case 4: /* INT_SOFTSET */ |
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return s->level & 1; |
309 |
case 8: /* FRQ_STATUS */ |
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return s->level & s->fiq_enabled;
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case 9: /* FRQ_RAWSTAT */ |
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return s->level;
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case 10: /* FRQ_ENABLESET */ |
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return s->fiq_enabled;
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case 3: /* IRQ_ENABLECLR */ |
316 |
case 5: /* INT_SOFTCLR */ |
317 |
case 11: /* FRQ_ENABLECLR */ |
318 |
default:
|
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printf ("icp_pic_read: Bad register offset 0x%x\n", (int)offset); |
320 |
return 0; |
321 |
} |
322 |
} |
323 |
|
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static void icp_pic_write(void *opaque, target_phys_addr_t offset, |
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uint32_t value) |
326 |
{ |
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icp_pic_state *s = (icp_pic_state *)opaque; |
328 |
|
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switch (offset >> 2) { |
330 |
case 2: /* IRQ_ENABLESET */ |
331 |
s->irq_enabled |= value; |
332 |
break;
|
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case 3: /* IRQ_ENABLECLR */ |
334 |
s->irq_enabled &= ~value; |
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break;
|
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case 4: /* INT_SOFTSET */ |
337 |
if (value & 1) |
338 |
icp_pic_set_irq(s, 0, 1); |
339 |
break;
|
340 |
case 5: /* INT_SOFTCLR */ |
341 |
if (value & 1) |
342 |
icp_pic_set_irq(s, 0, 0); |
343 |
break;
|
344 |
case 10: /* FRQ_ENABLESET */ |
345 |
s->fiq_enabled |= value; |
346 |
break;
|
347 |
case 11: /* FRQ_ENABLECLR */ |
348 |
s->fiq_enabled &= ~value; |
349 |
break;
|
350 |
case 0: /* IRQ_STATUS */ |
351 |
case 1: /* IRQ_RAWSTAT */ |
352 |
case 8: /* FRQ_STATUS */ |
353 |
case 9: /* FRQ_RAWSTAT */ |
354 |
default:
|
355 |
printf ("icp_pic_write: Bad register offset 0x%x\n", (int)offset); |
356 |
return;
|
357 |
} |
358 |
icp_pic_update(s); |
359 |
} |
360 |
|
361 |
static CPUReadMemoryFunc *icp_pic_readfn[] = {
|
362 |
icp_pic_read, |
363 |
icp_pic_read, |
364 |
icp_pic_read |
365 |
}; |
366 |
|
367 |
static CPUWriteMemoryFunc *icp_pic_writefn[] = {
|
368 |
icp_pic_write, |
369 |
icp_pic_write, |
370 |
icp_pic_write |
371 |
}; |
372 |
|
373 |
static qemu_irq *icp_pic_init(uint32_t base,
|
374 |
qemu_irq parent_irq, qemu_irq parent_fiq) |
375 |
{ |
376 |
icp_pic_state *s; |
377 |
int iomemtype;
|
378 |
qemu_irq *qi; |
379 |
|
380 |
s = (icp_pic_state *)qemu_mallocz(sizeof(icp_pic_state));
|
381 |
qi = qemu_allocate_irqs(icp_pic_set_irq, s, 32);
|
382 |
s->parent_irq = parent_irq; |
383 |
s->parent_fiq = parent_fiq; |
384 |
iomemtype = cpu_register_io_memory(0, icp_pic_readfn,
|
385 |
icp_pic_writefn, s); |
386 |
cpu_register_physical_memory(base, 0x00800000, iomemtype);
|
387 |
/* ??? Save/restore. */
|
388 |
return qi;
|
389 |
} |
390 |
|
391 |
/* CP control registers. */
|
392 |
static uint32_t icp_control_read(void *opaque, target_phys_addr_t offset) |
393 |
{ |
394 |
switch (offset >> 2) { |
395 |
case 0: /* CP_IDFIELD */ |
396 |
return 0x41034003; |
397 |
case 1: /* CP_FLASHPROG */ |
398 |
return 0; |
399 |
case 2: /* CP_INTREG */ |
400 |
return 0; |
401 |
case 3: /* CP_DECODE */ |
402 |
return 0x11; |
403 |
default:
|
404 |
cpu_abort (cpu_single_env, "icp_control_read: Bad offset %x\n",
|
405 |
(int)offset);
|
406 |
return 0; |
407 |
} |
408 |
} |
409 |
|
410 |
static void icp_control_write(void *opaque, target_phys_addr_t offset, |
411 |
uint32_t value) |
412 |
{ |
413 |
switch (offset >> 2) { |
414 |
case 1: /* CP_FLASHPROG */ |
415 |
case 2: /* CP_INTREG */ |
416 |
case 3: /* CP_DECODE */ |
417 |
/* Nothing interesting implemented yet. */
|
418 |
break;
|
419 |
default:
|
420 |
cpu_abort (cpu_single_env, "icp_control_write: Bad offset %x\n",
|
421 |
(int)offset);
|
422 |
} |
423 |
} |
424 |
static CPUReadMemoryFunc *icp_control_readfn[] = {
|
425 |
icp_control_read, |
426 |
icp_control_read, |
427 |
icp_control_read |
428 |
}; |
429 |
|
430 |
static CPUWriteMemoryFunc *icp_control_writefn[] = {
|
431 |
icp_control_write, |
432 |
icp_control_write, |
433 |
icp_control_write |
434 |
}; |
435 |
|
436 |
static void icp_control_init(uint32_t base) |
437 |
{ |
438 |
int iomemtype;
|
439 |
|
440 |
iomemtype = cpu_register_io_memory(0, icp_control_readfn,
|
441 |
icp_control_writefn, NULL);
|
442 |
cpu_register_physical_memory(base, 0x00800000, iomemtype);
|
443 |
/* ??? Save/restore. */
|
444 |
} |
445 |
|
446 |
|
447 |
/* Board init. */
|
448 |
|
449 |
static struct arm_boot_info integrator_binfo = { |
450 |
.loader_start = 0x0,
|
451 |
.board_id = 0x113,
|
452 |
}; |
453 |
|
454 |
static void integratorcp_init(ram_addr_t ram_size, int vga_ram_size, |
455 |
const char *boot_device, |
456 |
const char *kernel_filename, const char *kernel_cmdline, |
457 |
const char *initrd_filename, const char *cpu_model) |
458 |
{ |
459 |
CPUState *env; |
460 |
ram_addr_t ram_offset; |
461 |
qemu_irq *pic; |
462 |
qemu_irq *cpu_pic; |
463 |
int sd;
|
464 |
|
465 |
if (!cpu_model)
|
466 |
cpu_model = "arm926";
|
467 |
env = cpu_init(cpu_model); |
468 |
if (!env) {
|
469 |
fprintf(stderr, "Unable to find CPU definition\n");
|
470 |
exit(1);
|
471 |
} |
472 |
ram_offset = qemu_ram_alloc(ram_size); |
473 |
/* ??? On a real system the first 1Mb is mapped as SSRAM or boot flash. */
|
474 |
/* ??? RAM should repeat to fill physical memory space. */
|
475 |
/* SDRAM at address zero*/
|
476 |
cpu_register_physical_memory(0, ram_size, ram_offset | IO_MEM_RAM);
|
477 |
/* And again at address 0x80000000 */
|
478 |
cpu_register_physical_memory(0x80000000, ram_size, ram_offset | IO_MEM_RAM);
|
479 |
|
480 |
integratorcm_init(ram_size >> 20);
|
481 |
cpu_pic = arm_pic_init_cpu(env); |
482 |
pic = icp_pic_init(0x14000000, cpu_pic[ARM_PIC_CPU_IRQ],
|
483 |
cpu_pic[ARM_PIC_CPU_FIQ]); |
484 |
icp_pic_init(0xca000000, pic[26], NULL); |
485 |
icp_pit_init(0x13000000, pic, 5); |
486 |
pl031_init(0x15000000, pic[8]); |
487 |
pl011_init(0x16000000, pic[1], serial_hds[0], PL011_ARM); |
488 |
pl011_init(0x17000000, pic[2], serial_hds[1], PL011_ARM); |
489 |
icp_control_init(0xcb000000);
|
490 |
pl050_init(0x18000000, pic[3], 0); |
491 |
pl050_init(0x19000000, pic[4], 1); |
492 |
sd = drive_get_index(IF_SD, 0, 0); |
493 |
if (sd == -1) { |
494 |
fprintf(stderr, "qemu: missing SecureDigital card\n");
|
495 |
exit(1);
|
496 |
} |
497 |
pl181_init(0x1c000000, drives_table[sd].bdrv, pic[23], pic[24]); |
498 |
if (nd_table[0].vlan) |
499 |
smc91c111_init(&nd_table[0], 0xc8000000, pic[27]); |
500 |
pl110_init(0xc0000000, pic[22], 0); |
501 |
|
502 |
integrator_binfo.ram_size = ram_size; |
503 |
integrator_binfo.kernel_filename = kernel_filename; |
504 |
integrator_binfo.kernel_cmdline = kernel_cmdline; |
505 |
integrator_binfo.initrd_filename = initrd_filename; |
506 |
arm_load_kernel(env, &integrator_binfo); |
507 |
} |
508 |
|
509 |
QEMUMachine integratorcp_machine = { |
510 |
.name = "integratorcp",
|
511 |
.desc = "ARM Integrator/CP (ARM926EJ-S)",
|
512 |
.init = integratorcp_init, |
513 |
}; |