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1 | 7d13299d | bellard | /*
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2 | 7d13299d | bellard | * i386 emulator main execution loop
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3 | 7d13299d | bellard | *
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4 | 7d13299d | bellard | * Copyright (c) 2003 Fabrice Bellard
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5 | 7d13299d | bellard | *
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6 | 3ef693a0 | bellard | * This library is free software; you can redistribute it and/or
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7 | 3ef693a0 | bellard | * modify it under the terms of the GNU Lesser General Public
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8 | 3ef693a0 | bellard | * License as published by the Free Software Foundation; either
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9 | 3ef693a0 | bellard | * version 2 of the License, or (at your option) any later version.
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10 | 7d13299d | bellard | *
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11 | 3ef693a0 | bellard | * This library is distributed in the hope that it will be useful,
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12 | 3ef693a0 | bellard | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 | 3ef693a0 | bellard | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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14 | 3ef693a0 | bellard | * Lesser General Public License for more details.
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15 | 7d13299d | bellard | *
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16 | 3ef693a0 | bellard | * You should have received a copy of the GNU Lesser General Public
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17 | 3ef693a0 | bellard | * License along with this library; if not, write to the Free Software
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18 | 3ef693a0 | bellard | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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19 | 7d13299d | bellard | */
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20 | e4533c7a | bellard | #include "config.h" |
21 | e4533c7a | bellard | #ifdef TARGET_I386
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22 | 7d13299d | bellard | #include "exec-i386.h" |
23 | e4533c7a | bellard | #endif
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24 | e4533c7a | bellard | #ifdef TARGET_ARM
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25 | e4533c7a | bellard | #include "exec-arm.h" |
26 | e4533c7a | bellard | #endif
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27 | e4533c7a | bellard | |
28 | 956034d7 | bellard | #include "disas.h" |
29 | 7d13299d | bellard | |
30 | dc99065b | bellard | //#define DEBUG_EXEC
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31 | 9de5e440 | bellard | //#define DEBUG_SIGNAL
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32 | 7d13299d | bellard | |
33 | e4533c7a | bellard | #if defined(TARGET_ARM)
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34 | e4533c7a | bellard | /* XXX: unify with i386 target */
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35 | e4533c7a | bellard | void cpu_loop_exit(void) |
36 | e4533c7a | bellard | { |
37 | e4533c7a | bellard | longjmp(env->jmp_env, 1);
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38 | e4533c7a | bellard | } |
39 | e4533c7a | bellard | #endif
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40 | e4533c7a | bellard | |
41 | 7d13299d | bellard | /* main execution loop */
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42 | 7d13299d | bellard | |
43 | e4533c7a | bellard | int cpu_exec(CPUState *env1)
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44 | 7d13299d | bellard | { |
45 | e4533c7a | bellard | int saved_T0, saved_T1, saved_T2;
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46 | e4533c7a | bellard | CPUState *saved_env; |
47 | 04369ff2 | bellard | #ifdef reg_EAX
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48 | 04369ff2 | bellard | int saved_EAX;
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49 | 04369ff2 | bellard | #endif
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50 | 04369ff2 | bellard | #ifdef reg_ECX
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51 | 04369ff2 | bellard | int saved_ECX;
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52 | 04369ff2 | bellard | #endif
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53 | 04369ff2 | bellard | #ifdef reg_EDX
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54 | 04369ff2 | bellard | int saved_EDX;
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55 | 04369ff2 | bellard | #endif
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56 | 04369ff2 | bellard | #ifdef reg_EBX
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57 | 04369ff2 | bellard | int saved_EBX;
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58 | 04369ff2 | bellard | #endif
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59 | 04369ff2 | bellard | #ifdef reg_ESP
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60 | 04369ff2 | bellard | int saved_ESP;
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61 | 04369ff2 | bellard | #endif
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62 | 04369ff2 | bellard | #ifdef reg_EBP
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63 | 04369ff2 | bellard | int saved_EBP;
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64 | 04369ff2 | bellard | #endif
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65 | 04369ff2 | bellard | #ifdef reg_ESI
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66 | 04369ff2 | bellard | int saved_ESI;
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67 | 04369ff2 | bellard | #endif
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68 | 04369ff2 | bellard | #ifdef reg_EDI
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69 | 04369ff2 | bellard | int saved_EDI;
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70 | 04369ff2 | bellard | #endif
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71 | 8c6939c0 | bellard | #ifdef __sparc__
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72 | 8c6939c0 | bellard | int saved_i7, tmp_T0;
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73 | 8c6939c0 | bellard | #endif
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74 | 68a79315 | bellard | int code_gen_size, ret, interrupt_request;
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75 | 7d13299d | bellard | void (*gen_func)(void); |
76 | 9de5e440 | bellard | TranslationBlock *tb, **ptb; |
77 | dab2ed99 | bellard | uint8_t *tc_ptr, *cs_base, *pc; |
78 | 6dbad63e | bellard | unsigned int flags; |
79 | 8c6939c0 | bellard | |
80 | 7d13299d | bellard | /* first we save global registers */
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81 | 7d13299d | bellard | saved_T0 = T0; |
82 | 7d13299d | bellard | saved_T1 = T1; |
83 | e4533c7a | bellard | saved_T2 = T2; |
84 | 7d13299d | bellard | saved_env = env; |
85 | 7d13299d | bellard | env = env1; |
86 | e4533c7a | bellard | #ifdef __sparc__
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87 | e4533c7a | bellard | /* we also save i7 because longjmp may not restore it */
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88 | e4533c7a | bellard | asm volatile ("mov %%i7, %0" : "=r" (saved_i7)); |
89 | e4533c7a | bellard | #endif
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90 | e4533c7a | bellard | |
91 | e4533c7a | bellard | #if defined(TARGET_I386)
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92 | 04369ff2 | bellard | #ifdef reg_EAX
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93 | 04369ff2 | bellard | saved_EAX = EAX; |
94 | 04369ff2 | bellard | EAX = env->regs[R_EAX]; |
95 | 04369ff2 | bellard | #endif
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96 | 04369ff2 | bellard | #ifdef reg_ECX
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97 | 04369ff2 | bellard | saved_ECX = ECX; |
98 | 04369ff2 | bellard | ECX = env->regs[R_ECX]; |
99 | 04369ff2 | bellard | #endif
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100 | 04369ff2 | bellard | #ifdef reg_EDX
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101 | 04369ff2 | bellard | saved_EDX = EDX; |
102 | 04369ff2 | bellard | EDX = env->regs[R_EDX]; |
103 | 04369ff2 | bellard | #endif
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104 | 04369ff2 | bellard | #ifdef reg_EBX
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105 | 04369ff2 | bellard | saved_EBX = EBX; |
106 | 04369ff2 | bellard | EBX = env->regs[R_EBX]; |
107 | 04369ff2 | bellard | #endif
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108 | 04369ff2 | bellard | #ifdef reg_ESP
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109 | 04369ff2 | bellard | saved_ESP = ESP; |
110 | 04369ff2 | bellard | ESP = env->regs[R_ESP]; |
111 | 04369ff2 | bellard | #endif
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112 | 04369ff2 | bellard | #ifdef reg_EBP
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113 | 04369ff2 | bellard | saved_EBP = EBP; |
114 | 04369ff2 | bellard | EBP = env->regs[R_EBP]; |
115 | 04369ff2 | bellard | #endif
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116 | 04369ff2 | bellard | #ifdef reg_ESI
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117 | 04369ff2 | bellard | saved_ESI = ESI; |
118 | 04369ff2 | bellard | ESI = env->regs[R_ESI]; |
119 | 04369ff2 | bellard | #endif
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120 | 04369ff2 | bellard | #ifdef reg_EDI
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121 | 04369ff2 | bellard | saved_EDI = EDI; |
122 | 04369ff2 | bellard | EDI = env->regs[R_EDI]; |
123 | 04369ff2 | bellard | #endif
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124 | 7d13299d | bellard | |
125 | 9de5e440 | bellard | /* put eflags in CPU temporary format */
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126 | fc2b4c48 | bellard | CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); |
127 | fc2b4c48 | bellard | DF = 1 - (2 * ((env->eflags >> 10) & 1)); |
128 | 9de5e440 | bellard | CC_OP = CC_OP_EFLAGS; |
129 | fc2b4c48 | bellard | env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); |
130 | e4533c7a | bellard | #elif defined(TARGET_ARM)
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131 | e4533c7a | bellard | { |
132 | e4533c7a | bellard | unsigned int psr; |
133 | e4533c7a | bellard | psr = env->cpsr; |
134 | e4533c7a | bellard | env->CF = (psr >> 29) & 1; |
135 | e4533c7a | bellard | env->NZF = (psr & 0xc0000000) ^ 0x40000000; |
136 | e4533c7a | bellard | env->VF = (psr << 3) & 0x80000000; |
137 | e4533c7a | bellard | env->cpsr = psr & ~0xf0000000;
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138 | e4533c7a | bellard | } |
139 | e4533c7a | bellard | #else
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140 | e4533c7a | bellard | #error unsupported target CPU
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141 | e4533c7a | bellard | #endif
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142 | 3fb2ded1 | bellard | env->exception_index = -1;
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143 | 9d27abd9 | bellard | |
144 | 7d13299d | bellard | /* prepare setjmp context for exception handling */
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145 | 3fb2ded1 | bellard | for(;;) {
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146 | 3fb2ded1 | bellard | if (setjmp(env->jmp_env) == 0) { |
147 | 3fb2ded1 | bellard | /* if an exception is pending, we execute it here */
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148 | 3fb2ded1 | bellard | if (env->exception_index >= 0) { |
149 | 3fb2ded1 | bellard | if (env->exception_index >= EXCP_INTERRUPT) {
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150 | 3fb2ded1 | bellard | /* exit request from the cpu execution loop */
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151 | 3fb2ded1 | bellard | ret = env->exception_index; |
152 | 3fb2ded1 | bellard | break;
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153 | 3fb2ded1 | bellard | } else if (env->user_mode_only) { |
154 | 3fb2ded1 | bellard | /* if user mode only, we simulate a fake exception
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155 | 3fb2ded1 | bellard | which will be hanlded outside the cpu execution
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156 | 3fb2ded1 | bellard | loop */
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157 | 83479e77 | bellard | #if defined(TARGET_I386)
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158 | 3fb2ded1 | bellard | do_interrupt_user(env->exception_index, |
159 | 3fb2ded1 | bellard | env->exception_is_int, |
160 | 3fb2ded1 | bellard | env->error_code, |
161 | 3fb2ded1 | bellard | env->exception_next_eip); |
162 | 83479e77 | bellard | #endif
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163 | 3fb2ded1 | bellard | ret = env->exception_index; |
164 | 3fb2ded1 | bellard | break;
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165 | 3fb2ded1 | bellard | } else {
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166 | 83479e77 | bellard | #if defined(TARGET_I386)
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167 | 3fb2ded1 | bellard | /* simulate a real cpu exception. On i386, it can
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168 | 3fb2ded1 | bellard | trigger new exceptions, but we do not handle
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169 | 3fb2ded1 | bellard | double or triple faults yet. */
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170 | 3fb2ded1 | bellard | do_interrupt(env->exception_index, |
171 | 3fb2ded1 | bellard | env->exception_is_int, |
172 | 3fb2ded1 | bellard | env->error_code, |
173 | 3fb2ded1 | bellard | env->exception_next_eip); |
174 | 83479e77 | bellard | #endif
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175 | 3fb2ded1 | bellard | } |
176 | 3fb2ded1 | bellard | env->exception_index = -1;
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177 | 3fb2ded1 | bellard | } |
178 | 3fb2ded1 | bellard | T0 = 0; /* force lookup of first TB */ |
179 | 3fb2ded1 | bellard | for(;;) {
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180 | 8c6939c0 | bellard | #ifdef __sparc__
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181 | 3fb2ded1 | bellard | /* g1 can be modified by some libc? functions */
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182 | 3fb2ded1 | bellard | tmp_T0 = T0; |
183 | 8c6939c0 | bellard | #endif
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184 | 68a79315 | bellard | interrupt_request = env->interrupt_request; |
185 | 68a79315 | bellard | if (interrupt_request) {
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186 | 68a79315 | bellard | #if defined(TARGET_I386)
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187 | 68a79315 | bellard | /* if hardware interrupt pending, we execute it */
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188 | 68a79315 | bellard | if ((interrupt_request & CPU_INTERRUPT_HARD) &&
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189 | 68a79315 | bellard | (env->eflags & IF_MASK)) { |
190 | 68a79315 | bellard | int intno;
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191 | 68a79315 | bellard | intno = cpu_x86_get_pic_interrupt(env); |
192 | 68a79315 | bellard | if (loglevel) {
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193 | 68a79315 | bellard | fprintf(logfile, "Servicing hardware INT=0x%02x\n", intno);
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194 | 68a79315 | bellard | } |
195 | 68a79315 | bellard | do_interrupt(intno, 0, 0, 0); |
196 | 68a79315 | bellard | env->interrupt_request &= ~CPU_INTERRUPT_HARD; |
197 | 907a5b26 | bellard | /* ensure that no TB jump will be modified as
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198 | 907a5b26 | bellard | the program flow was changed */
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199 | 907a5b26 | bellard | #ifdef __sparc__
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200 | 907a5b26 | bellard | tmp_T0 = 0;
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201 | 907a5b26 | bellard | #else
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202 | 907a5b26 | bellard | T0 = 0;
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203 | 907a5b26 | bellard | #endif
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204 | 68a79315 | bellard | } |
205 | 68a79315 | bellard | #endif
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206 | 68a79315 | bellard | if (interrupt_request & CPU_INTERRUPT_EXIT) {
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207 | 68a79315 | bellard | env->interrupt_request &= ~CPU_INTERRUPT_EXIT; |
208 | 68a79315 | bellard | env->exception_index = EXCP_INTERRUPT; |
209 | 68a79315 | bellard | cpu_loop_exit(); |
210 | 68a79315 | bellard | } |
211 | 3fb2ded1 | bellard | } |
212 | 7d13299d | bellard | #ifdef DEBUG_EXEC
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213 | 3fb2ded1 | bellard | if (loglevel) {
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214 | e4533c7a | bellard | #if defined(TARGET_I386)
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215 | 3fb2ded1 | bellard | /* restore flags in standard format */
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216 | 3fb2ded1 | bellard | env->regs[R_EAX] = EAX; |
217 | 3fb2ded1 | bellard | env->regs[R_EBX] = EBX; |
218 | 3fb2ded1 | bellard | env->regs[R_ECX] = ECX; |
219 | 3fb2ded1 | bellard | env->regs[R_EDX] = EDX; |
220 | 3fb2ded1 | bellard | env->regs[R_ESI] = ESI; |
221 | 3fb2ded1 | bellard | env->regs[R_EDI] = EDI; |
222 | 3fb2ded1 | bellard | env->regs[R_EBP] = EBP; |
223 | 3fb2ded1 | bellard | env->regs[R_ESP] = ESP; |
224 | 3fb2ded1 | bellard | env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK); |
225 | 68a79315 | bellard | cpu_x86_dump_state(env, logfile, X86_DUMP_CCOP); |
226 | 3fb2ded1 | bellard | env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); |
227 | e4533c7a | bellard | #elif defined(TARGET_ARM)
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228 | 1b21b62a | bellard | env->cpsr = compute_cpsr(); |
229 | 3fb2ded1 | bellard | cpu_arm_dump_state(env, logfile, 0);
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230 | 1b21b62a | bellard | env->cpsr &= ~0xf0000000;
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231 | e4533c7a | bellard | #else
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232 | e4533c7a | bellard | #error unsupported target CPU
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233 | e4533c7a | bellard | #endif
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234 | 3fb2ded1 | bellard | } |
235 | 7d13299d | bellard | #endif
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236 | 3fb2ded1 | bellard | /* we compute the CPU state. We assume it will not
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237 | 3fb2ded1 | bellard | change during the whole generated block. */
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238 | e4533c7a | bellard | #if defined(TARGET_I386)
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239 | 3fb2ded1 | bellard | flags = (env->segs[R_CS].flags & DESC_B_MASK) |
240 | 3fb2ded1 | bellard | >> (DESC_B_SHIFT - GEN_FLAG_CODE32_SHIFT); |
241 | 3fb2ded1 | bellard | flags |= (env->segs[R_SS].flags & DESC_B_MASK) |
242 | 3fb2ded1 | bellard | >> (DESC_B_SHIFT - GEN_FLAG_SS32_SHIFT); |
243 | 3fb2ded1 | bellard | flags |= (((unsigned long)env->segs[R_DS].base | |
244 | 3fb2ded1 | bellard | (unsigned long)env->segs[R_ES].base | |
245 | 3fb2ded1 | bellard | (unsigned long)env->segs[R_SS].base) != 0) << |
246 | 3fb2ded1 | bellard | GEN_FLAG_ADDSEG_SHIFT; |
247 | a412ac57 | bellard | if (env->cr[0] & CR0_PE_MASK) { |
248 | a412ac57 | bellard | if (!(env->eflags & VM_MASK))
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249 | a412ac57 | bellard | flags |= (env->segs[R_CS].selector & 3) <<
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250 | a412ac57 | bellard | GEN_FLAG_CPL_SHIFT; |
251 | a412ac57 | bellard | else
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252 | a412ac57 | bellard | flags |= (1 << GEN_FLAG_VM_SHIFT);
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253 | 3fb2ded1 | bellard | } |
254 | 3fb2ded1 | bellard | flags |= (env->eflags & (IOPL_MASK | TF_MASK)); |
255 | 3fb2ded1 | bellard | cs_base = env->segs[R_CS].base; |
256 | 3fb2ded1 | bellard | pc = cs_base + env->eip; |
257 | e4533c7a | bellard | #elif defined(TARGET_ARM)
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258 | 3fb2ded1 | bellard | flags = 0;
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259 | 3fb2ded1 | bellard | cs_base = 0;
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260 | 3fb2ded1 | bellard | pc = (uint8_t *)env->regs[15];
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261 | e4533c7a | bellard | #else
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262 | e4533c7a | bellard | #error unsupported CPU
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263 | e4533c7a | bellard | #endif
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264 | 3fb2ded1 | bellard | tb = tb_find(&ptb, (unsigned long)pc, (unsigned long)cs_base, |
265 | 3fb2ded1 | bellard | flags); |
266 | d4e8164f | bellard | if (!tb) {
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267 | 3fb2ded1 | bellard | spin_lock(&tb_lock); |
268 | 3fb2ded1 | bellard | /* if no translated code available, then translate it now */
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269 | d4e8164f | bellard | tb = tb_alloc((unsigned long)pc); |
270 | 3fb2ded1 | bellard | if (!tb) {
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271 | 3fb2ded1 | bellard | /* flush must be done */
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272 | 3fb2ded1 | bellard | tb_flush(); |
273 | 3fb2ded1 | bellard | /* cannot fail at this point */
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274 | 3fb2ded1 | bellard | tb = tb_alloc((unsigned long)pc); |
275 | 3fb2ded1 | bellard | /* don't forget to invalidate previous TB info */
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276 | 3fb2ded1 | bellard | ptb = &tb_hash[tb_hash_func((unsigned long)pc)]; |
277 | 3fb2ded1 | bellard | T0 = 0;
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278 | 3fb2ded1 | bellard | } |
279 | 3fb2ded1 | bellard | tc_ptr = code_gen_ptr; |
280 | 3fb2ded1 | bellard | tb->tc_ptr = tc_ptr; |
281 | 3fb2ded1 | bellard | tb->cs_base = (unsigned long)cs_base; |
282 | 3fb2ded1 | bellard | tb->flags = flags; |
283 | 4c3a88a2 | bellard | ret = cpu_gen_code(env, tb, CODE_GEN_MAX_SIZE, &code_gen_size); |
284 | e4533c7a | bellard | #if defined(TARGET_I386)
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285 | 3fb2ded1 | bellard | /* XXX: suppress that, this is incorrect */
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286 | 3fb2ded1 | bellard | /* if invalid instruction, signal it */
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287 | 3fb2ded1 | bellard | if (ret != 0) { |
288 | 3fb2ded1 | bellard | /* NOTE: the tb is allocated but not linked, so we
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289 | 3fb2ded1 | bellard | can leave it */
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290 | 3fb2ded1 | bellard | spin_unlock(&tb_lock); |
291 | 3fb2ded1 | bellard | raise_exception(EXCP06_ILLOP); |
292 | 3fb2ded1 | bellard | } |
293 | 3fb2ded1 | bellard | #endif
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294 | 3fb2ded1 | bellard | *ptb = tb; |
295 | 3fb2ded1 | bellard | tb->hash_next = NULL;
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296 | 3fb2ded1 | bellard | tb_link(tb); |
297 | 3fb2ded1 | bellard | code_gen_ptr = (void *)(((unsigned long)code_gen_ptr + code_gen_size + CODE_GEN_ALIGN - 1) & ~(CODE_GEN_ALIGN - 1)); |
298 | 25eb4484 | bellard | spin_unlock(&tb_lock); |
299 | 9de5e440 | bellard | } |
300 | 9d27abd9 | bellard | #ifdef DEBUG_EXEC
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301 | 3fb2ded1 | bellard | if (loglevel) {
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302 | 3fb2ded1 | bellard | fprintf(logfile, "Trace 0x%08lx [0x%08lx] %s\n",
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303 | 3fb2ded1 | bellard | (long)tb->tc_ptr, (long)tb->pc, |
304 | 3fb2ded1 | bellard | lookup_symbol((void *)tb->pc));
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305 | 3fb2ded1 | bellard | } |
306 | 9d27abd9 | bellard | #endif
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307 | 8c6939c0 | bellard | #ifdef __sparc__
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308 | 3fb2ded1 | bellard | T0 = tmp_T0; |
309 | 8c6939c0 | bellard | #endif
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310 | 3fb2ded1 | bellard | /* see if we can patch the calling TB. XXX: remove TF test */
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311 | 1b21b62a | bellard | if (T0 != 0 |
312 | e4533c7a | bellard | #if defined(TARGET_I386)
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313 | 3fb2ded1 | bellard | && !(env->eflags & TF_MASK) |
314 | e4533c7a | bellard | #endif
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315 | 3fb2ded1 | bellard | ) { |
316 | 3fb2ded1 | bellard | spin_lock(&tb_lock); |
317 | 3fb2ded1 | bellard | tb_add_jump((TranslationBlock *)(T0 & ~3), T0 & 3, tb); |
318 | 3fb2ded1 | bellard | spin_unlock(&tb_lock); |
319 | 3fb2ded1 | bellard | } |
320 | 3fb2ded1 | bellard | tc_ptr = tb->tc_ptr; |
321 | 83479e77 | bellard | env->current_tb = tb; |
322 | 3fb2ded1 | bellard | /* execute the generated code */
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323 | 3fb2ded1 | bellard | gen_func = (void *)tc_ptr;
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324 | 8c6939c0 | bellard | #if defined(__sparc__)
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325 | 3fb2ded1 | bellard | __asm__ __volatile__("call %0\n\t"
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326 | 3fb2ded1 | bellard | "mov %%o7,%%i0"
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327 | 3fb2ded1 | bellard | : /* no outputs */
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328 | 3fb2ded1 | bellard | : "r" (gen_func)
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329 | 3fb2ded1 | bellard | : "i0", "i1", "i2", "i3", "i4", "i5"); |
330 | 8c6939c0 | bellard | #elif defined(__arm__)
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331 | 3fb2ded1 | bellard | asm volatile ("mov pc, %0\n\t" |
332 | 3fb2ded1 | bellard | ".global exec_loop\n\t"
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333 | 3fb2ded1 | bellard | "exec_loop:\n\t"
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334 | 3fb2ded1 | bellard | : /* no outputs */
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335 | 3fb2ded1 | bellard | : "r" (gen_func)
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336 | 3fb2ded1 | bellard | : "r1", "r2", "r3", "r8", "r9", "r10", "r12", "r14"); |
337 | ae228531 | bellard | #else
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338 | 3fb2ded1 | bellard | gen_func(); |
339 | ae228531 | bellard | #endif
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340 | 83479e77 | bellard | env->current_tb = NULL;
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341 | 3fb2ded1 | bellard | } |
342 | 3fb2ded1 | bellard | } else {
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343 | 7d13299d | bellard | } |
344 | 3fb2ded1 | bellard | } /* for(;;) */
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345 | 3fb2ded1 | bellard | |
346 | 7d13299d | bellard | |
347 | e4533c7a | bellard | #if defined(TARGET_I386)
|
348 | 9de5e440 | bellard | /* restore flags in standard format */
|
349 | fc2b4c48 | bellard | env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK); |
350 | 9de5e440 | bellard | |
351 | 7d13299d | bellard | /* restore global registers */
|
352 | 04369ff2 | bellard | #ifdef reg_EAX
|
353 | 04369ff2 | bellard | EAX = saved_EAX; |
354 | 04369ff2 | bellard | #endif
|
355 | 04369ff2 | bellard | #ifdef reg_ECX
|
356 | 04369ff2 | bellard | ECX = saved_ECX; |
357 | 04369ff2 | bellard | #endif
|
358 | 04369ff2 | bellard | #ifdef reg_EDX
|
359 | 04369ff2 | bellard | EDX = saved_EDX; |
360 | 04369ff2 | bellard | #endif
|
361 | 04369ff2 | bellard | #ifdef reg_EBX
|
362 | 04369ff2 | bellard | EBX = saved_EBX; |
363 | 04369ff2 | bellard | #endif
|
364 | 04369ff2 | bellard | #ifdef reg_ESP
|
365 | 04369ff2 | bellard | ESP = saved_ESP; |
366 | 04369ff2 | bellard | #endif
|
367 | 04369ff2 | bellard | #ifdef reg_EBP
|
368 | 04369ff2 | bellard | EBP = saved_EBP; |
369 | 04369ff2 | bellard | #endif
|
370 | 04369ff2 | bellard | #ifdef reg_ESI
|
371 | 04369ff2 | bellard | ESI = saved_ESI; |
372 | 04369ff2 | bellard | #endif
|
373 | 04369ff2 | bellard | #ifdef reg_EDI
|
374 | 04369ff2 | bellard | EDI = saved_EDI; |
375 | 04369ff2 | bellard | #endif
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376 | e4533c7a | bellard | #elif defined(TARGET_ARM)
|
377 | 1b21b62a | bellard | env->cpsr = compute_cpsr(); |
378 | e4533c7a | bellard | #else
|
379 | e4533c7a | bellard | #error unsupported target CPU
|
380 | e4533c7a | bellard | #endif
|
381 | 8c6939c0 | bellard | #ifdef __sparc__
|
382 | 8c6939c0 | bellard | asm volatile ("mov %0, %%i7" : : "r" (saved_i7)); |
383 | 8c6939c0 | bellard | #endif
|
384 | 7d13299d | bellard | T0 = saved_T0; |
385 | 7d13299d | bellard | T1 = saved_T1; |
386 | e4533c7a | bellard | T2 = saved_T2; |
387 | 7d13299d | bellard | env = saved_env; |
388 | 7d13299d | bellard | return ret;
|
389 | 7d13299d | bellard | } |
390 | 6dbad63e | bellard | |
391 | e4533c7a | bellard | #if defined(TARGET_I386)
|
392 | e4533c7a | bellard | |
393 | 6dbad63e | bellard | void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector) |
394 | 6dbad63e | bellard | { |
395 | 6dbad63e | bellard | CPUX86State *saved_env; |
396 | 6dbad63e | bellard | |
397 | 6dbad63e | bellard | saved_env = env; |
398 | 6dbad63e | bellard | env = s; |
399 | a412ac57 | bellard | if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK)) { |
400 | a513fe19 | bellard | SegmentCache *sc; |
401 | a513fe19 | bellard | selector &= 0xffff;
|
402 | 970a87a6 | bellard | sc = &env->segs[seg_reg]; |
403 | a513fe19 | bellard | sc->base = (void *)(selector << 4); |
404 | a513fe19 | bellard | sc->limit = 0xffff;
|
405 | 3fb2ded1 | bellard | sc->flags = 0;
|
406 | 970a87a6 | bellard | sc->selector = selector; |
407 | a513fe19 | bellard | } else {
|
408 | a513fe19 | bellard | load_seg(seg_reg, selector, 0);
|
409 | a513fe19 | bellard | } |
410 | 6dbad63e | bellard | env = saved_env; |
411 | 6dbad63e | bellard | } |
412 | 9de5e440 | bellard | |
413 | d0a1ffc9 | bellard | void cpu_x86_fsave(CPUX86State *s, uint8_t *ptr, int data32) |
414 | d0a1ffc9 | bellard | { |
415 | d0a1ffc9 | bellard | CPUX86State *saved_env; |
416 | d0a1ffc9 | bellard | |
417 | d0a1ffc9 | bellard | saved_env = env; |
418 | d0a1ffc9 | bellard | env = s; |
419 | d0a1ffc9 | bellard | |
420 | d0a1ffc9 | bellard | helper_fsave(ptr, data32); |
421 | d0a1ffc9 | bellard | |
422 | d0a1ffc9 | bellard | env = saved_env; |
423 | d0a1ffc9 | bellard | } |
424 | d0a1ffc9 | bellard | |
425 | d0a1ffc9 | bellard | void cpu_x86_frstor(CPUX86State *s, uint8_t *ptr, int data32) |
426 | d0a1ffc9 | bellard | { |
427 | d0a1ffc9 | bellard | CPUX86State *saved_env; |
428 | d0a1ffc9 | bellard | |
429 | d0a1ffc9 | bellard | saved_env = env; |
430 | d0a1ffc9 | bellard | env = s; |
431 | d0a1ffc9 | bellard | |
432 | d0a1ffc9 | bellard | helper_frstor(ptr, data32); |
433 | d0a1ffc9 | bellard | |
434 | d0a1ffc9 | bellard | env = saved_env; |
435 | d0a1ffc9 | bellard | } |
436 | d0a1ffc9 | bellard | |
437 | e4533c7a | bellard | #endif /* TARGET_I386 */ |
438 | e4533c7a | bellard | |
439 | 9de5e440 | bellard | #undef EAX
|
440 | 9de5e440 | bellard | #undef ECX
|
441 | 9de5e440 | bellard | #undef EDX
|
442 | 9de5e440 | bellard | #undef EBX
|
443 | 9de5e440 | bellard | #undef ESP
|
444 | 9de5e440 | bellard | #undef EBP
|
445 | 9de5e440 | bellard | #undef ESI
|
446 | 9de5e440 | bellard | #undef EDI
|
447 | 9de5e440 | bellard | #undef EIP
|
448 | 9de5e440 | bellard | #include <signal.h> |
449 | 9de5e440 | bellard | #include <sys/ucontext.h> |
450 | 9de5e440 | bellard | |
451 | 3fb2ded1 | bellard | #if defined(TARGET_I386)
|
452 | 3fb2ded1 | bellard | |
453 | b56dad1c | bellard | /* 'pc' is the host PC at which the exception was raised. 'address' is
|
454 | fd6ce8f6 | bellard | the effective address of the memory exception. 'is_write' is 1 if a
|
455 | fd6ce8f6 | bellard | write caused the exception and otherwise 0'. 'old_set' is the
|
456 | fd6ce8f6 | bellard | signal set which should be restored */
|
457 | 2b413144 | bellard | static inline int handle_cpu_signal(unsigned long pc, unsigned long address, |
458 | 2b413144 | bellard | int is_write, sigset_t *old_set)
|
459 | 9de5e440 | bellard | { |
460 | a513fe19 | bellard | TranslationBlock *tb; |
461 | a513fe19 | bellard | int ret;
|
462 | 68a79315 | bellard | |
463 | 83479e77 | bellard | if (cpu_single_env)
|
464 | 83479e77 | bellard | env = cpu_single_env; /* XXX: find a correct solution for multithread */
|
465 | fd6ce8f6 | bellard | #if defined(DEBUG_SIGNAL)
|
466 | 3fb2ded1 | bellard | printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
|
467 | fd6ce8f6 | bellard | pc, address, is_write, *(unsigned long *)old_set); |
468 | 9de5e440 | bellard | #endif
|
469 | 25eb4484 | bellard | /* XXX: locking issue */
|
470 | fd6ce8f6 | bellard | if (is_write && page_unprotect(address)) {
|
471 | fd6ce8f6 | bellard | return 1; |
472 | fd6ce8f6 | bellard | } |
473 | 3fb2ded1 | bellard | /* see if it is an MMU fault */
|
474 | 3fb2ded1 | bellard | ret = cpu_x86_handle_mmu_fault(env, address, is_write); |
475 | 3fb2ded1 | bellard | if (ret < 0) |
476 | 3fb2ded1 | bellard | return 0; /* not an MMU fault */ |
477 | 3fb2ded1 | bellard | if (ret == 0) |
478 | 3fb2ded1 | bellard | return 1; /* the MMU fault was handled without causing real CPU fault */ |
479 | 3fb2ded1 | bellard | /* now we have a real cpu fault */
|
480 | a513fe19 | bellard | tb = tb_find_pc(pc); |
481 | a513fe19 | bellard | if (tb) {
|
482 | 9de5e440 | bellard | /* the PC is inside the translated code. It means that we have
|
483 | 9de5e440 | bellard | a virtual CPU fault */
|
484 | 3fb2ded1 | bellard | cpu_restore_state(tb, env, pc); |
485 | 3fb2ded1 | bellard | } |
486 | 3fb2ded1 | bellard | #if 0
|
487 | 3fb2ded1 | bellard | printf("PF exception: EIP=0x%08x CR2=0x%08x error=0x%x\n",
|
488 | 3fb2ded1 | bellard | env->eip, env->cr[2], env->error_code);
|
489 | 3fb2ded1 | bellard | #endif
|
490 | 3fb2ded1 | bellard | /* we restore the process signal mask as the sigreturn should
|
491 | 3fb2ded1 | bellard | do it (XXX: use sigsetjmp) */
|
492 | 3fb2ded1 | bellard | sigprocmask(SIG_SETMASK, old_set, NULL);
|
493 | 3fb2ded1 | bellard | raise_exception_err(EXCP0E_PAGE, env->error_code); |
494 | 3fb2ded1 | bellard | /* never comes here */
|
495 | 3fb2ded1 | bellard | return 1; |
496 | 3fb2ded1 | bellard | } |
497 | 3fb2ded1 | bellard | |
498 | e4533c7a | bellard | #elif defined(TARGET_ARM)
|
499 | 3fb2ded1 | bellard | static inline int handle_cpu_signal(unsigned long pc, unsigned long address, |
500 | 3fb2ded1 | bellard | int is_write, sigset_t *old_set)
|
501 | 3fb2ded1 | bellard | { |
502 | 3fb2ded1 | bellard | /* XXX: do more */
|
503 | 3fb2ded1 | bellard | return 0; |
504 | 3fb2ded1 | bellard | } |
505 | e4533c7a | bellard | #else
|
506 | e4533c7a | bellard | #error unsupported target CPU
|
507 | e4533c7a | bellard | #endif
|
508 | 9de5e440 | bellard | |
509 | 2b413144 | bellard | #if defined(__i386__)
|
510 | 2b413144 | bellard | |
511 | e4533c7a | bellard | int cpu_signal_handler(int host_signum, struct siginfo *info, |
512 | e4533c7a | bellard | void *puc)
|
513 | 9de5e440 | bellard | { |
514 | 9de5e440 | bellard | struct ucontext *uc = puc;
|
515 | 9de5e440 | bellard | unsigned long pc; |
516 | 9de5e440 | bellard | |
517 | d691f669 | bellard | #ifndef REG_EIP
|
518 | d691f669 | bellard | /* for glibc 2.1 */
|
519 | fd6ce8f6 | bellard | #define REG_EIP EIP
|
520 | fd6ce8f6 | bellard | #define REG_ERR ERR
|
521 | fd6ce8f6 | bellard | #define REG_TRAPNO TRAPNO
|
522 | d691f669 | bellard | #endif
|
523 | fc2b4c48 | bellard | pc = uc->uc_mcontext.gregs[REG_EIP]; |
524 | fd6ce8f6 | bellard | return handle_cpu_signal(pc, (unsigned long)info->si_addr, |
525 | fd6ce8f6 | bellard | uc->uc_mcontext.gregs[REG_TRAPNO] == 0xe ?
|
526 | fd6ce8f6 | bellard | (uc->uc_mcontext.gregs[REG_ERR] >> 1) & 1 : 0, |
527 | 2b413144 | bellard | &uc->uc_sigmask); |
528 | 2b413144 | bellard | } |
529 | 2b413144 | bellard | |
530 | 25eb4484 | bellard | #elif defined(__powerpc)
|
531 | 2b413144 | bellard | |
532 | e4533c7a | bellard | int cpu_signal_handler(int host_signum, struct siginfo *info, |
533 | e4533c7a | bellard | void *puc)
|
534 | 2b413144 | bellard | { |
535 | 25eb4484 | bellard | struct ucontext *uc = puc;
|
536 | 25eb4484 | bellard | struct pt_regs *regs = uc->uc_mcontext.regs;
|
537 | 25eb4484 | bellard | unsigned long pc; |
538 | 25eb4484 | bellard | int is_write;
|
539 | 25eb4484 | bellard | |
540 | 25eb4484 | bellard | pc = regs->nip; |
541 | 25eb4484 | bellard | is_write = 0;
|
542 | 25eb4484 | bellard | #if 0
|
543 | 25eb4484 | bellard | /* ppc 4xx case */
|
544 | 25eb4484 | bellard | if (regs->dsisr & 0x00800000)
|
545 | 25eb4484 | bellard | is_write = 1;
|
546 | 25eb4484 | bellard | #else
|
547 | 25eb4484 | bellard | if (regs->trap != 0x400 && (regs->dsisr & 0x02000000)) |
548 | 25eb4484 | bellard | is_write = 1;
|
549 | 25eb4484 | bellard | #endif
|
550 | 25eb4484 | bellard | return handle_cpu_signal(pc, (unsigned long)info->si_addr, |
551 | 2b413144 | bellard | is_write, &uc->uc_sigmask); |
552 | 2b413144 | bellard | } |
553 | 2b413144 | bellard | |
554 | 2f87c607 | bellard | #elif defined(__alpha__)
|
555 | 2f87c607 | bellard | |
556 | e4533c7a | bellard | int cpu_signal_handler(int host_signum, struct siginfo *info, |
557 | 2f87c607 | bellard | void *puc)
|
558 | 2f87c607 | bellard | { |
559 | 2f87c607 | bellard | struct ucontext *uc = puc;
|
560 | 2f87c607 | bellard | uint32_t *pc = uc->uc_mcontext.sc_pc; |
561 | 2f87c607 | bellard | uint32_t insn = *pc; |
562 | 2f87c607 | bellard | int is_write = 0; |
563 | 2f87c607 | bellard | |
564 | 8c6939c0 | bellard | /* XXX: need kernel patch to get write flag faster */
|
565 | 2f87c607 | bellard | switch (insn >> 26) { |
566 | 2f87c607 | bellard | case 0x0d: // stw |
567 | 2f87c607 | bellard | case 0x0e: // stb |
568 | 2f87c607 | bellard | case 0x0f: // stq_u |
569 | 2f87c607 | bellard | case 0x24: // stf |
570 | 2f87c607 | bellard | case 0x25: // stg |
571 | 2f87c607 | bellard | case 0x26: // sts |
572 | 2f87c607 | bellard | case 0x27: // stt |
573 | 2f87c607 | bellard | case 0x2c: // stl |
574 | 2f87c607 | bellard | case 0x2d: // stq |
575 | 2f87c607 | bellard | case 0x2e: // stl_c |
576 | 2f87c607 | bellard | case 0x2f: // stq_c |
577 | 2f87c607 | bellard | is_write = 1;
|
578 | 2f87c607 | bellard | } |
579 | 2f87c607 | bellard | |
580 | 2f87c607 | bellard | return handle_cpu_signal(pc, (unsigned long)info->si_addr, |
581 | 2f87c607 | bellard | is_write, &uc->uc_sigmask); |
582 | 2f87c607 | bellard | } |
583 | 8c6939c0 | bellard | #elif defined(__sparc__)
|
584 | 8c6939c0 | bellard | |
585 | e4533c7a | bellard | int cpu_signal_handler(int host_signum, struct siginfo *info, |
586 | e4533c7a | bellard | void *puc)
|
587 | 8c6939c0 | bellard | { |
588 | 8c6939c0 | bellard | uint32_t *regs = (uint32_t *)(info + 1);
|
589 | 8c6939c0 | bellard | void *sigmask = (regs + 20); |
590 | 8c6939c0 | bellard | unsigned long pc; |
591 | 8c6939c0 | bellard | int is_write;
|
592 | 8c6939c0 | bellard | uint32_t insn; |
593 | 8c6939c0 | bellard | |
594 | 8c6939c0 | bellard | /* XXX: is there a standard glibc define ? */
|
595 | 8c6939c0 | bellard | pc = regs[1];
|
596 | 8c6939c0 | bellard | /* XXX: need kernel patch to get write flag faster */
|
597 | 8c6939c0 | bellard | is_write = 0;
|
598 | 8c6939c0 | bellard | insn = *(uint32_t *)pc; |
599 | 8c6939c0 | bellard | if ((insn >> 30) == 3) { |
600 | 8c6939c0 | bellard | switch((insn >> 19) & 0x3f) { |
601 | 8c6939c0 | bellard | case 0x05: // stb |
602 | 8c6939c0 | bellard | case 0x06: // sth |
603 | 8c6939c0 | bellard | case 0x04: // st |
604 | 8c6939c0 | bellard | case 0x07: // std |
605 | 8c6939c0 | bellard | case 0x24: // stf |
606 | 8c6939c0 | bellard | case 0x27: // stdf |
607 | 8c6939c0 | bellard | case 0x25: // stfsr |
608 | 8c6939c0 | bellard | is_write = 1;
|
609 | 8c6939c0 | bellard | break;
|
610 | 8c6939c0 | bellard | } |
611 | 8c6939c0 | bellard | } |
612 | 8c6939c0 | bellard | return handle_cpu_signal(pc, (unsigned long)info->si_addr, |
613 | 8c6939c0 | bellard | is_write, sigmask); |
614 | 8c6939c0 | bellard | } |
615 | 8c6939c0 | bellard | |
616 | 8c6939c0 | bellard | #elif defined(__arm__)
|
617 | 8c6939c0 | bellard | |
618 | e4533c7a | bellard | int cpu_signal_handler(int host_signum, struct siginfo *info, |
619 | e4533c7a | bellard | void *puc)
|
620 | 8c6939c0 | bellard | { |
621 | 8c6939c0 | bellard | struct ucontext *uc = puc;
|
622 | 8c6939c0 | bellard | unsigned long pc; |
623 | 8c6939c0 | bellard | int is_write;
|
624 | 8c6939c0 | bellard | |
625 | 8c6939c0 | bellard | pc = uc->uc_mcontext.gregs[R15]; |
626 | 8c6939c0 | bellard | /* XXX: compute is_write */
|
627 | 8c6939c0 | bellard | is_write = 0;
|
628 | 8c6939c0 | bellard | return handle_cpu_signal(pc, (unsigned long)info->si_addr, |
629 | 8c6939c0 | bellard | is_write, |
630 | 8c6939c0 | bellard | &uc->uc_sigmask); |
631 | 8c6939c0 | bellard | } |
632 | 8c6939c0 | bellard | |
633 | 9de5e440 | bellard | #else
|
634 | 2b413144 | bellard | |
635 | 3fb2ded1 | bellard | #error host CPU specific signal handler needed
|
636 | 2b413144 | bellard | |
637 | 9de5e440 | bellard | #endif |