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1 | 3ef693a0 | bellard | /*
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2 | 3ef693a0 | bellard | * i386 execution defines
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3 | 3ef693a0 | bellard | *
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4 | 3ef693a0 | bellard | * Copyright (c) 2003 Fabrice Bellard
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5 | 3ef693a0 | bellard | *
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6 | 3ef693a0 | bellard | * This library is free software; you can redistribute it and/or
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7 | 3ef693a0 | bellard | * modify it under the terms of the GNU Lesser General Public
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8 | 3ef693a0 | bellard | * License as published by the Free Software Foundation; either
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9 | 3ef693a0 | bellard | * version 2 of the License, or (at your option) any later version.
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10 | 3ef693a0 | bellard | *
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11 | 3ef693a0 | bellard | * This library is distributed in the hope that it will be useful,
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12 | 3ef693a0 | bellard | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 | 3ef693a0 | bellard | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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14 | 3ef693a0 | bellard | * Lesser General Public License for more details.
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15 | 3ef693a0 | bellard | *
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16 | 3ef693a0 | bellard | * You should have received a copy of the GNU Lesser General Public
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17 | 3ef693a0 | bellard | * License along with this library; if not, write to the Free Software
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18 | 3ef693a0 | bellard | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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19 | 3ef693a0 | bellard | */
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20 | 79638566 | bellard | #include "dyngen-exec.h" |
21 | 79638566 | bellard | |
22 | 79638566 | bellard | /* at least 4 register variables are defines */
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23 | 79638566 | bellard | register struct CPUX86State *env asm(AREG0); |
24 | 79638566 | bellard | register uint32_t T0 asm(AREG1); |
25 | 79638566 | bellard | register uint32_t T1 asm(AREG2); |
26 | 79638566 | bellard | register uint32_t T2 asm(AREG3); |
27 | 79638566 | bellard | |
28 | 79638566 | bellard | #define A0 T2
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29 | 79638566 | bellard | |
30 | 79638566 | bellard | /* if more registers are available, we define some registers too */
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31 | 79638566 | bellard | #ifdef AREG4
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32 | 79638566 | bellard | register uint32_t EAX asm(AREG4); |
33 | 04369ff2 | bellard | #define reg_EAX
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34 | 7d13299d | bellard | #endif
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35 | 79638566 | bellard | |
36 | 79638566 | bellard | #ifdef AREG5
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37 | 79638566 | bellard | register uint32_t ESP asm(AREG5); |
38 | ae228531 | bellard | #define reg_ESP
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39 | 79638566 | bellard | #endif
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40 | 79638566 | bellard | |
41 | 79638566 | bellard | #ifdef AREG6
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42 | 79638566 | bellard | register uint32_t EBP asm(AREG6); |
43 | ae228531 | bellard | #define reg_EBP
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44 | 7d13299d | bellard | #endif
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45 | 79638566 | bellard | |
46 | 79638566 | bellard | #ifdef AREG7
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47 | 79638566 | bellard | register uint32_t ECX asm(AREG7); |
48 | 79638566 | bellard | #define reg_ECX
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49 | fb3e5849 | bellard | #endif
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50 | 79638566 | bellard | |
51 | 79638566 | bellard | #ifdef AREG8
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52 | 79638566 | bellard | register uint32_t EDX asm(AREG8); |
53 | 79638566 | bellard | #define reg_EDX
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54 | d03cda59 | bellard | #endif
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55 | 79638566 | bellard | |
56 | 79638566 | bellard | #ifdef AREG9
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57 | 79638566 | bellard | register uint32_t EBX asm(AREG9); |
58 | 79638566 | bellard | #define reg_EBX
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59 | 0d330196 | bellard | #endif
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60 | 7d13299d | bellard | |
61 | 79638566 | bellard | #ifdef AREG10
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62 | 79638566 | bellard | register uint32_t ESI asm(AREG10); |
63 | 79638566 | bellard | #define reg_ESI
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64 | 79638566 | bellard | #endif
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65 | 7d13299d | bellard | |
66 | 79638566 | bellard | #ifdef AREG11
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67 | 79638566 | bellard | register uint32_t EDI asm(AREG11); |
68 | 79638566 | bellard | #define reg_EDI
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69 | 7d13299d | bellard | #endif
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70 | 7d13299d | bellard | |
71 | 79638566 | bellard | extern FILE *logfile;
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72 | 79638566 | bellard | extern int loglevel; |
73 | 7d13299d | bellard | |
74 | 04369ff2 | bellard | #ifndef reg_EAX
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75 | 7d13299d | bellard | #define EAX (env->regs[R_EAX])
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76 | 04369ff2 | bellard | #endif
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77 | 04369ff2 | bellard | #ifndef reg_ECX
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78 | 7d13299d | bellard | #define ECX (env->regs[R_ECX])
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79 | 04369ff2 | bellard | #endif
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80 | 04369ff2 | bellard | #ifndef reg_EDX
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81 | 7d13299d | bellard | #define EDX (env->regs[R_EDX])
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82 | 04369ff2 | bellard | #endif
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83 | 04369ff2 | bellard | #ifndef reg_EBX
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84 | 7d13299d | bellard | #define EBX (env->regs[R_EBX])
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85 | 04369ff2 | bellard | #endif
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86 | 04369ff2 | bellard | #ifndef reg_ESP
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87 | 7d13299d | bellard | #define ESP (env->regs[R_ESP])
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88 | 04369ff2 | bellard | #endif
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89 | 04369ff2 | bellard | #ifndef reg_EBP
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90 | 7d13299d | bellard | #define EBP (env->regs[R_EBP])
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91 | 04369ff2 | bellard | #endif
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92 | 04369ff2 | bellard | #ifndef reg_ESI
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93 | 7d13299d | bellard | #define ESI (env->regs[R_ESI])
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94 | 04369ff2 | bellard | #endif
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95 | 04369ff2 | bellard | #ifndef reg_EDI
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96 | 7d13299d | bellard | #define EDI (env->regs[R_EDI])
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97 | 04369ff2 | bellard | #endif
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98 | dab2ed99 | bellard | #define EIP (env->eip)
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99 | 7d13299d | bellard | #define DF (env->df)
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100 | 7d13299d | bellard | |
101 | 7d13299d | bellard | #define CC_SRC (env->cc_src)
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102 | 7d13299d | bellard | #define CC_DST (env->cc_dst)
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103 | 7d13299d | bellard | #define CC_OP (env->cc_op)
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104 | 7d13299d | bellard | |
105 | 7d13299d | bellard | /* float macros */
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106 | 7d13299d | bellard | #define FT0 (env->ft0)
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107 | 7d13299d | bellard | #define ST0 (env->fpregs[env->fpstt])
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108 | 7d13299d | bellard | #define ST(n) (env->fpregs[(env->fpstt + (n)) & 7]) |
109 | 7d13299d | bellard | #define ST1 ST(1) |
110 | 7d13299d | bellard | |
111 | d014c98c | bellard | #ifdef USE_FP_CONVERT
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112 | d014c98c | bellard | #define FP_CONVERT (env->fp_convert)
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113 | d014c98c | bellard | #endif
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114 | d014c98c | bellard | |
115 | 7d13299d | bellard | #include "cpu-i386.h" |
116 | d4e8164f | bellard | #include "exec.h" |
117 | 7d13299d | bellard | |
118 | 7d13299d | bellard | typedef struct CCTable { |
119 | 7d13299d | bellard | int (*compute_all)(void); /* return all the flags */ |
120 | 7d13299d | bellard | int (*compute_c)(void); /* return the C flag */ |
121 | 7d13299d | bellard | } CCTable; |
122 | 7d13299d | bellard | |
123 | 7d13299d | bellard | extern CCTable cc_table[];
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124 | 6dbad63e | bellard | |
125 | a513fe19 | bellard | void load_seg(int seg_reg, int selector, unsigned cur_eip); |
126 | d8bc1fd0 | bellard | void jmp_seg(int selector, unsigned int new_eip); |
127 | 90a9fdae | bellard | void helper_iret_protected(int shift); |
128 | d8bc1fd0 | bellard | void helper_lldt_T0(void); |
129 | d8bc1fd0 | bellard | void helper_ltr_T0(void); |
130 | d8bc1fd0 | bellard | void helper_movl_crN_T0(int reg); |
131 | d8bc1fd0 | bellard | void helper_movl_drN_T0(int reg); |
132 | 90a9fdae | bellard | void helper_invlpg(unsigned int addr); |
133 | 90a9fdae | bellard | void cpu_x86_update_cr0(CPUX86State *env);
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134 | 90a9fdae | bellard | void cpu_x86_update_cr3(CPUX86State *env);
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135 | 90a9fdae | bellard | void cpu_x86_flush_tlb(CPUX86State *env, uint32_t addr);
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136 | 90a9fdae | bellard | int cpu_x86_handle_mmu_fault(CPUX86State *env, uint32_t addr, int is_write); |
137 | 3ec9c4fc | bellard | void __hidden cpu_lock(void); |
138 | 3ec9c4fc | bellard | void __hidden cpu_unlock(void); |
139 | 90a9fdae | bellard | void do_interrupt(int intno, int is_int, int error_code, |
140 | 90a9fdae | bellard | unsigned int next_eip); |
141 | 90a9fdae | bellard | void do_interrupt_user(int intno, int is_int, int error_code, |
142 | 90a9fdae | bellard | unsigned int next_eip); |
143 | a513fe19 | bellard | void raise_interrupt(int intno, int is_int, int error_code, |
144 | a513fe19 | bellard | unsigned int next_eip); |
145 | 455b7619 | bellard | void raise_exception_err(int exception_index, int error_code); |
146 | 9de5e440 | bellard | void raise_exception(int exception_index); |
147 | 3ec9c4fc | bellard | void __hidden cpu_loop_exit(void); |
148 | d0a1ffc9 | bellard | void helper_fsave(uint8_t *ptr, int data32); |
149 | d0a1ffc9 | bellard | void helper_frstor(uint8_t *ptr, int data32); |
150 | 9de5e440 | bellard | |
151 | 9de5e440 | bellard | void OPPROTO op_movl_eflags_T0(void); |
152 | 9de5e440 | bellard | void OPPROTO op_movl_T0_eflags(void); |
153 | 3ec9c4fc | bellard | void raise_interrupt(int intno, int is_int, int error_code, |
154 | 3ec9c4fc | bellard | unsigned int next_eip); |
155 | 3ec9c4fc | bellard | void raise_exception_err(int exception_index, int error_code); |
156 | 3ec9c4fc | bellard | void raise_exception(int exception_index); |
157 | e163bca7 | bellard | void helper_divl_EAX_T0(uint32_t eip);
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158 | e163bca7 | bellard | void helper_idivl_EAX_T0(uint32_t eip);
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159 | e163bca7 | bellard | void helper_cmpxchg8b(void); |
160 | 3ec9c4fc | bellard | void helper_cpuid(void); |
161 | e163bca7 | bellard | void helper_rdtsc(void); |
162 | 3c1cf9fa | bellard | void helper_rdmsr(void); |
163 | 3c1cf9fa | bellard | void helper_wrmsr(void); |
164 | 3ec9c4fc | bellard | void helper_lsl(void); |
165 | 3ec9c4fc | bellard | void helper_lar(void); |
166 | 3ec9c4fc | bellard | |
167 | 3ec9c4fc | bellard | #ifdef USE_X86LDOUBLE
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168 | 3ec9c4fc | bellard | /* use long double functions */
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169 | 3ec9c4fc | bellard | #define lrint lrintl
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170 | 3ec9c4fc | bellard | #define llrint llrintl
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171 | 3ec9c4fc | bellard | #define fabs fabsl
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172 | 3ec9c4fc | bellard | #define sin sinl
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173 | 3ec9c4fc | bellard | #define cos cosl
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174 | 3ec9c4fc | bellard | #define sqrt sqrtl
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175 | 3ec9c4fc | bellard | #define pow powl
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176 | 3ec9c4fc | bellard | #define log logl
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177 | 3ec9c4fc | bellard | #define tan tanl
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178 | 3ec9c4fc | bellard | #define atan2 atan2l
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179 | 3ec9c4fc | bellard | #define floor floorl
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180 | 3ec9c4fc | bellard | #define ceil ceill
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181 | 3ec9c4fc | bellard | #define rint rintl
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182 | 3ec9c4fc | bellard | #endif
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183 | 3ec9c4fc | bellard | |
184 | 3ec9c4fc | bellard | extern int lrint(CPU86_LDouble x); |
185 | 3ec9c4fc | bellard | extern int64_t llrint(CPU86_LDouble x);
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186 | 3ec9c4fc | bellard | extern CPU86_LDouble fabs(CPU86_LDouble x);
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187 | 3ec9c4fc | bellard | extern CPU86_LDouble sin(CPU86_LDouble x);
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188 | 3ec9c4fc | bellard | extern CPU86_LDouble cos(CPU86_LDouble x);
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189 | 3ec9c4fc | bellard | extern CPU86_LDouble sqrt(CPU86_LDouble x);
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190 | 3ec9c4fc | bellard | extern CPU86_LDouble pow(CPU86_LDouble, CPU86_LDouble);
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191 | 3ec9c4fc | bellard | extern CPU86_LDouble log(CPU86_LDouble x);
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192 | 3ec9c4fc | bellard | extern CPU86_LDouble tan(CPU86_LDouble x);
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193 | 3ec9c4fc | bellard | extern CPU86_LDouble atan2(CPU86_LDouble, CPU86_LDouble);
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194 | 3ec9c4fc | bellard | extern CPU86_LDouble floor(CPU86_LDouble x);
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195 | 3ec9c4fc | bellard | extern CPU86_LDouble ceil(CPU86_LDouble x);
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196 | 3ec9c4fc | bellard | extern CPU86_LDouble rint(CPU86_LDouble x);
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197 | 3ec9c4fc | bellard | |
198 | 3ec9c4fc | bellard | #define RC_MASK 0xc00 |
199 | 3ec9c4fc | bellard | #define RC_NEAR 0x000 |
200 | 3ec9c4fc | bellard | #define RC_DOWN 0x400 |
201 | 3ec9c4fc | bellard | #define RC_UP 0x800 |
202 | 3ec9c4fc | bellard | #define RC_CHOP 0xc00 |
203 | 3ec9c4fc | bellard | |
204 | 3ec9c4fc | bellard | #define MAXTAN 9223372036854775808.0 |
205 | 3ec9c4fc | bellard | |
206 | e163bca7 | bellard | #ifdef __arm__
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207 | e163bca7 | bellard | /* we have no way to do correct rounding - a FPU emulator is needed */
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208 | e163bca7 | bellard | #define FE_DOWNWARD FE_TONEAREST
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209 | e163bca7 | bellard | #define FE_UPWARD FE_TONEAREST
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210 | e163bca7 | bellard | #define FE_TOWARDZERO FE_TONEAREST
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211 | e163bca7 | bellard | #endif
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212 | e163bca7 | bellard | |
213 | 3ec9c4fc | bellard | #ifdef USE_X86LDOUBLE
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214 | 3ec9c4fc | bellard | |
215 | 3ec9c4fc | bellard | /* only for x86 */
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216 | 3ec9c4fc | bellard | typedef union { |
217 | 3ec9c4fc | bellard | long double d; |
218 | 3ec9c4fc | bellard | struct {
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219 | 3ec9c4fc | bellard | unsigned long long lower; |
220 | 3ec9c4fc | bellard | unsigned short upper; |
221 | 3ec9c4fc | bellard | } l; |
222 | 3ec9c4fc | bellard | } CPU86_LDoubleU; |
223 | 3ec9c4fc | bellard | |
224 | 3ec9c4fc | bellard | /* the following deal with x86 long double-precision numbers */
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225 | 3ec9c4fc | bellard | #define MAXEXPD 0x7fff |
226 | 3ec9c4fc | bellard | #define EXPBIAS 16383 |
227 | 3ec9c4fc | bellard | #define EXPD(fp) (fp.l.upper & 0x7fff) |
228 | 3ec9c4fc | bellard | #define SIGND(fp) ((fp.l.upper) & 0x8000) |
229 | 3ec9c4fc | bellard | #define MANTD(fp) (fp.l.lower)
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230 | 3ec9c4fc | bellard | #define BIASEXPONENT(fp) fp.l.upper = (fp.l.upper & ~(0x7fff)) | EXPBIAS |
231 | 3ec9c4fc | bellard | |
232 | 3ec9c4fc | bellard | #else
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233 | 3ec9c4fc | bellard | |
234 | e163bca7 | bellard | /* NOTE: arm is horrible as double 32 bit words are stored in big endian ! */
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235 | 3ec9c4fc | bellard | typedef union { |
236 | 3ec9c4fc | bellard | double d;
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237 | e163bca7 | bellard | #if !defined(WORDS_BIGENDIAN) && !defined(__arm__)
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238 | 3ec9c4fc | bellard | struct {
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239 | 3ec9c4fc | bellard | uint32_t lower; |
240 | 3ec9c4fc | bellard | int32_t upper; |
241 | 3ec9c4fc | bellard | } l; |
242 | 3ec9c4fc | bellard | #else
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243 | 3ec9c4fc | bellard | struct {
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244 | 3ec9c4fc | bellard | int32_t upper; |
245 | 3ec9c4fc | bellard | uint32_t lower; |
246 | 3ec9c4fc | bellard | } l; |
247 | 3ec9c4fc | bellard | #endif
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248 | e163bca7 | bellard | #ifndef __arm__
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249 | 3ec9c4fc | bellard | int64_t ll; |
250 | e163bca7 | bellard | #endif
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251 | 3ec9c4fc | bellard | } CPU86_LDoubleU; |
252 | 3ec9c4fc | bellard | |
253 | 3ec9c4fc | bellard | /* the following deal with IEEE double-precision numbers */
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254 | 3ec9c4fc | bellard | #define MAXEXPD 0x7ff |
255 | 3ec9c4fc | bellard | #define EXPBIAS 1023 |
256 | 3ec9c4fc | bellard | #define EXPD(fp) (((fp.l.upper) >> 20) & 0x7FF) |
257 | 3ec9c4fc | bellard | #define SIGND(fp) ((fp.l.upper) & 0x80000000) |
258 | e163bca7 | bellard | #ifdef __arm__
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259 | e163bca7 | bellard | #define MANTD(fp) (fp.l.lower | ((uint64_t)(fp.l.upper & ((1 << 20) - 1)) << 32)) |
260 | e163bca7 | bellard | #else
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261 | 3ec9c4fc | bellard | #define MANTD(fp) (fp.ll & ((1LL << 52) - 1)) |
262 | e163bca7 | bellard | #endif
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263 | 3ec9c4fc | bellard | #define BIASEXPONENT(fp) fp.l.upper = (fp.l.upper & ~(0x7ff << 20)) | (EXPBIAS << 20) |
264 | 3ec9c4fc | bellard | #endif
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265 | 3ec9c4fc | bellard | |
266 | 3ec9c4fc | bellard | static inline void fpush(void) |
267 | 3ec9c4fc | bellard | { |
268 | 3ec9c4fc | bellard | env->fpstt = (env->fpstt - 1) & 7; |
269 | 3ec9c4fc | bellard | env->fptags[env->fpstt] = 0; /* validate stack entry */ |
270 | 3ec9c4fc | bellard | } |
271 | 3ec9c4fc | bellard | |
272 | 3ec9c4fc | bellard | static inline void fpop(void) |
273 | 3ec9c4fc | bellard | { |
274 | 3ec9c4fc | bellard | env->fptags[env->fpstt] = 1; /* invvalidate stack entry */ |
275 | 3ec9c4fc | bellard | env->fpstt = (env->fpstt + 1) & 7; |
276 | 3ec9c4fc | bellard | } |
277 | 3ec9c4fc | bellard | |
278 | 3ec9c4fc | bellard | #ifndef USE_X86LDOUBLE
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279 | 3ec9c4fc | bellard | static inline CPU86_LDouble helper_fldt(uint8_t *ptr) |
280 | 3ec9c4fc | bellard | { |
281 | 3ec9c4fc | bellard | CPU86_LDoubleU temp; |
282 | 3ec9c4fc | bellard | int upper, e;
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283 | e163bca7 | bellard | uint64_t ll; |
284 | e163bca7 | bellard | |
285 | 3ec9c4fc | bellard | /* mantissa */
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286 | 3ec9c4fc | bellard | upper = lduw(ptr + 8);
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287 | 3ec9c4fc | bellard | /* XXX: handle overflow ? */
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288 | 3ec9c4fc | bellard | e = (upper & 0x7fff) - 16383 + EXPBIAS; /* exponent */ |
289 | 3ec9c4fc | bellard | e |= (upper >> 4) & 0x800; /* sign */ |
290 | e163bca7 | bellard | ll = (ldq(ptr) >> 11) & ((1LL << 52) - 1); |
291 | e163bca7 | bellard | #ifdef __arm__
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292 | e163bca7 | bellard | temp.l.upper = (e << 20) | (ll >> 32); |
293 | e163bca7 | bellard | temp.l.lower = ll; |
294 | e163bca7 | bellard | #else
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295 | e163bca7 | bellard | temp.ll = ll | ((uint64_t)e << 52);
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296 | e163bca7 | bellard | #endif
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297 | 3ec9c4fc | bellard | return temp.d;
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298 | 3ec9c4fc | bellard | } |
299 | 3ec9c4fc | bellard | |
300 | 3ec9c4fc | bellard | static inline void helper_fstt(CPU86_LDouble f, uint8_t *ptr) |
301 | 3ec9c4fc | bellard | { |
302 | 3ec9c4fc | bellard | CPU86_LDoubleU temp; |
303 | 3ec9c4fc | bellard | int e;
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304 | e163bca7 | bellard | |
305 | 3ec9c4fc | bellard | temp.d = f; |
306 | 3ec9c4fc | bellard | /* mantissa */
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307 | 3ec9c4fc | bellard | stq(ptr, (MANTD(temp) << 11) | (1LL << 63)); |
308 | 3ec9c4fc | bellard | /* exponent + sign */
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309 | 3ec9c4fc | bellard | e = EXPD(temp) - EXPBIAS + 16383;
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310 | 3ec9c4fc | bellard | e |= SIGND(temp) >> 16;
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311 | 3ec9c4fc | bellard | stw(ptr + 8, e);
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312 | 3ec9c4fc | bellard | } |
313 | 3ec9c4fc | bellard | #endif
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314 | 3ec9c4fc | bellard | |
315 | e163bca7 | bellard | const CPU86_LDouble f15rk[7]; |
316 | e163bca7 | bellard | |
317 | 3ec9c4fc | bellard | void helper_fldt_ST0_A0(void); |
318 | 3ec9c4fc | bellard | void helper_fstt_ST0_A0(void); |
319 | 3ec9c4fc | bellard | void helper_fbld_ST0_A0(void); |
320 | 3ec9c4fc | bellard | void helper_fbst_ST0_A0(void); |
321 | 3ec9c4fc | bellard | void helper_f2xm1(void); |
322 | 3ec9c4fc | bellard | void helper_fyl2x(void); |
323 | 3ec9c4fc | bellard | void helper_fptan(void); |
324 | 3ec9c4fc | bellard | void helper_fpatan(void); |
325 | 3ec9c4fc | bellard | void helper_fxtract(void); |
326 | 3ec9c4fc | bellard | void helper_fprem1(void); |
327 | 3ec9c4fc | bellard | void helper_fprem(void); |
328 | 3ec9c4fc | bellard | void helper_fyl2xp1(void); |
329 | 3ec9c4fc | bellard | void helper_fsqrt(void); |
330 | 3ec9c4fc | bellard | void helper_fsincos(void); |
331 | 3ec9c4fc | bellard | void helper_frndint(void); |
332 | 3ec9c4fc | bellard | void helper_fscale(void); |
333 | 3ec9c4fc | bellard | void helper_fsin(void); |
334 | 3ec9c4fc | bellard | void helper_fcos(void); |
335 | 3ec9c4fc | bellard | void helper_fxam_ST0(void); |
336 | 3ec9c4fc | bellard | void helper_fstenv(uint8_t *ptr, int data32); |
337 | 3ec9c4fc | bellard | void helper_fldenv(uint8_t *ptr, int data32); |
338 | 3ec9c4fc | bellard | void helper_fsave(uint8_t *ptr, int data32); |
339 | 3ec9c4fc | bellard | void helper_frstor(uint8_t *ptr, int data32); |
340 | 3ec9c4fc | bellard | |
341 | 79638566 | bellard | const uint8_t parity_table[256]; |
342 | 79638566 | bellard | const uint8_t rclw_table[32]; |
343 | 79638566 | bellard | const uint8_t rclb_table[32]; |
344 | 90a9fdae | bellard | |
345 | 90a9fdae | bellard | static inline uint32_t compute_eflags(void) |
346 | 90a9fdae | bellard | { |
347 | 90a9fdae | bellard | return env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK);
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348 | 90a9fdae | bellard | } |
349 | 90a9fdae | bellard | |
350 | 90a9fdae | bellard | #define FL_UPDATE_MASK32 (TF_MASK | AC_MASK | ID_MASK)
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351 | 90a9fdae | bellard | |
352 | 90a9fdae | bellard | #define FL_UPDATE_CPL0_MASK (TF_MASK | IF_MASK | IOPL_MASK | NT_MASK | \
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353 | 90a9fdae | bellard | RF_MASK | AC_MASK | ID_MASK) |
354 | 90a9fdae | bellard | |
355 | 90a9fdae | bellard | /* NOTE: CC_OP must be modified manually to CC_OP_EFLAGS */
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356 | 90a9fdae | bellard | static inline void load_eflags(int eflags, int update_mask) |
357 | 90a9fdae | bellard | { |
358 | 90a9fdae | bellard | CC_SRC = eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); |
359 | 90a9fdae | bellard | DF = 1 - (2 * ((eflags >> 10) & 1)); |
360 | 90a9fdae | bellard | env->eflags = (env->eflags & ~update_mask) | |
361 | 90a9fdae | bellard | (eflags & update_mask); |
362 | 90a9fdae | bellard | } |