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/*
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 *  i386 micro operations
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 * 
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 *  Copyright (c) 2003 Fabrice Bellard
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 *
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 * This library is free software; you can redistribute it and/or
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 * modify it under the terms of the GNU Lesser General Public
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 * License as published by the Free Software Foundation; either
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 * version 2 of the License, or (at your option) any later version.
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 *
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 * This library is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
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 * Lesser General Public License for more details.
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 *
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 * You should have received a copy of the GNU Lesser General Public
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 * License along with this library; if not, write to the Free Software
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 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
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 */
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#include "exec-i386.h"
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/* n must be a constant to be efficient */
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static inline int lshift(int x, int n)
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{
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    if (n >= 0)
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        return x << n;
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    else
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        return x >> (-n);
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}
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/* we define the various pieces of code used by the JIT */
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#define REG EAX
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#define REGNAME _EAX
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#include "opreg_template.h"
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#undef REG
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#undef REGNAME
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#define REG ECX
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#define REGNAME _ECX
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#include "opreg_template.h"
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#undef REG
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#undef REGNAME
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#define REG EDX
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#define REGNAME _EDX
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#include "opreg_template.h"
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#undef REG
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#undef REGNAME
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#define REG EBX
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#define REGNAME _EBX
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#include "opreg_template.h"
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#undef REG
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#undef REGNAME
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#define REG ESP
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#define REGNAME _ESP
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#include "opreg_template.h"
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#undef REG
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#undef REGNAME
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#define REG EBP
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#define REGNAME _EBP
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#include "opreg_template.h"
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#undef REG
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#undef REGNAME
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#define REG ESI
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#define REGNAME _ESI
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#include "opreg_template.h"
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#undef REG
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#undef REGNAME
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#define REG EDI
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#define REGNAME _EDI
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#include "opreg_template.h"
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#undef REG
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#undef REGNAME
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/* operations with flags */
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/* update flags with T0 and T1 (add/sub case) */
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void OPPROTO op_update2_cc(void)
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{
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    CC_SRC = T1;
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    CC_DST = T0;
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}
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/* update flags with T0 (logic operation case) */
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void OPPROTO op_update1_cc(void)
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{
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    CC_DST = T0;
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}
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void OPPROTO op_update_neg_cc(void)
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{
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    CC_SRC = -T0;
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    CC_DST = T0;
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}
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void OPPROTO op_cmpl_T0_T1_cc(void)
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{
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    CC_SRC = T1;
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    CC_DST = T0 - T1;
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}
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void OPPROTO op_update_inc_cc(void)
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{
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    CC_SRC = cc_table[CC_OP].compute_c();
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    CC_DST = T0;
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}
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void OPPROTO op_testl_T0_T1_cc(void)
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{
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    CC_DST = T0 & T1;
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}
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/* operations without flags */
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void OPPROTO op_addl_T0_T1(void)
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{
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    T0 += T1;
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}
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void OPPROTO op_orl_T0_T1(void)
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{
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    T0 |= T1;
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}
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void OPPROTO op_andl_T0_T1(void)
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{
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    T0 &= T1;
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}
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void OPPROTO op_subl_T0_T1(void)
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{
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    T0 -= T1;
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}
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void OPPROTO op_xorl_T0_T1(void)
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{
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    T0 ^= T1;
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}
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void OPPROTO op_negl_T0(void)
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{
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    T0 = -T0;
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}
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void OPPROTO op_incl_T0(void)
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{
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    T0++;
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}
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void OPPROTO op_decl_T0(void)
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{
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    T0--;
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}
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void OPPROTO op_notl_T0(void)
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{
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    T0 = ~T0;
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}
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void OPPROTO op_bswapl_T0(void)
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{
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    T0 = bswap32(T0);
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}
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/* multiply/divide */
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void OPPROTO op_mulb_AL_T0(void)
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{
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    unsigned int res;
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    res = (uint8_t)EAX * (uint8_t)T0;
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    EAX = (EAX & 0xffff0000) | res;
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    CC_SRC = (res & 0xff00);
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}
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void OPPROTO op_imulb_AL_T0(void)
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{
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    int res;
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    res = (int8_t)EAX * (int8_t)T0;
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    EAX = (EAX & 0xffff0000) | (res & 0xffff);
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    CC_SRC = (res != (int8_t)res);
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}
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void OPPROTO op_mulw_AX_T0(void)
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{
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    unsigned int res;
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    res = (uint16_t)EAX * (uint16_t)T0;
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    EAX = (EAX & 0xffff0000) | (res & 0xffff);
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    EDX = (EDX & 0xffff0000) | ((res >> 16) & 0xffff);
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    CC_SRC = res >> 16;
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}
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void OPPROTO op_imulw_AX_T0(void)
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{
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    int res;
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    res = (int16_t)EAX * (int16_t)T0;
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    EAX = (EAX & 0xffff0000) | (res & 0xffff);
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    EDX = (EDX & 0xffff0000) | ((res >> 16) & 0xffff);
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    CC_SRC = (res != (int16_t)res);
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}
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void OPPROTO op_mull_EAX_T0(void)
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{
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    uint64_t res;
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    res = (uint64_t)((uint32_t)EAX) * (uint64_t)((uint32_t)T0);
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    EAX = res;
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    EDX = res >> 32;
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    CC_SRC = res >> 32;
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}
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void OPPROTO op_imull_EAX_T0(void)
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{
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    int64_t res;
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    res = (int64_t)((int32_t)EAX) * (int64_t)((int32_t)T0);
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    EAX = res;
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    EDX = res >> 32;
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    CC_SRC = (res != (int32_t)res);
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}
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void OPPROTO op_imulw_T0_T1(void)
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{
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    int res;
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    res = (int16_t)T0 * (int16_t)T1;
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    T0 = res;
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    CC_SRC = (res != (int16_t)res);
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}
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void OPPROTO op_imull_T0_T1(void)
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{
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    int64_t res;
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    res = (int64_t)((int32_t)T0) * (int64_t)((int32_t)T1);
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    T0 = res;
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    CC_SRC = (res != (int32_t)res);
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}
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/* division, flags are undefined */
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/* XXX: add exceptions for overflow */
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void OPPROTO op_divb_AL_T0(void)
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{
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    unsigned int num, den, q, r;
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    num = (EAX & 0xffff);
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    den = (T0 & 0xff);
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    if (den == 0) {
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        EIP = PARAM1;
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        raise_exception(EXCP00_DIVZ);
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    }
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    q = (num / den) & 0xff;
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    r = (num % den) & 0xff;
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    EAX = (EAX & 0xffff0000) | (r << 8) | q;
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}
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void OPPROTO op_idivb_AL_T0(void)
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{
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    int num, den, q, r;
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    num = (int16_t)EAX;
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    den = (int8_t)T0;
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    if (den == 0) {
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        EIP = PARAM1;
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        raise_exception(EXCP00_DIVZ);
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    }
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    q = (num / den) & 0xff;
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    r = (num % den) & 0xff;
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    EAX = (EAX & 0xffff0000) | (r << 8) | q;
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}
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void OPPROTO op_divw_AX_T0(void)
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{
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    unsigned int num, den, q, r;
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    num = (EAX & 0xffff) | ((EDX & 0xffff) << 16);
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    den = (T0 & 0xffff);
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    if (den == 0) {
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        EIP = PARAM1;
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        raise_exception(EXCP00_DIVZ);
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    }
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    q = (num / den) & 0xffff;
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    r = (num % den) & 0xffff;
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    EAX = (EAX & 0xffff0000) | q;
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    EDX = (EDX & 0xffff0000) | r;
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}
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void OPPROTO op_idivw_AX_T0(void)
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{
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    int num, den, q, r;
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    num = (EAX & 0xffff) | ((EDX & 0xffff) << 16);
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    den = (int16_t)T0;
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    if (den == 0) {
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        EIP = PARAM1;
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        raise_exception(EXCP00_DIVZ);
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    }
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    q = (num / den) & 0xffff;
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    r = (num % den) & 0xffff;
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    EAX = (EAX & 0xffff0000) | q;
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    EDX = (EDX & 0xffff0000) | r;
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}
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void OPPROTO op_divl_EAX_T0(void)
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{
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    helper_divl_EAX_T0(PARAM1);
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}
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void OPPROTO op_idivl_EAX_T0(void)
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{
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    helper_idivl_EAX_T0(PARAM1);
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}
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/* constant load & misc op */
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void OPPROTO op_movl_T0_im(void)
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{
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    T0 = PARAM1;
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}
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void OPPROTO op_addl_T0_im(void)
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{
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    T0 += PARAM1;
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}
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void OPPROTO op_andl_T0_ffff(void)
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{
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    T0 = T0 & 0xffff;
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}
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void OPPROTO op_andl_T0_im(void)
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{
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    T0 = T0 & PARAM1;
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}
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void OPPROTO op_movl_T0_T1(void)
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{
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    T0 = T1;
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}
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void OPPROTO op_movl_T1_im(void)
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{
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    T1 = PARAM1;
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}
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void OPPROTO op_addl_T1_im(void)
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{
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    T1 += PARAM1;
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}
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void OPPROTO op_movl_T1_A0(void)
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{
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    T1 = A0;
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}
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void OPPROTO op_movl_A0_im(void)
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{
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    A0 = PARAM1;
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}
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void OPPROTO op_addl_A0_im(void)
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{
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    A0 += PARAM1;
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}
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void OPPROTO op_addl_A0_AL(void)
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{
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    A0 += (EAX & 0xff);
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}
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void OPPROTO op_andl_A0_ffff(void)
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{
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    A0 = A0 & 0xffff;
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}
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/* memory access */
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void OPPROTO op_ldub_T0_A0(void)
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{
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    T0 = ldub((uint8_t *)A0);
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}
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void OPPROTO op_ldsb_T0_A0(void)
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{
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    T0 = ldsb((int8_t *)A0);
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}
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void OPPROTO op_lduw_T0_A0(void)
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{
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    T0 = lduw((uint8_t *)A0);
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}
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void OPPROTO op_ldsw_T0_A0(void)
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{
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    T0 = ldsw((int8_t *)A0);
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}
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void OPPROTO op_ldl_T0_A0(void)
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{
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    T0 = ldl((uint8_t *)A0);
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}
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void OPPROTO op_ldub_T1_A0(void)
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{
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    T1 = ldub((uint8_t *)A0);
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}
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void OPPROTO op_ldsb_T1_A0(void)
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{
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    T1 = ldsb((int8_t *)A0);
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}
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void OPPROTO op_lduw_T1_A0(void)
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{
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    T1 = lduw((uint8_t *)A0);
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}
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void OPPROTO op_ldsw_T1_A0(void)
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{
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    T1 = ldsw((int8_t *)A0);
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}
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void OPPROTO op_ldl_T1_A0(void)
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{
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    T1 = ldl((uint8_t *)A0);
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}
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void OPPROTO op_stb_T0_A0(void)
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{
431 7bfdb6d1 bellard
    stb((uint8_t *)A0, T0);
432 7bfdb6d1 bellard
}
433 7bfdb6d1 bellard
434 7bfdb6d1 bellard
void OPPROTO op_stw_T0_A0(void)
435 7bfdb6d1 bellard
{
436 7bfdb6d1 bellard
    stw((uint8_t *)A0, T0);
437 7bfdb6d1 bellard
}
438 7bfdb6d1 bellard
439 7bfdb6d1 bellard
void OPPROTO op_stl_T0_A0(void)
440 7bfdb6d1 bellard
{
441 7bfdb6d1 bellard
    stl((uint8_t *)A0, T0);
442 7bfdb6d1 bellard
}
443 7bfdb6d1 bellard
444 4b74fe1f bellard
/* used for bit operations */
445 4b74fe1f bellard
446 4b74fe1f bellard
void OPPROTO op_add_bitw_A0_T1(void)
447 4b74fe1f bellard
{
448 4b74fe1f bellard
    A0 += ((int32_t)T1 >> 4) << 1;
449 4b74fe1f bellard
}
450 4b74fe1f bellard
451 4b74fe1f bellard
void OPPROTO op_add_bitl_A0_T1(void)
452 4b74fe1f bellard
{
453 4b74fe1f bellard
    A0 += ((int32_t)T1 >> 5) << 2;
454 4b74fe1f bellard
}
455 7bfdb6d1 bellard
456 7bfdb6d1 bellard
/* indirect jump */
457 0ecfa993 bellard
458 7bfdb6d1 bellard
void OPPROTO op_jmp_T0(void)
459 7bfdb6d1 bellard
{
460 dab2ed99 bellard
    EIP = T0;
461 7bfdb6d1 bellard
}
462 7bfdb6d1 bellard
463 7bfdb6d1 bellard
void OPPROTO op_jmp_im(void)
464 7bfdb6d1 bellard
{
465 dab2ed99 bellard
    EIP = PARAM1;
466 7bfdb6d1 bellard
}
467 7bfdb6d1 bellard
468 90a9fdae bellard
void OPPROTO op_hlt(void)
469 90a9fdae bellard
{
470 90a9fdae bellard
    env->exception_index = EXCP_HLT;
471 90a9fdae bellard
    cpu_loop_exit();
472 90a9fdae bellard
}
473 90a9fdae bellard
474 4c3a88a2 bellard
void OPPROTO op_debug(void)
475 4c3a88a2 bellard
{
476 4c3a88a2 bellard
    env->exception_index = EXCP_DEBUG;
477 4c3a88a2 bellard
    cpu_loop_exit();
478 4c3a88a2 bellard
}
479 4c3a88a2 bellard
480 f4beb510 bellard
void OPPROTO op_raise_interrupt(void)
481 0ecfa993 bellard
{
482 504e56eb bellard
    int intno;
483 f4beb510 bellard
    unsigned int next_eip;
484 504e56eb bellard
    intno = PARAM1;
485 f4beb510 bellard
    next_eip = PARAM2;
486 f4beb510 bellard
    raise_interrupt(intno, 1, 0, next_eip);
487 0ecfa993 bellard
}
488 0ecfa993 bellard
489 564c8f99 bellard
void OPPROTO op_raise_exception(void)
490 0ecfa993 bellard
{
491 564c8f99 bellard
    int exception_index;
492 564c8f99 bellard
    exception_index = PARAM1;
493 564c8f99 bellard
    raise_exception(exception_index);
494 0ecfa993 bellard
}
495 0ecfa993 bellard
496 0ecfa993 bellard
void OPPROTO op_into(void)
497 0ecfa993 bellard
{
498 0ecfa993 bellard
    int eflags;
499 0ecfa993 bellard
    eflags = cc_table[CC_OP].compute_all();
500 0ecfa993 bellard
    if (eflags & CC_O) {
501 f4beb510 bellard
        raise_interrupt(EXCP04_INTO, 1, 0, PARAM1);
502 a4a0ffdb bellard
    }
503 504e56eb bellard
    FORCE_RET();
504 a4a0ffdb bellard
}
505 a4a0ffdb bellard
506 504e56eb bellard
void OPPROTO op_cli(void)
507 504e56eb bellard
{
508 504e56eb bellard
    env->eflags &= ~IF_MASK;
509 504e56eb bellard
}
510 504e56eb bellard
511 f631ef9b bellard
void OPPROTO op_sti(void)
512 f631ef9b bellard
{
513 504e56eb bellard
    env->eflags |= IF_MASK;
514 f631ef9b bellard
}
515 f631ef9b bellard
516 3acace13 bellard
#if 0
517 f631ef9b bellard
/* vm86plus instructions */
518 f631ef9b bellard
void OPPROTO op_cli_vm(void)
519 f631ef9b bellard
{
520 f631ef9b bellard
    env->eflags &= ~VIF_MASK;
521 f631ef9b bellard
}
522 f631ef9b bellard

523 f631ef9b bellard
void OPPROTO op_sti_vm(void)
524 f631ef9b bellard
{
525 f631ef9b bellard
    env->eflags |= VIF_MASK;
526 f631ef9b bellard
    if (env->eflags & VIP_MASK) {
527 f631ef9b bellard
        EIP = PARAM1;
528 f631ef9b bellard
        raise_exception(EXCP0D_GPF);
529 f631ef9b bellard
    }
530 f631ef9b bellard
    FORCE_RET();
531 f631ef9b bellard
}
532 3acace13 bellard
#endif
533 f631ef9b bellard
534 a4a0ffdb bellard
void OPPROTO op_boundw(void)
535 a4a0ffdb bellard
{
536 a4a0ffdb bellard
    int low, high, v;
537 a4a0ffdb bellard
    low = ldsw((uint8_t *)A0);
538 a4a0ffdb bellard
    high = ldsw((uint8_t *)A0 + 2);
539 a4a0ffdb bellard
    v = (int16_t)T0;
540 f4beb510 bellard
    if (v < low || v > high) {
541 f4beb510 bellard
        EIP = PARAM1;
542 a4a0ffdb bellard
        raise_exception(EXCP05_BOUND);
543 f4beb510 bellard
    }
544 a4a0ffdb bellard
    FORCE_RET();
545 a4a0ffdb bellard
}
546 a4a0ffdb bellard
547 a4a0ffdb bellard
void OPPROTO op_boundl(void)
548 a4a0ffdb bellard
{
549 a4a0ffdb bellard
    int low, high, v;
550 a4a0ffdb bellard
    low = ldl((uint8_t *)A0);
551 a4a0ffdb bellard
    high = ldl((uint8_t *)A0 + 4);
552 a4a0ffdb bellard
    v = T0;
553 f4beb510 bellard
    if (v < low || v > high) {
554 f4beb510 bellard
        EIP = PARAM1;
555 a4a0ffdb bellard
        raise_exception(EXCP05_BOUND);
556 f4beb510 bellard
    }
557 a4a0ffdb bellard
    FORCE_RET();
558 a4a0ffdb bellard
}
559 a4a0ffdb bellard
560 a4a0ffdb bellard
void OPPROTO op_cmpxchg8b(void)
561 a4a0ffdb bellard
{
562 87f4827e bellard
    helper_cmpxchg8b();
563 0ecfa993 bellard
}
564 0ecfa993 bellard
565 d4e8164f bellard
void OPPROTO op_jmp_tb_next(void)
566 d4e8164f bellard
{
567 d4e8164f bellard
    JUMP_TB(PARAM1, 0, PARAM2);
568 d4e8164f bellard
}
569 d4e8164f bellard
570 d4e8164f bellard
void OPPROTO op_movl_T0_0(void)
571 d4e8164f bellard
{
572 d4e8164f bellard
    T0 = 0;
573 d4e8164f bellard
}
574 d4e8164f bellard
575 9621339d bellard
void OPPROTO op_exit_tb(void)
576 9621339d bellard
{
577 9621339d bellard
    EXIT_TB();
578 9621339d bellard
}
579 9621339d bellard
580 d4e8164f bellard
/* multiple size ops */
581 7bfdb6d1 bellard
582 7bfdb6d1 bellard
#define ldul ldl
583 7bfdb6d1 bellard
584 7bfdb6d1 bellard
#define SHIFT 0
585 367e86e8 bellard
#include "ops_template.h"
586 7bfdb6d1 bellard
#undef SHIFT
587 7bfdb6d1 bellard
588 7bfdb6d1 bellard
#define SHIFT 1
589 367e86e8 bellard
#include "ops_template.h"
590 7bfdb6d1 bellard
#undef SHIFT
591 7bfdb6d1 bellard
592 7bfdb6d1 bellard
#define SHIFT 2
593 367e86e8 bellard
#include "ops_template.h"
594 7bfdb6d1 bellard
#undef SHIFT
595 7bfdb6d1 bellard
596 7bfdb6d1 bellard
/* sign extend */
597 7bfdb6d1 bellard
598 7bfdb6d1 bellard
void OPPROTO op_movsbl_T0_T0(void)
599 7bfdb6d1 bellard
{
600 7bfdb6d1 bellard
    T0 = (int8_t)T0;
601 7bfdb6d1 bellard
}
602 7bfdb6d1 bellard
603 7bfdb6d1 bellard
void OPPROTO op_movzbl_T0_T0(void)
604 7bfdb6d1 bellard
{
605 7bfdb6d1 bellard
    T0 = (uint8_t)T0;
606 7bfdb6d1 bellard
}
607 7bfdb6d1 bellard
608 7bfdb6d1 bellard
void OPPROTO op_movswl_T0_T0(void)
609 7bfdb6d1 bellard
{
610 7bfdb6d1 bellard
    T0 = (int16_t)T0;
611 7bfdb6d1 bellard
}
612 7bfdb6d1 bellard
613 7bfdb6d1 bellard
void OPPROTO op_movzwl_T0_T0(void)
614 7bfdb6d1 bellard
{
615 7bfdb6d1 bellard
    T0 = (uint16_t)T0;
616 7bfdb6d1 bellard
}
617 7bfdb6d1 bellard
618 7bfdb6d1 bellard
void OPPROTO op_movswl_EAX_AX(void)
619 7bfdb6d1 bellard
{
620 7bfdb6d1 bellard
    EAX = (int16_t)EAX;
621 7bfdb6d1 bellard
}
622 7bfdb6d1 bellard
623 7bfdb6d1 bellard
void OPPROTO op_movsbw_AX_AL(void)
624 7bfdb6d1 bellard
{
625 7bfdb6d1 bellard
    EAX = (EAX & 0xffff0000) | ((int8_t)EAX & 0xffff);
626 7bfdb6d1 bellard
}
627 7bfdb6d1 bellard
628 7bfdb6d1 bellard
void OPPROTO op_movslq_EDX_EAX(void)
629 7bfdb6d1 bellard
{
630 7bfdb6d1 bellard
    EDX = (int32_t)EAX >> 31;
631 7bfdb6d1 bellard
}
632 7bfdb6d1 bellard
633 7bfdb6d1 bellard
void OPPROTO op_movswl_DX_AX(void)
634 7bfdb6d1 bellard
{
635 7bfdb6d1 bellard
    EDX = (EDX & 0xffff0000) | (((int16_t)EAX >> 15) & 0xffff);
636 7bfdb6d1 bellard
}
637 7bfdb6d1 bellard
638 7bfdb6d1 bellard
/* push/pop */
639 7bfdb6d1 bellard
640 7bfdb6d1 bellard
void op_pushl_T0(void)
641 7bfdb6d1 bellard
{
642 7bfdb6d1 bellard
    uint32_t offset;
643 7bfdb6d1 bellard
    offset = ESP - 4;
644 7bfdb6d1 bellard
    stl((void *)offset, T0);
645 7bfdb6d1 bellard
    /* modify ESP after to handle exceptions correctly */
646 7bfdb6d1 bellard
    ESP = offset;
647 7bfdb6d1 bellard
}
648 7bfdb6d1 bellard
649 dab2ed99 bellard
void op_pushw_T0(void)
650 dab2ed99 bellard
{
651 dab2ed99 bellard
    uint32_t offset;
652 dab2ed99 bellard
    offset = ESP - 2;
653 dab2ed99 bellard
    stw((void *)offset, T0);
654 dab2ed99 bellard
    /* modify ESP after to handle exceptions correctly */
655 dab2ed99 bellard
    ESP = offset;
656 dab2ed99 bellard
}
657 dab2ed99 bellard
658 dab2ed99 bellard
void op_pushl_ss32_T0(void)
659 7bfdb6d1 bellard
{
660 7bfdb6d1 bellard
    uint32_t offset;
661 7bfdb6d1 bellard
    offset = ESP - 4;
662 d8bc1fd0 bellard
    stl(env->segs[R_SS].base + offset, T0);
663 dab2ed99 bellard
    /* modify ESP after to handle exceptions correctly */
664 dab2ed99 bellard
    ESP = offset;
665 dab2ed99 bellard
}
666 dab2ed99 bellard
667 dab2ed99 bellard
void op_pushw_ss32_T0(void)
668 dab2ed99 bellard
{
669 dab2ed99 bellard
    uint32_t offset;
670 dab2ed99 bellard
    offset = ESP - 2;
671 d8bc1fd0 bellard
    stw(env->segs[R_SS].base + offset, T0);
672 7bfdb6d1 bellard
    /* modify ESP after to handle exceptions correctly */
673 7bfdb6d1 bellard
    ESP = offset;
674 7bfdb6d1 bellard
}
675 7bfdb6d1 bellard
676 dab2ed99 bellard
void op_pushl_ss16_T0(void)
677 dab2ed99 bellard
{
678 dab2ed99 bellard
    uint32_t offset;
679 dab2ed99 bellard
    offset = (ESP - 4) & 0xffff;
680 d8bc1fd0 bellard
    stl(env->segs[R_SS].base + offset, T0);
681 dab2ed99 bellard
    /* modify ESP after to handle exceptions correctly */
682 dab2ed99 bellard
    ESP = (ESP & ~0xffff) | offset;
683 dab2ed99 bellard
}
684 dab2ed99 bellard
685 dab2ed99 bellard
void op_pushw_ss16_T0(void)
686 dab2ed99 bellard
{
687 dab2ed99 bellard
    uint32_t offset;
688 dab2ed99 bellard
    offset = (ESP - 2) & 0xffff;
689 d8bc1fd0 bellard
    stw(env->segs[R_SS].base + offset, T0);
690 dab2ed99 bellard
    /* modify ESP after to handle exceptions correctly */
691 dab2ed99 bellard
    ESP = (ESP & ~0xffff) | offset;
692 dab2ed99 bellard
}
693 dab2ed99 bellard
694 dab2ed99 bellard
/* NOTE: ESP update is done after */
695 7bfdb6d1 bellard
void op_popl_T0(void)
696 7bfdb6d1 bellard
{
697 7bfdb6d1 bellard
    T0 = ldl((void *)ESP);
698 dab2ed99 bellard
}
699 dab2ed99 bellard
700 dab2ed99 bellard
void op_popw_T0(void)
701 dab2ed99 bellard
{
702 dab2ed99 bellard
    T0 = lduw((void *)ESP);
703 dab2ed99 bellard
}
704 dab2ed99 bellard
705 dab2ed99 bellard
void op_popl_ss32_T0(void)
706 dab2ed99 bellard
{
707 d8bc1fd0 bellard
    T0 = ldl(env->segs[R_SS].base + ESP);
708 dab2ed99 bellard
}
709 dab2ed99 bellard
710 dab2ed99 bellard
void op_popw_ss32_T0(void)
711 dab2ed99 bellard
{
712 d8bc1fd0 bellard
    T0 = lduw(env->segs[R_SS].base + ESP);
713 dab2ed99 bellard
}
714 dab2ed99 bellard
715 dab2ed99 bellard
void op_popl_ss16_T0(void)
716 dab2ed99 bellard
{
717 d8bc1fd0 bellard
    T0 = ldl(env->segs[R_SS].base + (ESP & 0xffff));
718 dab2ed99 bellard
}
719 dab2ed99 bellard
720 dab2ed99 bellard
void op_popw_ss16_T0(void)
721 dab2ed99 bellard
{
722 d8bc1fd0 bellard
    T0 = lduw(env->segs[R_SS].base + (ESP & 0xffff));
723 dab2ed99 bellard
}
724 dab2ed99 bellard
725 dab2ed99 bellard
void op_addl_ESP_4(void)
726 dab2ed99 bellard
{
727 7bfdb6d1 bellard
    ESP += 4;
728 7bfdb6d1 bellard
}
729 7bfdb6d1 bellard
730 dab2ed99 bellard
void op_addl_ESP_2(void)
731 dab2ed99 bellard
{
732 dab2ed99 bellard
    ESP += 2;
733 dab2ed99 bellard
}
734 dab2ed99 bellard
735 dab2ed99 bellard
void op_addw_ESP_4(void)
736 dab2ed99 bellard
{
737 dab2ed99 bellard
    ESP = (ESP & ~0xffff) | ((ESP + 4) & 0xffff);
738 dab2ed99 bellard
}
739 dab2ed99 bellard
740 dab2ed99 bellard
void op_addw_ESP_2(void)
741 dab2ed99 bellard
{
742 dab2ed99 bellard
    ESP = (ESP & ~0xffff) | ((ESP + 2) & 0xffff);
743 dab2ed99 bellard
}
744 dab2ed99 bellard
745 7bfdb6d1 bellard
void op_addl_ESP_im(void)
746 7bfdb6d1 bellard
{
747 7bfdb6d1 bellard
    ESP += PARAM1;
748 7bfdb6d1 bellard
}
749 367e86e8 bellard
750 dab2ed99 bellard
void op_addw_ESP_im(void)
751 dab2ed99 bellard
{
752 dab2ed99 bellard
    ESP = (ESP & ~0xffff) | ((ESP + PARAM1) & 0xffff);
753 27362c82 bellard
}
754 27362c82 bellard
755 a4a0ffdb bellard
void OPPROTO op_rdtsc(void)
756 27362c82 bellard
{
757 87f4827e bellard
    helper_rdtsc();
758 27362c82 bellard
}
759 27362c82 bellard
760 a4a0ffdb bellard
void OPPROTO op_cpuid(void)
761 a4a0ffdb bellard
{
762 a4a0ffdb bellard
    helper_cpuid();
763 a4a0ffdb bellard
}
764 a4a0ffdb bellard
765 3c1cf9fa bellard
void OPPROTO op_rdmsr(void)
766 3c1cf9fa bellard
{
767 3c1cf9fa bellard
    helper_rdmsr();
768 3c1cf9fa bellard
}
769 3c1cf9fa bellard
770 3c1cf9fa bellard
void OPPROTO op_wrmsr(void)
771 3c1cf9fa bellard
{
772 3c1cf9fa bellard
    helper_wrmsr();
773 3c1cf9fa bellard
}
774 3c1cf9fa bellard
775 27362c82 bellard
/* bcd */
776 27362c82 bellard
777 27362c82 bellard
/* XXX: exception */
778 27362c82 bellard
void OPPROTO op_aam(void)
779 27362c82 bellard
{
780 27362c82 bellard
    int base = PARAM1;
781 27362c82 bellard
    int al, ah;
782 27362c82 bellard
    al = EAX & 0xff;
783 27362c82 bellard
    ah = al / base;
784 27362c82 bellard
    al = al % base;
785 27362c82 bellard
    EAX = (EAX & ~0xffff) | al | (ah << 8);
786 27362c82 bellard
    CC_DST = al;
787 27362c82 bellard
}
788 27362c82 bellard
789 27362c82 bellard
void OPPROTO op_aad(void)
790 27362c82 bellard
{
791 27362c82 bellard
    int base = PARAM1;
792 27362c82 bellard
    int al, ah;
793 27362c82 bellard
    al = EAX & 0xff;
794 27362c82 bellard
    ah = (EAX >> 8) & 0xff;
795 27362c82 bellard
    al = ((ah * base) + al) & 0xff;
796 27362c82 bellard
    EAX = (EAX & ~0xffff) | al;
797 27362c82 bellard
    CC_DST = al;
798 27362c82 bellard
}
799 27362c82 bellard
800 27362c82 bellard
void OPPROTO op_aaa(void)
801 27362c82 bellard
{
802 27362c82 bellard
    int icarry;
803 27362c82 bellard
    int al, ah, af;
804 27362c82 bellard
    int eflags;
805 27362c82 bellard
806 27362c82 bellard
    eflags = cc_table[CC_OP].compute_all();
807 27362c82 bellard
    af = eflags & CC_A;
808 27362c82 bellard
    al = EAX & 0xff;
809 27362c82 bellard
    ah = (EAX >> 8) & 0xff;
810 27362c82 bellard
811 27362c82 bellard
    icarry = (al > 0xf9);
812 27362c82 bellard
    if (((al & 0x0f) > 9 ) || af) {
813 27362c82 bellard
        al = (al + 6) & 0x0f;
814 27362c82 bellard
        ah = (ah + 1 + icarry) & 0xff;
815 27362c82 bellard
        eflags |= CC_C | CC_A;
816 27362c82 bellard
    } else {
817 27362c82 bellard
        eflags &= ~(CC_C | CC_A);
818 27362c82 bellard
        al &= 0x0f;
819 27362c82 bellard
    }
820 27362c82 bellard
    EAX = (EAX & ~0xffff) | al | (ah << 8);
821 27362c82 bellard
    CC_SRC = eflags;
822 27362c82 bellard
}
823 27362c82 bellard
824 27362c82 bellard
void OPPROTO op_aas(void)
825 27362c82 bellard
{
826 27362c82 bellard
    int icarry;
827 27362c82 bellard
    int al, ah, af;
828 27362c82 bellard
    int eflags;
829 27362c82 bellard
830 27362c82 bellard
    eflags = cc_table[CC_OP].compute_all();
831 27362c82 bellard
    af = eflags & CC_A;
832 27362c82 bellard
    al = EAX & 0xff;
833 27362c82 bellard
    ah = (EAX >> 8) & 0xff;
834 27362c82 bellard
835 27362c82 bellard
    icarry = (al < 6);
836 27362c82 bellard
    if (((al & 0x0f) > 9 ) || af) {
837 27362c82 bellard
        al = (al - 6) & 0x0f;
838 27362c82 bellard
        ah = (ah - 1 - icarry) & 0xff;
839 27362c82 bellard
        eflags |= CC_C | CC_A;
840 27362c82 bellard
    } else {
841 27362c82 bellard
        eflags &= ~(CC_C | CC_A);
842 27362c82 bellard
        al &= 0x0f;
843 27362c82 bellard
    }
844 27362c82 bellard
    EAX = (EAX & ~0xffff) | al | (ah << 8);
845 27362c82 bellard
    CC_SRC = eflags;
846 27362c82 bellard
}
847 27362c82 bellard
848 27362c82 bellard
void OPPROTO op_daa(void)
849 27362c82 bellard
{
850 27362c82 bellard
    int al, af, cf;
851 27362c82 bellard
    int eflags;
852 27362c82 bellard
853 27362c82 bellard
    eflags = cc_table[CC_OP].compute_all();
854 27362c82 bellard
    cf = eflags & CC_C;
855 27362c82 bellard
    af = eflags & CC_A;
856 27362c82 bellard
    al = EAX & 0xff;
857 27362c82 bellard
858 27362c82 bellard
    eflags = 0;
859 27362c82 bellard
    if (((al & 0x0f) > 9 ) || af) {
860 27362c82 bellard
        al = (al + 6) & 0xff;
861 27362c82 bellard
        eflags |= CC_A;
862 27362c82 bellard
    }
863 27362c82 bellard
    if ((al > 0x9f) || cf) {
864 27362c82 bellard
        al = (al + 0x60) & 0xff;
865 27362c82 bellard
        eflags |= CC_C;
866 27362c82 bellard
    }
867 27362c82 bellard
    EAX = (EAX & ~0xff) | al;
868 27362c82 bellard
    /* well, speed is not an issue here, so we compute the flags by hand */
869 27362c82 bellard
    eflags |= (al == 0) << 6; /* zf */
870 27362c82 bellard
    eflags |= parity_table[al]; /* pf */
871 27362c82 bellard
    eflags |= (al & 0x80); /* sf */
872 27362c82 bellard
    CC_SRC = eflags;
873 27362c82 bellard
}
874 27362c82 bellard
875 27362c82 bellard
void OPPROTO op_das(void)
876 27362c82 bellard
{
877 27362c82 bellard
    int al, al1, af, cf;
878 27362c82 bellard
    int eflags;
879 27362c82 bellard
880 27362c82 bellard
    eflags = cc_table[CC_OP].compute_all();
881 27362c82 bellard
    cf = eflags & CC_C;
882 27362c82 bellard
    af = eflags & CC_A;
883 27362c82 bellard
    al = EAX & 0xff;
884 27362c82 bellard
885 27362c82 bellard
    eflags = 0;
886 27362c82 bellard
    al1 = al;
887 27362c82 bellard
    if (((al & 0x0f) > 9 ) || af) {
888 27362c82 bellard
        eflags |= CC_A;
889 27362c82 bellard
        if (al < 6 || cf)
890 27362c82 bellard
            eflags |= CC_C;
891 27362c82 bellard
        al = (al - 6) & 0xff;
892 27362c82 bellard
    }
893 27362c82 bellard
    if ((al1 > 0x99) || cf) {
894 27362c82 bellard
        al = (al - 0x60) & 0xff;
895 27362c82 bellard
        eflags |= CC_C;
896 27362c82 bellard
    }
897 27362c82 bellard
    EAX = (EAX & ~0xff) | al;
898 27362c82 bellard
    /* well, speed is not an issue here, so we compute the flags by hand */
899 27362c82 bellard
    eflags |= (al == 0) << 6; /* zf */
900 27362c82 bellard
    eflags |= parity_table[al]; /* pf */
901 27362c82 bellard
    eflags |= (al & 0x80); /* sf */
902 27362c82 bellard
    CC_SRC = eflags;
903 27362c82 bellard
}
904 27362c82 bellard
905 6dbad63e bellard
/* segment handling */
906 6dbad63e bellard
907 6dbad63e bellard
void OPPROTO op_movl_seg_T0(void)
908 6dbad63e bellard
{
909 f4beb510 bellard
    load_seg(PARAM1, T0 & 0xffff, PARAM2);
910 f4beb510 bellard
}
911 f4beb510 bellard
912 f4beb510 bellard
/* faster VM86 version */
913 f4beb510 bellard
void OPPROTO op_movl_seg_T0_vm(void)
914 f4beb510 bellard
{
915 f4beb510 bellard
    int selector;
916 d8bc1fd0 bellard
    SegmentCache *sc;
917 f4beb510 bellard
    
918 f4beb510 bellard
    selector = T0 & 0xffff;
919 f4beb510 bellard
    /* env->segs[] access */
920 d8bc1fd0 bellard
    sc = (SegmentCache *)((char *)env + PARAM1);
921 d8bc1fd0 bellard
    sc->selector = selector;
922 d8bc1fd0 bellard
    sc->base = (void *)(selector << 4);
923 6dbad63e bellard
}
924 6dbad63e bellard
925 6dbad63e bellard
void OPPROTO op_movl_T0_seg(void)
926 6dbad63e bellard
{
927 d8bc1fd0 bellard
    T0 = env->segs[PARAM1].selector;
928 6dbad63e bellard
}
929 6dbad63e bellard
930 a4a0ffdb bellard
void OPPROTO op_movl_A0_seg(void)
931 a4a0ffdb bellard
{
932 a4a0ffdb bellard
    A0 = *(unsigned long *)((char *)env + PARAM1);
933 a4a0ffdb bellard
}
934 a4a0ffdb bellard
935 6dbad63e bellard
void OPPROTO op_addl_A0_seg(void)
936 6dbad63e bellard
{
937 6dbad63e bellard
    A0 += *(unsigned long *)((char *)env + PARAM1);
938 6dbad63e bellard
}
939 6dbad63e bellard
940 2792c4f2 bellard
void OPPROTO op_lsl(void)
941 2792c4f2 bellard
{
942 2792c4f2 bellard
    helper_lsl();
943 2792c4f2 bellard
}
944 2792c4f2 bellard
945 2792c4f2 bellard
void OPPROTO op_lar(void)
946 2792c4f2 bellard
{
947 2792c4f2 bellard
    helper_lar();
948 2792c4f2 bellard
}
949 2792c4f2 bellard
950 d8bc1fd0 bellard
/* T0: segment, T1:eip */
951 d8bc1fd0 bellard
void OPPROTO op_ljmp_T0_T1(void)
952 d8bc1fd0 bellard
{
953 d8bc1fd0 bellard
    jmp_seg(T0 & 0xffff, T1);
954 d8bc1fd0 bellard
}
955 d8bc1fd0 bellard
956 8f186479 bellard
void OPPROTO op_iret_real(void)
957 8f186479 bellard
{
958 8f186479 bellard
    helper_iret_real(PARAM1);
959 8f186479 bellard
}
960 8f186479 bellard
961 90a9fdae bellard
void OPPROTO op_iret_protected(void)
962 90a9fdae bellard
{
963 90a9fdae bellard
    helper_iret_protected(PARAM1);
964 90a9fdae bellard
}
965 90a9fdae bellard
966 d8bc1fd0 bellard
void OPPROTO op_lldt_T0(void)
967 d8bc1fd0 bellard
{
968 d8bc1fd0 bellard
    helper_lldt_T0();
969 d8bc1fd0 bellard
}
970 d8bc1fd0 bellard
971 d8bc1fd0 bellard
void OPPROTO op_ltr_T0(void)
972 d8bc1fd0 bellard
{
973 d8bc1fd0 bellard
    helper_ltr_T0();
974 d8bc1fd0 bellard
}
975 d8bc1fd0 bellard
976 d8bc1fd0 bellard
/* CR registers access */
977 d8bc1fd0 bellard
void OPPROTO op_movl_crN_T0(void)
978 d8bc1fd0 bellard
{
979 d8bc1fd0 bellard
    helper_movl_crN_T0(PARAM1);
980 d8bc1fd0 bellard
}
981 d8bc1fd0 bellard
982 d8bc1fd0 bellard
/* DR registers access */
983 d8bc1fd0 bellard
void OPPROTO op_movl_drN_T0(void)
984 d8bc1fd0 bellard
{
985 d8bc1fd0 bellard
    helper_movl_drN_T0(PARAM1);
986 d8bc1fd0 bellard
}
987 d8bc1fd0 bellard
988 d8bc1fd0 bellard
void OPPROTO op_lmsw_T0(void)
989 d8bc1fd0 bellard
{
990 d8bc1fd0 bellard
    /* only 4 lower bits of CR0 are modified */
991 d8bc1fd0 bellard
    T0 = (env->cr[0] & ~0xf) | (T0 & 0xf);
992 d8bc1fd0 bellard
    helper_movl_crN_T0(0);
993 d8bc1fd0 bellard
}
994 d8bc1fd0 bellard
995 90a9fdae bellard
void OPPROTO op_invlpg_A0(void)
996 90a9fdae bellard
{
997 90a9fdae bellard
    helper_invlpg(A0);
998 90a9fdae bellard
}
999 90a9fdae bellard
1000 d8bc1fd0 bellard
void OPPROTO op_movl_T0_env(void)
1001 d8bc1fd0 bellard
{
1002 d8bc1fd0 bellard
    T0 = *(uint32_t *)((char *)env + PARAM1);
1003 d8bc1fd0 bellard
}
1004 d8bc1fd0 bellard
1005 d8bc1fd0 bellard
void OPPROTO op_movl_env_T0(void)
1006 d8bc1fd0 bellard
{
1007 d8bc1fd0 bellard
    *(uint32_t *)((char *)env + PARAM1) = T0;
1008 d8bc1fd0 bellard
}
1009 d8bc1fd0 bellard
1010 d8bc1fd0 bellard
void OPPROTO op_movl_env_T1(void)
1011 d8bc1fd0 bellard
{
1012 d8bc1fd0 bellard
    *(uint32_t *)((char *)env + PARAM1) = T1;
1013 d8bc1fd0 bellard
}
1014 d8bc1fd0 bellard
1015 d8bc1fd0 bellard
void OPPROTO op_clts(void)
1016 d8bc1fd0 bellard
{
1017 d8bc1fd0 bellard
    env->cr[0] &= ~CR0_TS_MASK;
1018 d8bc1fd0 bellard
}
1019 d8bc1fd0 bellard
1020 367e86e8 bellard
/* flags handling */
1021 367e86e8 bellard
1022 d4e8164f bellard
/* slow jumps cases : in order to avoid calling a function with a
1023 d4e8164f bellard
   pointer (which can generate a stack frame on PowerPC), we use
1024 d4e8164f bellard
   op_setcc to set T0 and then call op_jcc. */
1025 d4e8164f bellard
void OPPROTO op_jcc(void)
1026 367e86e8 bellard
{
1027 d4e8164f bellard
    if (T0)
1028 d4e8164f bellard
        JUMP_TB(PARAM1, 0, PARAM2);
1029 367e86e8 bellard
    else
1030 d4e8164f bellard
        JUMP_TB(PARAM1, 1, PARAM3);
1031 0ecfa993 bellard
    FORCE_RET();
1032 367e86e8 bellard
}
1033 367e86e8 bellard
1034 367e86e8 bellard
/* slow set cases (compute x86 flags) */
1035 367e86e8 bellard
void OPPROTO op_seto_T0_cc(void)
1036 367e86e8 bellard
{
1037 367e86e8 bellard
    int eflags;
1038 367e86e8 bellard
    eflags = cc_table[CC_OP].compute_all();
1039 367e86e8 bellard
    T0 = (eflags >> 11) & 1;
1040 367e86e8 bellard
}
1041 367e86e8 bellard
1042 367e86e8 bellard
void OPPROTO op_setb_T0_cc(void)
1043 367e86e8 bellard
{
1044 367e86e8 bellard
    T0 = cc_table[CC_OP].compute_c();
1045 367e86e8 bellard
}
1046 367e86e8 bellard
1047 367e86e8 bellard
void OPPROTO op_setz_T0_cc(void)
1048 367e86e8 bellard
{
1049 367e86e8 bellard
    int eflags;
1050 367e86e8 bellard
    eflags = cc_table[CC_OP].compute_all();
1051 367e86e8 bellard
    T0 = (eflags >> 6) & 1;
1052 367e86e8 bellard
}
1053 367e86e8 bellard
1054 367e86e8 bellard
void OPPROTO op_setbe_T0_cc(void)
1055 367e86e8 bellard
{
1056 367e86e8 bellard
    int eflags;
1057 367e86e8 bellard
    eflags = cc_table[CC_OP].compute_all();
1058 367e86e8 bellard
    T0 = (eflags & (CC_Z | CC_C)) != 0;
1059 367e86e8 bellard
}
1060 367e86e8 bellard
1061 367e86e8 bellard
void OPPROTO op_sets_T0_cc(void)
1062 367e86e8 bellard
{
1063 367e86e8 bellard
    int eflags;
1064 367e86e8 bellard
    eflags = cc_table[CC_OP].compute_all();
1065 367e86e8 bellard
    T0 = (eflags >> 7) & 1;
1066 367e86e8 bellard
}
1067 367e86e8 bellard
1068 367e86e8 bellard
void OPPROTO op_setp_T0_cc(void)
1069 367e86e8 bellard
{
1070 367e86e8 bellard
    int eflags;
1071 367e86e8 bellard
    eflags = cc_table[CC_OP].compute_all();
1072 367e86e8 bellard
    T0 = (eflags >> 2) & 1;
1073 367e86e8 bellard
}
1074 367e86e8 bellard
1075 367e86e8 bellard
void OPPROTO op_setl_T0_cc(void)
1076 367e86e8 bellard
{
1077 367e86e8 bellard
    int eflags;
1078 367e86e8 bellard
    eflags = cc_table[CC_OP].compute_all();
1079 367e86e8 bellard
    T0 = ((eflags ^ (eflags >> 4)) >> 7) & 1;
1080 367e86e8 bellard
}
1081 367e86e8 bellard
1082 367e86e8 bellard
void OPPROTO op_setle_T0_cc(void)
1083 367e86e8 bellard
{
1084 367e86e8 bellard
    int eflags;
1085 367e86e8 bellard
    eflags = cc_table[CC_OP].compute_all();
1086 367e86e8 bellard
    T0 = (((eflags ^ (eflags >> 4)) & 0x80) || (eflags & CC_Z)) != 0;
1087 367e86e8 bellard
}
1088 367e86e8 bellard
1089 367e86e8 bellard
void OPPROTO op_xor_T0_1(void)
1090 367e86e8 bellard
{
1091 367e86e8 bellard
    T0 ^= 1;
1092 367e86e8 bellard
}
1093 367e86e8 bellard
1094 367e86e8 bellard
void OPPROTO op_set_cc_op(void)
1095 367e86e8 bellard
{
1096 367e86e8 bellard
    CC_OP = PARAM1;
1097 367e86e8 bellard
}
1098 367e86e8 bellard
1099 90a9fdae bellard
#define FL_UPDATE_MASK16 (FL_UPDATE_MASK32 & 0xffff)
1100 a4a0ffdb bellard
1101 367e86e8 bellard
void OPPROTO op_movl_eflags_T0(void)
1102 367e86e8 bellard
{
1103 a4a0ffdb bellard
    int eflags;
1104 a4a0ffdb bellard
    eflags = T0;
1105 a4a0ffdb bellard
    CC_SRC = eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
1106 a4a0ffdb bellard
    DF = 1 - (2 * ((eflags >> 10) & 1));
1107 a4a0ffdb bellard
    /* we also update some system flags as in user mode */
1108 90a9fdae bellard
    env->eflags = (env->eflags & ~FL_UPDATE_MASK32) | 
1109 90a9fdae bellard
        (eflags & FL_UPDATE_MASK32);
1110 f631ef9b bellard
}
1111 f631ef9b bellard
1112 f631ef9b bellard
void OPPROTO op_movw_eflags_T0(void)
1113 f631ef9b bellard
{
1114 f631ef9b bellard
    int eflags;
1115 f631ef9b bellard
    eflags = T0;
1116 f631ef9b bellard
    CC_SRC = eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
1117 f631ef9b bellard
    DF = 1 - (2 * ((eflags >> 10) & 1));
1118 f631ef9b bellard
    /* we also update some system flags as in user mode */
1119 90a9fdae bellard
    env->eflags = (env->eflags & ~FL_UPDATE_MASK16) | 
1120 90a9fdae bellard
        (eflags & FL_UPDATE_MASK16);
1121 90a9fdae bellard
}
1122 90a9fdae bellard
1123 90a9fdae bellard
void OPPROTO op_movl_eflags_T0_cpl0(void)
1124 90a9fdae bellard
{
1125 90a9fdae bellard
    load_eflags(T0, FL_UPDATE_CPL0_MASK);
1126 90a9fdae bellard
}
1127 90a9fdae bellard
1128 90a9fdae bellard
void OPPROTO op_movw_eflags_T0_cpl0(void)
1129 90a9fdae bellard
{
1130 90a9fdae bellard
    load_eflags(T0, FL_UPDATE_CPL0_MASK & 0xffff);
1131 f631ef9b bellard
}
1132 f631ef9b bellard
1133 3acace13 bellard
#if 0
1134 3acace13 bellard
/* vm86plus version */
1135 f631ef9b bellard
void OPPROTO op_movw_eflags_T0_vm(void)
1136 f631ef9b bellard
{
1137 f631ef9b bellard
    int eflags;
1138 f631ef9b bellard
    eflags = T0;
1139 f631ef9b bellard
    CC_SRC = eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
1140 f631ef9b bellard
    DF = 1 - (2 * ((eflags >> 10) & 1));
1141 f631ef9b bellard
    /* we also update some system flags as in user mode */
1142 f631ef9b bellard
    env->eflags = (env->eflags & ~(FL_UPDATE_MASK16 | VIF_MASK)) |
1143 f631ef9b bellard
        (eflags & FL_UPDATE_MASK16);
1144 f631ef9b bellard
    if (eflags & IF_MASK) {
1145 f631ef9b bellard
        env->eflags |= VIF_MASK;
1146 f631ef9b bellard
        if (env->eflags & VIP_MASK) {
1147 f631ef9b bellard
            EIP = PARAM1;
1148 f631ef9b bellard
            raise_exception(EXCP0D_GPF);
1149 f631ef9b bellard
        }
1150 f631ef9b bellard
    }
1151 f631ef9b bellard
    FORCE_RET();
1152 f631ef9b bellard
}
1153 f631ef9b bellard

1154 f631ef9b bellard
void OPPROTO op_movl_eflags_T0_vm(void)
1155 f631ef9b bellard
{
1156 f631ef9b bellard
    int eflags;
1157 f631ef9b bellard
    eflags = T0;
1158 f631ef9b bellard
    CC_SRC = eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
1159 f631ef9b bellard
    DF = 1 - (2 * ((eflags >> 10) & 1));
1160 f631ef9b bellard
    /* we also update some system flags as in user mode */
1161 f631ef9b bellard
    env->eflags = (env->eflags & ~(FL_UPDATE_MASK32 | VIF_MASK)) |
1162 f631ef9b bellard
        (eflags & FL_UPDATE_MASK32);
1163 f631ef9b bellard
    if (eflags & IF_MASK) {
1164 f631ef9b bellard
        env->eflags |= VIF_MASK;
1165 f631ef9b bellard
        if (env->eflags & VIP_MASK) {
1166 f631ef9b bellard
            EIP = PARAM1;
1167 f631ef9b bellard
            raise_exception(EXCP0D_GPF);
1168 f631ef9b bellard
        }
1169 f631ef9b bellard
    }
1170 f631ef9b bellard
    FORCE_RET();
1171 367e86e8 bellard
}
1172 3acace13 bellard
#endif
1173 367e86e8 bellard
1174 367e86e8 bellard
/* XXX: compute only O flag */
1175 367e86e8 bellard
void OPPROTO op_movb_eflags_T0(void)
1176 367e86e8 bellard
{
1177 367e86e8 bellard
    int of;
1178 367e86e8 bellard
    of = cc_table[CC_OP].compute_all() & CC_O;
1179 a4a0ffdb bellard
    CC_SRC = (T0 & (CC_S | CC_Z | CC_A | CC_P | CC_C)) | of;
1180 367e86e8 bellard
}
1181 367e86e8 bellard
1182 367e86e8 bellard
void OPPROTO op_movl_T0_eflags(void)
1183 367e86e8 bellard
{
1184 a4a0ffdb bellard
    int eflags;
1185 a4a0ffdb bellard
    eflags = cc_table[CC_OP].compute_all();
1186 a4a0ffdb bellard
    eflags |= (DF & DF_MASK);
1187 a4a0ffdb bellard
    eflags |= env->eflags & ~(VM_MASK | RF_MASK);
1188 a4a0ffdb bellard
    T0 = eflags;
1189 367e86e8 bellard
}
1190 367e86e8 bellard
1191 3acace13 bellard
/* vm86plus version */
1192 3acace13 bellard
#if 0
1193 f631ef9b bellard
void OPPROTO op_movl_T0_eflags_vm(void)
1194 f631ef9b bellard
{
1195 f631ef9b bellard
    int eflags;
1196 f631ef9b bellard
    eflags = cc_table[CC_OP].compute_all();
1197 f631ef9b bellard
    eflags |= (DF & DF_MASK);
1198 f631ef9b bellard
    eflags |= env->eflags & ~(VM_MASK | RF_MASK | IF_MASK);
1199 f631ef9b bellard
    if (env->eflags & VIF_MASK)
1200 f631ef9b bellard
        eflags |= IF_MASK;
1201 f631ef9b bellard
    T0 = eflags;
1202 f631ef9b bellard
}
1203 3acace13 bellard
#endif
1204 f631ef9b bellard
1205 367e86e8 bellard
void OPPROTO op_cld(void)
1206 367e86e8 bellard
{
1207 367e86e8 bellard
    DF = 1;
1208 367e86e8 bellard
}
1209 367e86e8 bellard
1210 367e86e8 bellard
void OPPROTO op_std(void)
1211 367e86e8 bellard
{
1212 367e86e8 bellard
    DF = -1;
1213 367e86e8 bellard
}
1214 367e86e8 bellard
1215 367e86e8 bellard
void OPPROTO op_clc(void)
1216 367e86e8 bellard
{
1217 367e86e8 bellard
    int eflags;
1218 367e86e8 bellard
    eflags = cc_table[CC_OP].compute_all();
1219 367e86e8 bellard
    eflags &= ~CC_C;
1220 367e86e8 bellard
    CC_SRC = eflags;
1221 367e86e8 bellard
}
1222 367e86e8 bellard
1223 367e86e8 bellard
void OPPROTO op_stc(void)
1224 367e86e8 bellard
{
1225 367e86e8 bellard
    int eflags;
1226 367e86e8 bellard
    eflags = cc_table[CC_OP].compute_all();
1227 367e86e8 bellard
    eflags |= CC_C;
1228 367e86e8 bellard
    CC_SRC = eflags;
1229 367e86e8 bellard
}
1230 367e86e8 bellard
1231 367e86e8 bellard
void OPPROTO op_cmc(void)
1232 367e86e8 bellard
{
1233 367e86e8 bellard
    int eflags;
1234 367e86e8 bellard
    eflags = cc_table[CC_OP].compute_all();
1235 367e86e8 bellard
    eflags ^= CC_C;
1236 367e86e8 bellard
    CC_SRC = eflags;
1237 367e86e8 bellard
}
1238 367e86e8 bellard
1239 27362c82 bellard
void OPPROTO op_salc(void)
1240 27362c82 bellard
{
1241 27362c82 bellard
    int cf;
1242 27362c82 bellard
    cf = cc_table[CC_OP].compute_c();
1243 27362c82 bellard
    EAX = (EAX & ~0xff) | ((-cf) & 0xff);
1244 27362c82 bellard
}
1245 27362c82 bellard
1246 367e86e8 bellard
static int compute_all_eflags(void)
1247 367e86e8 bellard
{
1248 367e86e8 bellard
    return CC_SRC;
1249 367e86e8 bellard
}
1250 367e86e8 bellard
1251 367e86e8 bellard
static int compute_c_eflags(void)
1252 367e86e8 bellard
{
1253 367e86e8 bellard
    return CC_SRC & CC_C;
1254 367e86e8 bellard
}
1255 367e86e8 bellard
1256 367e86e8 bellard
static int compute_c_mul(void)
1257 367e86e8 bellard
{
1258 367e86e8 bellard
    int cf;
1259 367e86e8 bellard
    cf = (CC_SRC != 0);
1260 367e86e8 bellard
    return cf;
1261 367e86e8 bellard
}
1262 367e86e8 bellard
1263 367e86e8 bellard
static int compute_all_mul(void)
1264 367e86e8 bellard
{
1265 367e86e8 bellard
    int cf, pf, af, zf, sf, of;
1266 367e86e8 bellard
    cf = (CC_SRC != 0);
1267 367e86e8 bellard
    pf = 0; /* undefined */
1268 367e86e8 bellard
    af = 0; /* undefined */
1269 367e86e8 bellard
    zf = 0; /* undefined */
1270 367e86e8 bellard
    sf = 0; /* undefined */
1271 367e86e8 bellard
    of = cf << 11;
1272 367e86e8 bellard
    return cf | pf | af | zf | sf | of;
1273 367e86e8 bellard
}
1274 367e86e8 bellard
    
1275 367e86e8 bellard
CCTable cc_table[CC_OP_NB] = {
1276 367e86e8 bellard
    [CC_OP_DYNAMIC] = { /* should never happen */ },
1277 367e86e8 bellard
1278 367e86e8 bellard
    [CC_OP_EFLAGS] = { compute_all_eflags, compute_c_eflags },
1279 367e86e8 bellard
1280 367e86e8 bellard
    [CC_OP_MUL] = { compute_all_mul, compute_c_mul },
1281 367e86e8 bellard
1282 367e86e8 bellard
    [CC_OP_ADDB] = { compute_all_addb, compute_c_addb },
1283 367e86e8 bellard
    [CC_OP_ADDW] = { compute_all_addw, compute_c_addw  },
1284 367e86e8 bellard
    [CC_OP_ADDL] = { compute_all_addl, compute_c_addl  },
1285 367e86e8 bellard
1286 4b74fe1f bellard
    [CC_OP_ADCB] = { compute_all_adcb, compute_c_adcb },
1287 4b74fe1f bellard
    [CC_OP_ADCW] = { compute_all_adcw, compute_c_adcw  },
1288 4b74fe1f bellard
    [CC_OP_ADCL] = { compute_all_adcl, compute_c_adcl  },
1289 4b74fe1f bellard
1290 367e86e8 bellard
    [CC_OP_SUBB] = { compute_all_subb, compute_c_subb  },
1291 367e86e8 bellard
    [CC_OP_SUBW] = { compute_all_subw, compute_c_subw  },
1292 367e86e8 bellard
    [CC_OP_SUBL] = { compute_all_subl, compute_c_subl  },
1293 367e86e8 bellard
    
1294 4b74fe1f bellard
    [CC_OP_SBBB] = { compute_all_sbbb, compute_c_sbbb  },
1295 4b74fe1f bellard
    [CC_OP_SBBW] = { compute_all_sbbw, compute_c_sbbw  },
1296 4b74fe1f bellard
    [CC_OP_SBBL] = { compute_all_sbbl, compute_c_sbbl  },
1297 4b74fe1f bellard
    
1298 367e86e8 bellard
    [CC_OP_LOGICB] = { compute_all_logicb, compute_c_logicb },
1299 367e86e8 bellard
    [CC_OP_LOGICW] = { compute_all_logicw, compute_c_logicw },
1300 367e86e8 bellard
    [CC_OP_LOGICL] = { compute_all_logicl, compute_c_logicl },
1301 367e86e8 bellard
    
1302 4b74fe1f bellard
    [CC_OP_INCB] = { compute_all_incb, compute_c_incl },
1303 4b74fe1f bellard
    [CC_OP_INCW] = { compute_all_incw, compute_c_incl },
1304 367e86e8 bellard
    [CC_OP_INCL] = { compute_all_incl, compute_c_incl },
1305 367e86e8 bellard
    
1306 4b74fe1f bellard
    [CC_OP_DECB] = { compute_all_decb, compute_c_incl },
1307 4b74fe1f bellard
    [CC_OP_DECW] = { compute_all_decw, compute_c_incl },
1308 367e86e8 bellard
    [CC_OP_DECL] = { compute_all_decl, compute_c_incl },
1309 367e86e8 bellard
    
1310 2792c4f2 bellard
    [CC_OP_SHLB] = { compute_all_shlb, compute_c_shlb },
1311 2792c4f2 bellard
    [CC_OP_SHLW] = { compute_all_shlw, compute_c_shlw },
1312 367e86e8 bellard
    [CC_OP_SHLL] = { compute_all_shll, compute_c_shll },
1313 4b74fe1f bellard
1314 2792c4f2 bellard
    [CC_OP_SARB] = { compute_all_sarb, compute_c_sarl },
1315 2792c4f2 bellard
    [CC_OP_SARW] = { compute_all_sarw, compute_c_sarl },
1316 2792c4f2 bellard
    [CC_OP_SARL] = { compute_all_sarl, compute_c_sarl },
1317 367e86e8 bellard
};
1318 927f621e bellard
1319 f631ef9b bellard
/* floating point support. Some of the code for complicated x87
1320 f631ef9b bellard
   functions comes from the LGPL'ed x86 emulator found in the Willows
1321 f631ef9b bellard
   TWIN windows emulator. */
1322 927f621e bellard
1323 51fe6890 bellard
#if defined(__powerpc__)
1324 51fe6890 bellard
extern CPU86_LDouble copysign(CPU86_LDouble, CPU86_LDouble);
1325 51fe6890 bellard
1326 51fe6890 bellard
/* correct (but slow) PowerPC rint() (glibc version is incorrect) */
1327 51fe6890 bellard
double qemu_rint(double x)
1328 51fe6890 bellard
{
1329 51fe6890 bellard
    double y = 4503599627370496.0;
1330 51fe6890 bellard
    if (fabs(x) >= y)
1331 51fe6890 bellard
        return x;
1332 51fe6890 bellard
    if (x < 0) 
1333 51fe6890 bellard
        y = -y;
1334 51fe6890 bellard
    y = (x + y) - y;
1335 51fe6890 bellard
    if (y == 0.0)
1336 51fe6890 bellard
        y = copysign(y, x);
1337 51fe6890 bellard
    return y;
1338 51fe6890 bellard
}
1339 51fe6890 bellard
1340 51fe6890 bellard
#define rint qemu_rint
1341 51fe6890 bellard
#endif
1342 51fe6890 bellard
1343 927f621e bellard
/* fp load FT0 */
1344 927f621e bellard
1345 927f621e bellard
void OPPROTO op_flds_FT0_A0(void)
1346 927f621e bellard
{
1347 d014c98c bellard
#ifdef USE_FP_CONVERT
1348 d014c98c bellard
    FP_CONVERT.i32 = ldl((void *)A0);
1349 d014c98c bellard
    FT0 = FP_CONVERT.f;
1350 d014c98c bellard
#else
1351 927f621e bellard
    FT0 = ldfl((void *)A0);
1352 d014c98c bellard
#endif
1353 927f621e bellard
}
1354 927f621e bellard
1355 927f621e bellard
void OPPROTO op_fldl_FT0_A0(void)
1356 927f621e bellard
{
1357 d014c98c bellard
#ifdef USE_FP_CONVERT
1358 d014c98c bellard
    FP_CONVERT.i64 = ldq((void *)A0);
1359 d014c98c bellard
    FT0 = FP_CONVERT.d;
1360 d014c98c bellard
#else
1361 927f621e bellard
    FT0 = ldfq((void *)A0);
1362 d014c98c bellard
#endif
1363 927f621e bellard
}
1364 927f621e bellard
1365 04369ff2 bellard
/* helpers are needed to avoid static constant reference. XXX: find a better way */
1366 04369ff2 bellard
#ifdef USE_INT_TO_FLOAT_HELPERS
1367 04369ff2 bellard
1368 04369ff2 bellard
void helper_fild_FT0_A0(void)
1369 04369ff2 bellard
{
1370 04369ff2 bellard
    FT0 = (CPU86_LDouble)ldsw((void *)A0);
1371 04369ff2 bellard
}
1372 04369ff2 bellard
1373 04369ff2 bellard
void helper_fildl_FT0_A0(void)
1374 04369ff2 bellard
{
1375 04369ff2 bellard
    FT0 = (CPU86_LDouble)((int32_t)ldl((void *)A0));
1376 04369ff2 bellard
}
1377 04369ff2 bellard
1378 04369ff2 bellard
void helper_fildll_FT0_A0(void)
1379 04369ff2 bellard
{
1380 04369ff2 bellard
    FT0 = (CPU86_LDouble)((int64_t)ldq((void *)A0));
1381 04369ff2 bellard
}
1382 04369ff2 bellard
1383 04369ff2 bellard
void OPPROTO op_fild_FT0_A0(void)
1384 04369ff2 bellard
{
1385 04369ff2 bellard
    helper_fild_FT0_A0();
1386 04369ff2 bellard
}
1387 04369ff2 bellard
1388 04369ff2 bellard
void OPPROTO op_fildl_FT0_A0(void)
1389 04369ff2 bellard
{
1390 04369ff2 bellard
    helper_fildl_FT0_A0();
1391 04369ff2 bellard
}
1392 04369ff2 bellard
1393 04369ff2 bellard
void OPPROTO op_fildll_FT0_A0(void)
1394 04369ff2 bellard
{
1395 04369ff2 bellard
    helper_fildll_FT0_A0();
1396 04369ff2 bellard
}
1397 04369ff2 bellard
1398 04369ff2 bellard
#else
1399 04369ff2 bellard
1400 927f621e bellard
void OPPROTO op_fild_FT0_A0(void)
1401 927f621e bellard
{
1402 d014c98c bellard
#ifdef USE_FP_CONVERT
1403 d014c98c bellard
    FP_CONVERT.i32 = ldsw((void *)A0);
1404 d014c98c bellard
    FT0 = (CPU86_LDouble)FP_CONVERT.i32;
1405 d014c98c bellard
#else
1406 927f621e bellard
    FT0 = (CPU86_LDouble)ldsw((void *)A0);
1407 d014c98c bellard
#endif
1408 927f621e bellard
}
1409 927f621e bellard
1410 927f621e bellard
void OPPROTO op_fildl_FT0_A0(void)
1411 927f621e bellard
{
1412 d014c98c bellard
#ifdef USE_FP_CONVERT
1413 d014c98c bellard
    FP_CONVERT.i32 = (int32_t) ldl((void *)A0);
1414 d014c98c bellard
    FT0 = (CPU86_LDouble)FP_CONVERT.i32;
1415 d014c98c bellard
#else
1416 927f621e bellard
    FT0 = (CPU86_LDouble)((int32_t)ldl((void *)A0));
1417 d014c98c bellard
#endif
1418 927f621e bellard
}
1419 927f621e bellard
1420 927f621e bellard
void OPPROTO op_fildll_FT0_A0(void)
1421 927f621e bellard
{
1422 d014c98c bellard
#ifdef USE_FP_CONVERT
1423 d014c98c bellard
    FP_CONVERT.i64 = (int64_t) ldq((void *)A0);
1424 d014c98c bellard
    FT0 = (CPU86_LDouble)FP_CONVERT.i64;
1425 d014c98c bellard
#else
1426 927f621e bellard
    FT0 = (CPU86_LDouble)((int64_t)ldq((void *)A0));
1427 d014c98c bellard
#endif
1428 927f621e bellard
}
1429 04369ff2 bellard
#endif
1430 927f621e bellard
1431 927f621e bellard
/* fp load ST0 */
1432 927f621e bellard
1433 927f621e bellard
void OPPROTO op_flds_ST0_A0(void)
1434 927f621e bellard
{
1435 c39d5b78 bellard
    int new_fpstt;
1436 c39d5b78 bellard
    new_fpstt = (env->fpstt - 1) & 7;
1437 d014c98c bellard
#ifdef USE_FP_CONVERT
1438 d014c98c bellard
    FP_CONVERT.i32 = ldl((void *)A0);
1439 c39d5b78 bellard
    env->fpregs[new_fpstt] = FP_CONVERT.f;
1440 d014c98c bellard
#else
1441 c39d5b78 bellard
    env->fpregs[new_fpstt] = ldfl((void *)A0);
1442 d014c98c bellard
#endif
1443 c39d5b78 bellard
    env->fpstt = new_fpstt;
1444 c39d5b78 bellard
    env->fptags[new_fpstt] = 0; /* validate stack entry */
1445 927f621e bellard
}
1446 927f621e bellard
1447 927f621e bellard
void OPPROTO op_fldl_ST0_A0(void)
1448 927f621e bellard
{
1449 c39d5b78 bellard
    int new_fpstt;
1450 c39d5b78 bellard
    new_fpstt = (env->fpstt - 1) & 7;
1451 d014c98c bellard
#ifdef USE_FP_CONVERT
1452 d014c98c bellard
    FP_CONVERT.i64 = ldq((void *)A0);
1453 c39d5b78 bellard
    env->fpregs[new_fpstt] = FP_CONVERT.d;
1454 d014c98c bellard
#else
1455 c39d5b78 bellard
    env->fpregs[new_fpstt] = ldfq((void *)A0);
1456 d014c98c bellard
#endif
1457 c39d5b78 bellard
    env->fpstt = new_fpstt;
1458 c39d5b78 bellard
    env->fptags[new_fpstt] = 0; /* validate stack entry */
1459 927f621e bellard
}
1460 927f621e bellard
1461 77f8dd5a bellard
#ifdef USE_X86LDOUBLE
1462 77f8dd5a bellard
void OPPROTO op_fldt_ST0_A0(void)
1463 77f8dd5a bellard
{
1464 c39d5b78 bellard
    int new_fpstt;
1465 c39d5b78 bellard
    new_fpstt = (env->fpstt - 1) & 7;
1466 c39d5b78 bellard
    env->fpregs[new_fpstt] = *(long double *)A0;
1467 c39d5b78 bellard
    env->fpstt = new_fpstt;
1468 c39d5b78 bellard
    env->fptags[new_fpstt] = 0; /* validate stack entry */
1469 77f8dd5a bellard
}
1470 77f8dd5a bellard
#else
1471 77f8dd5a bellard
void OPPROTO op_fldt_ST0_A0(void)
1472 77f8dd5a bellard
{
1473 77f8dd5a bellard
    helper_fldt_ST0_A0();
1474 77f8dd5a bellard
}
1475 77f8dd5a bellard
#endif
1476 77f8dd5a bellard
1477 04369ff2 bellard
/* helpers are needed to avoid static constant reference. XXX: find a better way */
1478 04369ff2 bellard
#ifdef USE_INT_TO_FLOAT_HELPERS
1479 04369ff2 bellard
1480 04369ff2 bellard
void helper_fild_ST0_A0(void)
1481 04369ff2 bellard
{
1482 c39d5b78 bellard
    int new_fpstt;
1483 c39d5b78 bellard
    new_fpstt = (env->fpstt - 1) & 7;
1484 c39d5b78 bellard
    env->fpregs[new_fpstt] = (CPU86_LDouble)ldsw((void *)A0);
1485 c39d5b78 bellard
    env->fpstt = new_fpstt;
1486 c39d5b78 bellard
    env->fptags[new_fpstt] = 0; /* validate stack entry */
1487 04369ff2 bellard
}
1488 04369ff2 bellard
1489 04369ff2 bellard
void helper_fildl_ST0_A0(void)
1490 04369ff2 bellard
{
1491 c39d5b78 bellard
    int new_fpstt;
1492 c39d5b78 bellard
    new_fpstt = (env->fpstt - 1) & 7;
1493 c39d5b78 bellard
    env->fpregs[new_fpstt] = (CPU86_LDouble)((int32_t)ldl((void *)A0));
1494 c39d5b78 bellard
    env->fpstt = new_fpstt;
1495 c39d5b78 bellard
    env->fptags[new_fpstt] = 0; /* validate stack entry */
1496 04369ff2 bellard
}
1497 04369ff2 bellard
1498 04369ff2 bellard
void helper_fildll_ST0_A0(void)
1499 04369ff2 bellard
{
1500 c39d5b78 bellard
    int new_fpstt;
1501 c39d5b78 bellard
    new_fpstt = (env->fpstt - 1) & 7;
1502 c39d5b78 bellard
    env->fpregs[new_fpstt] = (CPU86_LDouble)((int64_t)ldq((void *)A0));
1503 c39d5b78 bellard
    env->fpstt = new_fpstt;
1504 c39d5b78 bellard
    env->fptags[new_fpstt] = 0; /* validate stack entry */
1505 04369ff2 bellard
}
1506 04369ff2 bellard
1507 04369ff2 bellard
void OPPROTO op_fild_ST0_A0(void)
1508 04369ff2 bellard
{
1509 04369ff2 bellard
    helper_fild_ST0_A0();
1510 04369ff2 bellard
}
1511 04369ff2 bellard
1512 04369ff2 bellard
void OPPROTO op_fildl_ST0_A0(void)
1513 04369ff2 bellard
{
1514 04369ff2 bellard
    helper_fildl_ST0_A0();
1515 04369ff2 bellard
}
1516 04369ff2 bellard
1517 04369ff2 bellard
void OPPROTO op_fildll_ST0_A0(void)
1518 04369ff2 bellard
{
1519 04369ff2 bellard
    helper_fildll_ST0_A0();
1520 04369ff2 bellard
}
1521 04369ff2 bellard
1522 04369ff2 bellard
#else
1523 04369ff2 bellard
1524 927f621e bellard
void OPPROTO op_fild_ST0_A0(void)
1525 927f621e bellard
{
1526 c39d5b78 bellard
    int new_fpstt;
1527 c39d5b78 bellard
    new_fpstt = (env->fpstt - 1) & 7;
1528 d014c98c bellard
#ifdef USE_FP_CONVERT
1529 d014c98c bellard
    FP_CONVERT.i32 = ldsw((void *)A0);
1530 c39d5b78 bellard
    env->fpregs[new_fpstt] = (CPU86_LDouble)FP_CONVERT.i32;
1531 d014c98c bellard
#else
1532 c39d5b78 bellard
    env->fpregs[new_fpstt] = (CPU86_LDouble)ldsw((void *)A0);
1533 d014c98c bellard
#endif
1534 c39d5b78 bellard
    env->fpstt = new_fpstt;
1535 c39d5b78 bellard
    env->fptags[new_fpstt] = 0; /* validate stack entry */
1536 927f621e bellard
}
1537 927f621e bellard
1538 927f621e bellard
void OPPROTO op_fildl_ST0_A0(void)
1539 927f621e bellard
{
1540 c39d5b78 bellard
    int new_fpstt;
1541 c39d5b78 bellard
    new_fpstt = (env->fpstt - 1) & 7;
1542 d014c98c bellard
#ifdef USE_FP_CONVERT
1543 d014c98c bellard
    FP_CONVERT.i32 = (int32_t) ldl((void *)A0);
1544 c39d5b78 bellard
    env->fpregs[new_fpstt] = (CPU86_LDouble)FP_CONVERT.i32;
1545 d014c98c bellard
#else
1546 c39d5b78 bellard
    env->fpregs[new_fpstt] = (CPU86_LDouble)((int32_t)ldl((void *)A0));
1547 d014c98c bellard
#endif
1548 c39d5b78 bellard
    env->fpstt = new_fpstt;
1549 c39d5b78 bellard
    env->fptags[new_fpstt] = 0; /* validate stack entry */
1550 927f621e bellard
}
1551 927f621e bellard
1552 927f621e bellard
void OPPROTO op_fildll_ST0_A0(void)
1553 927f621e bellard
{
1554 c39d5b78 bellard
    int new_fpstt;
1555 c39d5b78 bellard
    new_fpstt = (env->fpstt - 1) & 7;
1556 d014c98c bellard
#ifdef USE_FP_CONVERT
1557 d014c98c bellard
    FP_CONVERT.i64 = (int64_t) ldq((void *)A0);
1558 c39d5b78 bellard
    env->fpregs[new_fpstt] = (CPU86_LDouble)FP_CONVERT.i64;
1559 d014c98c bellard
#else
1560 c39d5b78 bellard
    env->fpregs[new_fpstt] = (CPU86_LDouble)((int64_t)ldq((void *)A0));
1561 d014c98c bellard
#endif
1562 c39d5b78 bellard
    env->fpstt = new_fpstt;
1563 c39d5b78 bellard
    env->fptags[new_fpstt] = 0; /* validate stack entry */
1564 927f621e bellard
}
1565 927f621e bellard
1566 04369ff2 bellard
#endif
1567 04369ff2 bellard
1568 927f621e bellard
/* fp store */
1569 927f621e bellard
1570 927f621e bellard
void OPPROTO op_fsts_ST0_A0(void)
1571 927f621e bellard
{
1572 d014c98c bellard
#ifdef USE_FP_CONVERT
1573 87f4827e bellard
    FP_CONVERT.f = (float)ST0;
1574 d014c98c bellard
    stfl((void *)A0, FP_CONVERT.f);
1575 d014c98c bellard
#else
1576 927f621e bellard
    stfl((void *)A0, (float)ST0);
1577 d014c98c bellard
#endif
1578 927f621e bellard
}
1579 927f621e bellard
1580 927f621e bellard
void OPPROTO op_fstl_ST0_A0(void)
1581 927f621e bellard
{
1582 77f8dd5a bellard
    stfq((void *)A0, (double)ST0);
1583 927f621e bellard
}
1584 927f621e bellard
1585 77f8dd5a bellard
#ifdef USE_X86LDOUBLE
1586 77f8dd5a bellard
void OPPROTO op_fstt_ST0_A0(void)
1587 77f8dd5a bellard
{
1588 77f8dd5a bellard
    *(long double *)A0 = ST0;
1589 77f8dd5a bellard
}
1590 77f8dd5a bellard
#else
1591 77f8dd5a bellard
void OPPROTO op_fstt_ST0_A0(void)
1592 77f8dd5a bellard
{
1593 77f8dd5a bellard
    helper_fstt_ST0_A0();
1594 77f8dd5a bellard
}
1595 77f8dd5a bellard
#endif
1596 77f8dd5a bellard
1597 927f621e bellard
void OPPROTO op_fist_ST0_A0(void)
1598 927f621e bellard
{
1599 d014c98c bellard
#if defined(__sparc__) && !defined(__sparc_v9__)
1600 d014c98c bellard
    register CPU86_LDouble d asm("o0");
1601 d014c98c bellard
#else
1602 d014c98c bellard
    CPU86_LDouble d;
1603 d014c98c bellard
#endif
1604 927f621e bellard
    int val;
1605 d014c98c bellard
1606 d014c98c bellard
    d = ST0;
1607 d014c98c bellard
    val = lrint(d);
1608 1e5ffbed bellard
    if (val != (int16_t)val)
1609 1e5ffbed bellard
        val = -32768;
1610 927f621e bellard
    stw((void *)A0, val);
1611 927f621e bellard
}
1612 927f621e bellard
1613 927f621e bellard
void OPPROTO op_fistl_ST0_A0(void)
1614 927f621e bellard
{
1615 d014c98c bellard
#if defined(__sparc__) && !defined(__sparc_v9__)
1616 d014c98c bellard
    register CPU86_LDouble d asm("o0");
1617 d014c98c bellard
#else
1618 d014c98c bellard
    CPU86_LDouble d;
1619 d014c98c bellard
#endif
1620 927f621e bellard
    int val;
1621 d014c98c bellard
1622 d014c98c bellard
    d = ST0;
1623 d014c98c bellard
    val = lrint(d);
1624 927f621e bellard
    stl((void *)A0, val);
1625 927f621e bellard
}
1626 927f621e bellard
1627 927f621e bellard
void OPPROTO op_fistll_ST0_A0(void)
1628 927f621e bellard
{
1629 d014c98c bellard
#if defined(__sparc__) && !defined(__sparc_v9__)
1630 d014c98c bellard
    register CPU86_LDouble d asm("o0");
1631 d014c98c bellard
#else
1632 d014c98c bellard
    CPU86_LDouble d;
1633 d014c98c bellard
#endif
1634 927f621e bellard
    int64_t val;
1635 d014c98c bellard
1636 d014c98c bellard
    d = ST0;
1637 d014c98c bellard
    val = llrint(d);
1638 927f621e bellard
    stq((void *)A0, val);
1639 927f621e bellard
}
1640 927f621e bellard
1641 77f8dd5a bellard
void OPPROTO op_fbld_ST0_A0(void)
1642 77f8dd5a bellard
{
1643 77f8dd5a bellard
    helper_fbld_ST0_A0();
1644 77f8dd5a bellard
}
1645 77f8dd5a bellard
1646 77f8dd5a bellard
void OPPROTO op_fbst_ST0_A0(void)
1647 77f8dd5a bellard
{
1648 77f8dd5a bellard
    helper_fbst_ST0_A0();
1649 77f8dd5a bellard
}
1650 77f8dd5a bellard
1651 927f621e bellard
/* FPU move */
1652 927f621e bellard
1653 927f621e bellard
void OPPROTO op_fpush(void)
1654 927f621e bellard
{
1655 927f621e bellard
    fpush();
1656 927f621e bellard
}
1657 927f621e bellard
1658 927f621e bellard
void OPPROTO op_fpop(void)
1659 927f621e bellard
{
1660 927f621e bellard
    fpop();
1661 927f621e bellard
}
1662 927f621e bellard
1663 927f621e bellard
void OPPROTO op_fdecstp(void)
1664 927f621e bellard
{
1665 927f621e bellard
    env->fpstt = (env->fpstt - 1) & 7;
1666 927f621e bellard
    env->fpus &= (~0x4700);
1667 927f621e bellard
}
1668 927f621e bellard
1669 927f621e bellard
void OPPROTO op_fincstp(void)
1670 927f621e bellard
{
1671 927f621e bellard
    env->fpstt = (env->fpstt + 1) & 7;
1672 927f621e bellard
    env->fpus &= (~0x4700);
1673 927f621e bellard
}
1674 927f621e bellard
1675 927f621e bellard
void OPPROTO op_fmov_ST0_FT0(void)
1676 927f621e bellard
{
1677 927f621e bellard
    ST0 = FT0;
1678 927f621e bellard
}
1679 927f621e bellard
1680 927f621e bellard
void OPPROTO op_fmov_FT0_STN(void)
1681 927f621e bellard
{
1682 927f621e bellard
    FT0 = ST(PARAM1);
1683 927f621e bellard
}
1684 927f621e bellard
1685 927f621e bellard
void OPPROTO op_fmov_ST0_STN(void)
1686 927f621e bellard
{
1687 927f621e bellard
    ST0 = ST(PARAM1);
1688 927f621e bellard
}
1689 927f621e bellard
1690 927f621e bellard
void OPPROTO op_fmov_STN_ST0(void)
1691 927f621e bellard
{
1692 927f621e bellard
    ST(PARAM1) = ST0;
1693 927f621e bellard
}
1694 927f621e bellard
1695 927f621e bellard
void OPPROTO op_fxchg_ST0_STN(void)
1696 927f621e bellard
{
1697 927f621e bellard
    CPU86_LDouble tmp;
1698 927f621e bellard
    tmp = ST(PARAM1);
1699 927f621e bellard
    ST(PARAM1) = ST0;
1700 927f621e bellard
    ST0 = tmp;
1701 927f621e bellard
}
1702 927f621e bellard
1703 927f621e bellard
/* FPU operations */
1704 927f621e bellard
1705 927f621e bellard
/* XXX: handle nans */
1706 927f621e bellard
void OPPROTO op_fcom_ST0_FT0(void)
1707 927f621e bellard
{
1708 927f621e bellard
    env->fpus &= (~0x4500);        /* (C3,C2,C0) <-- 000 */
1709 927f621e bellard
    if (ST0 < FT0)
1710 927f621e bellard
        env->fpus |= 0x100;        /* (C3,C2,C0) <-- 001 */
1711 927f621e bellard
    else if (ST0 == FT0)
1712 927f621e bellard
        env->fpus |= 0x4000; /* (C3,C2,C0) <-- 100 */
1713 927f621e bellard
    FORCE_RET();
1714 927f621e bellard
}
1715 927f621e bellard
1716 77f8dd5a bellard
/* XXX: handle nans */
1717 77f8dd5a bellard
void OPPROTO op_fucom_ST0_FT0(void)
1718 77f8dd5a bellard
{
1719 77f8dd5a bellard
    env->fpus &= (~0x4500);        /* (C3,C2,C0) <-- 000 */
1720 77f8dd5a bellard
    if (ST0 < FT0)
1721 77f8dd5a bellard
        env->fpus |= 0x100;        /* (C3,C2,C0) <-- 001 */
1722 77f8dd5a bellard
    else if (ST0 == FT0)
1723 77f8dd5a bellard
        env->fpus |= 0x4000; /* (C3,C2,C0) <-- 100 */
1724 77f8dd5a bellard
    FORCE_RET();
1725 77f8dd5a bellard
}
1726 77f8dd5a bellard
1727 d0a1ffc9 bellard
/* XXX: handle nans */
1728 d0a1ffc9 bellard
void OPPROTO op_fcomi_ST0_FT0(void)
1729 d0a1ffc9 bellard
{
1730 d0a1ffc9 bellard
    int eflags;
1731 d0a1ffc9 bellard
    eflags = cc_table[CC_OP].compute_all();
1732 d0a1ffc9 bellard
    eflags &= ~(CC_Z | CC_P | CC_C);
1733 d0a1ffc9 bellard
    if (ST0 < FT0)
1734 d0a1ffc9 bellard
        eflags |= CC_C;
1735 d0a1ffc9 bellard
    else if (ST0 == FT0)
1736 d0a1ffc9 bellard
        eflags |= CC_Z;
1737 d0a1ffc9 bellard
    CC_SRC = eflags;
1738 d0a1ffc9 bellard
    FORCE_RET();
1739 d0a1ffc9 bellard
}
1740 d0a1ffc9 bellard
1741 d0a1ffc9 bellard
/* XXX: handle nans */
1742 d0a1ffc9 bellard
void OPPROTO op_fucomi_ST0_FT0(void)
1743 d0a1ffc9 bellard
{
1744 d0a1ffc9 bellard
    int eflags;
1745 d0a1ffc9 bellard
    eflags = cc_table[CC_OP].compute_all();
1746 d0a1ffc9 bellard
    eflags &= ~(CC_Z | CC_P | CC_C);
1747 d0a1ffc9 bellard
    if (ST0 < FT0)
1748 d0a1ffc9 bellard
        eflags |= CC_C;
1749 d0a1ffc9 bellard
    else if (ST0 == FT0)
1750 d0a1ffc9 bellard
        eflags |= CC_Z;
1751 d0a1ffc9 bellard
    CC_SRC = eflags;
1752 d0a1ffc9 bellard
    FORCE_RET();
1753 d0a1ffc9 bellard
}
1754 d0a1ffc9 bellard
1755 927f621e bellard
void OPPROTO op_fadd_ST0_FT0(void)
1756 927f621e bellard
{
1757 927f621e bellard
    ST0 += FT0;
1758 927f621e bellard
}
1759 927f621e bellard
1760 927f621e bellard
void OPPROTO op_fmul_ST0_FT0(void)
1761 927f621e bellard
{
1762 927f621e bellard
    ST0 *= FT0;
1763 927f621e bellard
}
1764 927f621e bellard
1765 927f621e bellard
void OPPROTO op_fsub_ST0_FT0(void)
1766 927f621e bellard
{
1767 927f621e bellard
    ST0 -= FT0;
1768 927f621e bellard
}
1769 927f621e bellard
1770 927f621e bellard
void OPPROTO op_fsubr_ST0_FT0(void)
1771 927f621e bellard
{
1772 927f621e bellard
    ST0 = FT0 - ST0;
1773 927f621e bellard
}
1774 927f621e bellard
1775 927f621e bellard
void OPPROTO op_fdiv_ST0_FT0(void)
1776 927f621e bellard
{
1777 927f621e bellard
    ST0 /= FT0;
1778 927f621e bellard
}
1779 927f621e bellard
1780 927f621e bellard
void OPPROTO op_fdivr_ST0_FT0(void)
1781 927f621e bellard
{
1782 927f621e bellard
    ST0 = FT0 / ST0;
1783 927f621e bellard
}
1784 927f621e bellard
1785 927f621e bellard
/* fp operations between STN and ST0 */
1786 927f621e bellard
1787 927f621e bellard
void OPPROTO op_fadd_STN_ST0(void)
1788 927f621e bellard
{
1789 927f621e bellard
    ST(PARAM1) += ST0;
1790 927f621e bellard
}
1791 927f621e bellard
1792 927f621e bellard
void OPPROTO op_fmul_STN_ST0(void)
1793 927f621e bellard
{
1794 927f621e bellard
    ST(PARAM1) *= ST0;
1795 927f621e bellard
}
1796 927f621e bellard
1797 927f621e bellard
void OPPROTO op_fsub_STN_ST0(void)
1798 927f621e bellard
{
1799 927f621e bellard
    ST(PARAM1) -= ST0;
1800 927f621e bellard
}
1801 927f621e bellard
1802 927f621e bellard
void OPPROTO op_fsubr_STN_ST0(void)
1803 927f621e bellard
{
1804 927f621e bellard
    CPU86_LDouble *p;
1805 927f621e bellard
    p = &ST(PARAM1);
1806 927f621e bellard
    *p = ST0 - *p;
1807 927f621e bellard
}
1808 927f621e bellard
1809 927f621e bellard
void OPPROTO op_fdiv_STN_ST0(void)
1810 927f621e bellard
{
1811 927f621e bellard
    ST(PARAM1) /= ST0;
1812 927f621e bellard
}
1813 927f621e bellard
1814 927f621e bellard
void OPPROTO op_fdivr_STN_ST0(void)
1815 927f621e bellard
{
1816 927f621e bellard
    CPU86_LDouble *p;
1817 927f621e bellard
    p = &ST(PARAM1);
1818 927f621e bellard
    *p = ST0 / *p;
1819 927f621e bellard
}
1820 927f621e bellard
1821 927f621e bellard
/* misc FPU operations */
1822 927f621e bellard
void OPPROTO op_fchs_ST0(void)
1823 927f621e bellard
{
1824 927f621e bellard
    ST0 = -ST0;
1825 927f621e bellard
}
1826 927f621e bellard
1827 927f621e bellard
void OPPROTO op_fabs_ST0(void)
1828 927f621e bellard
{
1829 927f621e bellard
    ST0 = fabs(ST0);
1830 927f621e bellard
}
1831 927f621e bellard
1832 77f8dd5a bellard
void OPPROTO op_fxam_ST0(void)
1833 77f8dd5a bellard
{
1834 77f8dd5a bellard
    helper_fxam_ST0();
1835 927f621e bellard
}
1836 927f621e bellard
1837 927f621e bellard
void OPPROTO op_fld1_ST0(void)
1838 927f621e bellard
{
1839 87f4827e bellard
    ST0 = f15rk[1];
1840 927f621e bellard
}
1841 927f621e bellard
1842 77f8dd5a bellard
void OPPROTO op_fldl2t_ST0(void)
1843 927f621e bellard
{
1844 87f4827e bellard
    ST0 = f15rk[6];
1845 927f621e bellard
}
1846 927f621e bellard
1847 77f8dd5a bellard
void OPPROTO op_fldl2e_ST0(void)
1848 927f621e bellard
{
1849 87f4827e bellard
    ST0 = f15rk[5];
1850 927f621e bellard
}
1851 927f621e bellard
1852 927f621e bellard
void OPPROTO op_fldpi_ST0(void)
1853 927f621e bellard
{
1854 87f4827e bellard
    ST0 = f15rk[2];
1855 927f621e bellard
}
1856 927f621e bellard
1857 927f621e bellard
void OPPROTO op_fldlg2_ST0(void)
1858 927f621e bellard
{
1859 87f4827e bellard
    ST0 = f15rk[3];
1860 927f621e bellard
}
1861 927f621e bellard
1862 927f621e bellard
void OPPROTO op_fldln2_ST0(void)
1863 927f621e bellard
{
1864 87f4827e bellard
    ST0 = f15rk[4];
1865 927f621e bellard
}
1866 927f621e bellard
1867 927f621e bellard
void OPPROTO op_fldz_ST0(void)
1868 927f621e bellard
{
1869 87f4827e bellard
    ST0 = f15rk[0];
1870 927f621e bellard
}
1871 927f621e bellard
1872 927f621e bellard
void OPPROTO op_fldz_FT0(void)
1873 927f621e bellard
{
1874 87f4827e bellard
    ST0 = f15rk[0];
1875 927f621e bellard
}
1876 927f621e bellard
1877 927f621e bellard
/* associated heplers to reduce generated code length and to simplify
1878 927f621e bellard
   relocation (FP constants are usually stored in .rodata section) */
1879 927f621e bellard
1880 927f621e bellard
void OPPROTO op_f2xm1(void)
1881 927f621e bellard
{
1882 927f621e bellard
    helper_f2xm1();
1883 927f621e bellard
}
1884 927f621e bellard
1885 927f621e bellard
void OPPROTO op_fyl2x(void)
1886 927f621e bellard
{
1887 927f621e bellard
    helper_fyl2x();
1888 927f621e bellard
}
1889 927f621e bellard
1890 927f621e bellard
void OPPROTO op_fptan(void)
1891 927f621e bellard
{
1892 927f621e bellard
    helper_fptan();
1893 927f621e bellard
}
1894 927f621e bellard
1895 927f621e bellard
void OPPROTO op_fpatan(void)
1896 927f621e bellard
{
1897 927f621e bellard
    helper_fpatan();
1898 927f621e bellard
}
1899 927f621e bellard
1900 927f621e bellard
void OPPROTO op_fxtract(void)
1901 927f621e bellard
{
1902 927f621e bellard
    helper_fxtract();
1903 927f621e bellard
}
1904 927f621e bellard
1905 927f621e bellard
void OPPROTO op_fprem1(void)
1906 927f621e bellard
{
1907 927f621e bellard
    helper_fprem1();
1908 927f621e bellard
}
1909 927f621e bellard
1910 927f621e bellard
1911 927f621e bellard
void OPPROTO op_fprem(void)
1912 927f621e bellard
{
1913 927f621e bellard
    helper_fprem();
1914 927f621e bellard
}
1915 927f621e bellard
1916 927f621e bellard
void OPPROTO op_fyl2xp1(void)
1917 927f621e bellard
{
1918 927f621e bellard
    helper_fyl2xp1();
1919 927f621e bellard
}
1920 927f621e bellard
1921 927f621e bellard
void OPPROTO op_fsqrt(void)
1922 927f621e bellard
{
1923 927f621e bellard
    helper_fsqrt();
1924 927f621e bellard
}
1925 927f621e bellard
1926 927f621e bellard
void OPPROTO op_fsincos(void)
1927 927f621e bellard
{
1928 927f621e bellard
    helper_fsincos();
1929 927f621e bellard
}
1930 927f621e bellard
1931 927f621e bellard
void OPPROTO op_frndint(void)
1932 927f621e bellard
{
1933 927f621e bellard
    helper_frndint();
1934 927f621e bellard
}
1935 927f621e bellard
1936 927f621e bellard
void OPPROTO op_fscale(void)
1937 927f621e bellard
{
1938 927f621e bellard
    helper_fscale();
1939 927f621e bellard
}
1940 927f621e bellard
1941 927f621e bellard
void OPPROTO op_fsin(void)
1942 927f621e bellard
{
1943 927f621e bellard
    helper_fsin();
1944 927f621e bellard
}
1945 927f621e bellard
1946 927f621e bellard
void OPPROTO op_fcos(void)
1947 927f621e bellard
{
1948 927f621e bellard
    helper_fcos();
1949 927f621e bellard
}
1950 927f621e bellard
1951 4b74fe1f bellard
void OPPROTO op_fnstsw_A0(void)
1952 4b74fe1f bellard
{
1953 4b74fe1f bellard
    int fpus;
1954 4b74fe1f bellard
    fpus = (env->fpus & ~0x3800) | (env->fpstt & 0x7) << 11;
1955 4b74fe1f bellard
    stw((void *)A0, fpus);
1956 4b74fe1f bellard
}
1957 4b74fe1f bellard
1958 77f8dd5a bellard
void OPPROTO op_fnstsw_EAX(void)
1959 77f8dd5a bellard
{
1960 77f8dd5a bellard
    int fpus;
1961 77f8dd5a bellard
    fpus = (env->fpus & ~0x3800) | (env->fpstt & 0x7) << 11;
1962 77f8dd5a bellard
    EAX = (EAX & 0xffff0000) | fpus;
1963 77f8dd5a bellard
}
1964 77f8dd5a bellard
1965 4b74fe1f bellard
void OPPROTO op_fnstcw_A0(void)
1966 4b74fe1f bellard
{
1967 4b74fe1f bellard
    stw((void *)A0, env->fpuc);
1968 4b74fe1f bellard
}
1969 4b74fe1f bellard
1970 4b74fe1f bellard
void OPPROTO op_fldcw_A0(void)
1971 4b74fe1f bellard
{
1972 4b74fe1f bellard
    int rnd_type;
1973 4b74fe1f bellard
    env->fpuc = lduw((void *)A0);
1974 4b74fe1f bellard
    /* set rounding mode */
1975 4b74fe1f bellard
    switch(env->fpuc & RC_MASK) {
1976 4b74fe1f bellard
    default:
1977 4b74fe1f bellard
    case RC_NEAR:
1978 4b74fe1f bellard
        rnd_type = FE_TONEAREST;
1979 4b74fe1f bellard
        break;
1980 4b74fe1f bellard
    case RC_DOWN:
1981 4b74fe1f bellard
        rnd_type = FE_DOWNWARD;
1982 4b74fe1f bellard
        break;
1983 4b74fe1f bellard
    case RC_UP:
1984 4b74fe1f bellard
        rnd_type = FE_UPWARD;
1985 4b74fe1f bellard
        break;
1986 4b74fe1f bellard
    case RC_CHOP:
1987 4b74fe1f bellard
        rnd_type = FE_TOWARDZERO;
1988 4b74fe1f bellard
        break;
1989 4b74fe1f bellard
    }
1990 4b74fe1f bellard
    fesetround(rnd_type);
1991 4b74fe1f bellard
}
1992 4b74fe1f bellard
1993 1a9353d2 bellard
void OPPROTO op_fclex(void)
1994 1a9353d2 bellard
{
1995 1a9353d2 bellard
    env->fpus &= 0x7f00;
1996 1a9353d2 bellard
}
1997 1a9353d2 bellard
1998 1a9353d2 bellard
void OPPROTO op_fninit(void)
1999 1a9353d2 bellard
{
2000 1a9353d2 bellard
    env->fpus = 0;
2001 1a9353d2 bellard
    env->fpstt = 0;
2002 1a9353d2 bellard
    env->fpuc = 0x37f;
2003 1a9353d2 bellard
    env->fptags[0] = 1;
2004 1a9353d2 bellard
    env->fptags[1] = 1;
2005 1a9353d2 bellard
    env->fptags[2] = 1;
2006 1a9353d2 bellard
    env->fptags[3] = 1;
2007 1a9353d2 bellard
    env->fptags[4] = 1;
2008 1a9353d2 bellard
    env->fptags[5] = 1;
2009 1a9353d2 bellard
    env->fptags[6] = 1;
2010 1a9353d2 bellard
    env->fptags[7] = 1;
2011 1a9353d2 bellard
}
2012 1b6b029e bellard
2013 d0a1ffc9 bellard
void OPPROTO op_fnstenv_A0(void)
2014 d0a1ffc9 bellard
{
2015 d0a1ffc9 bellard
    helper_fstenv((uint8_t *)A0, PARAM1);
2016 d0a1ffc9 bellard
}
2017 d0a1ffc9 bellard
2018 d0a1ffc9 bellard
void OPPROTO op_fldenv_A0(void)
2019 d0a1ffc9 bellard
{
2020 d0a1ffc9 bellard
    helper_fldenv((uint8_t *)A0, PARAM1);
2021 d0a1ffc9 bellard
}
2022 d0a1ffc9 bellard
2023 d0a1ffc9 bellard
void OPPROTO op_fnsave_A0(void)
2024 d0a1ffc9 bellard
{
2025 d0a1ffc9 bellard
    helper_fsave((uint8_t *)A0, PARAM1);
2026 d0a1ffc9 bellard
}
2027 d0a1ffc9 bellard
2028 d0a1ffc9 bellard
void OPPROTO op_frstor_A0(void)
2029 d0a1ffc9 bellard
{
2030 d0a1ffc9 bellard
    helper_frstor((uint8_t *)A0, PARAM1);
2031 d0a1ffc9 bellard
}
2032 d0a1ffc9 bellard
2033 1b6b029e bellard
/* threading support */
2034 1b6b029e bellard
void OPPROTO op_lock(void)
2035 1b6b029e bellard
{
2036 1b6b029e bellard
    cpu_lock();
2037 1b6b029e bellard
}
2038 1b6b029e bellard
2039 1b6b029e bellard
void OPPROTO op_unlock(void)
2040 1b6b029e bellard
{
2041 1b6b029e bellard
    cpu_unlock();
2042 1b6b029e bellard
}