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1 | 3475187d | bellard | /*
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2 | 3475187d | bellard | * QEMU Sun4u System Emulator
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3 | 5fafdf24 | ths | *
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4 | 3475187d | bellard | * Copyright (c) 2005 Fabrice Bellard
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5 | 5fafdf24 | ths | *
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6 | 3475187d | bellard | * Permission is hereby granted, free of charge, to any person obtaining a copy
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7 | 3475187d | bellard | * of this software and associated documentation files (the "Software"), to deal
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8 | 3475187d | bellard | * in the Software without restriction, including without limitation the rights
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9 | 3475187d | bellard | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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10 | 3475187d | bellard | * copies of the Software, and to permit persons to whom the Software is
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11 | 3475187d | bellard | * furnished to do so, subject to the following conditions:
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12 | 3475187d | bellard | *
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13 | 3475187d | bellard | * The above copyright notice and this permission notice shall be included in
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14 | 3475187d | bellard | * all copies or substantial portions of the Software.
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15 | 3475187d | bellard | *
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16 | 3475187d | bellard | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 | 3475187d | bellard | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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18 | 3475187d | bellard | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 | 3475187d | bellard | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 | 3475187d | bellard | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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21 | 3475187d | bellard | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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22 | 3475187d | bellard | * THE SOFTWARE.
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23 | 3475187d | bellard | */
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24 | 3475187d | bellard | #include "vl.h" |
25 | 83469015 | bellard | #include "m48t59.h" |
26 | 3475187d | bellard | |
27 | 83469015 | bellard | #define KERNEL_LOAD_ADDR 0x00404000 |
28 | 83469015 | bellard | #define CMDLINE_ADDR 0x003ff000 |
29 | 83469015 | bellard | #define INITRD_LOAD_ADDR 0x00300000 |
30 | 75956cf0 | pbrook | #define PROM_SIZE_MAX (512 * 1024) |
31 | f930d07e | blueswir1 | #define PROM_ADDR 0x1fff0000000ULL |
32 | f930d07e | blueswir1 | #define PROM_VADDR 0x000ffd00000ULL |
33 | 83469015 | bellard | #define APB_SPECIAL_BASE 0x1fe00000000ULL |
34 | f930d07e | blueswir1 | #define APB_MEM_BASE 0x1ff00000000ULL |
35 | f930d07e | blueswir1 | #define VGA_BASE (APB_MEM_BASE + 0x400000ULL) |
36 | f930d07e | blueswir1 | #define PROM_FILENAME "openbios-sparc64" |
37 | 83469015 | bellard | #define NVRAM_SIZE 0x2000 |
38 | 3475187d | bellard | |
39 | 3475187d | bellard | /* TSC handling */
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40 | 3475187d | bellard | |
41 | 3475187d | bellard | uint64_t cpu_get_tsc() |
42 | 3475187d | bellard | { |
43 | 3475187d | bellard | return qemu_get_clock(vm_clock);
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44 | 3475187d | bellard | } |
45 | 3475187d | bellard | |
46 | 3475187d | bellard | int DMA_get_channel_mode (int nchan) |
47 | 3475187d | bellard | { |
48 | 3475187d | bellard | return 0; |
49 | 3475187d | bellard | } |
50 | 3475187d | bellard | int DMA_read_memory (int nchan, void *buf, int pos, int size) |
51 | 3475187d | bellard | { |
52 | 3475187d | bellard | return 0; |
53 | 3475187d | bellard | } |
54 | 3475187d | bellard | int DMA_write_memory (int nchan, void *buf, int pos, int size) |
55 | 3475187d | bellard | { |
56 | 3475187d | bellard | return 0; |
57 | 3475187d | bellard | } |
58 | 3475187d | bellard | void DMA_hold_DREQ (int nchan) {} |
59 | 3475187d | bellard | void DMA_release_DREQ (int nchan) {} |
60 | 3475187d | bellard | void DMA_schedule(int nchan) {} |
61 | 3475187d | bellard | void DMA_run (void) {} |
62 | 3475187d | bellard | void DMA_init (int high_page_enable) {} |
63 | 3475187d | bellard | void DMA_register_channel (int nchan, |
64 | 3475187d | bellard | DMA_transfer_handler transfer_handler, |
65 | 3475187d | bellard | void *opaque)
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66 | 3475187d | bellard | { |
67 | 3475187d | bellard | } |
68 | 3475187d | bellard | |
69 | 83469015 | bellard | /* NVRAM helpers */
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70 | 83469015 | bellard | void NVRAM_set_byte (m48t59_t *nvram, uint32_t addr, uint8_t value)
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71 | 3475187d | bellard | { |
72 | 819385c5 | bellard | m48t59_write(nvram, addr, value); |
73 | 3475187d | bellard | } |
74 | 3475187d | bellard | |
75 | 83469015 | bellard | uint8_t NVRAM_get_byte (m48t59_t *nvram, uint32_t addr) |
76 | 3475187d | bellard | { |
77 | 819385c5 | bellard | return m48t59_read(nvram, addr);
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78 | 3475187d | bellard | } |
79 | 3475187d | bellard | |
80 | 83469015 | bellard | void NVRAM_set_word (m48t59_t *nvram, uint32_t addr, uint16_t value)
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81 | 83469015 | bellard | { |
82 | 819385c5 | bellard | m48t59_write(nvram, addr, value >> 8);
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83 | 819385c5 | bellard | m48t59_write(nvram, addr + 1, value & 0xFF); |
84 | 83469015 | bellard | } |
85 | 83469015 | bellard | |
86 | 83469015 | bellard | uint16_t NVRAM_get_word (m48t59_t *nvram, uint32_t addr) |
87 | 83469015 | bellard | { |
88 | 83469015 | bellard | uint16_t tmp; |
89 | 83469015 | bellard | |
90 | 819385c5 | bellard | tmp = m48t59_read(nvram, addr) << 8;
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91 | 819385c5 | bellard | tmp |= m48t59_read(nvram, addr + 1);
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92 | 83469015 | bellard | |
93 | 83469015 | bellard | return tmp;
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94 | 83469015 | bellard | } |
95 | 83469015 | bellard | |
96 | 83469015 | bellard | void NVRAM_set_lword (m48t59_t *nvram, uint32_t addr, uint32_t value)
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97 | 83469015 | bellard | { |
98 | 819385c5 | bellard | m48t59_write(nvram, addr, value >> 24);
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99 | 819385c5 | bellard | m48t59_write(nvram, addr + 1, (value >> 16) & 0xFF); |
100 | 819385c5 | bellard | m48t59_write(nvram, addr + 2, (value >> 8) & 0xFF); |
101 | 819385c5 | bellard | m48t59_write(nvram, addr + 3, value & 0xFF); |
102 | 83469015 | bellard | } |
103 | 83469015 | bellard | |
104 | 83469015 | bellard | uint32_t NVRAM_get_lword (m48t59_t *nvram, uint32_t addr) |
105 | 83469015 | bellard | { |
106 | 83469015 | bellard | uint32_t tmp; |
107 | 83469015 | bellard | |
108 | 819385c5 | bellard | tmp = m48t59_read(nvram, addr) << 24;
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109 | 819385c5 | bellard | tmp |= m48t59_read(nvram, addr + 1) << 16; |
110 | 819385c5 | bellard | tmp |= m48t59_read(nvram, addr + 2) << 8; |
111 | 819385c5 | bellard | tmp |= m48t59_read(nvram, addr + 3);
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112 | 83469015 | bellard | |
113 | 83469015 | bellard | return tmp;
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114 | 83469015 | bellard | } |
115 | 83469015 | bellard | |
116 | 83469015 | bellard | void NVRAM_set_string (m48t59_t *nvram, uint32_t addr,
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117 | 3475187d | bellard | const unsigned char *str, uint32_t max) |
118 | 3475187d | bellard | { |
119 | 83469015 | bellard | int i;
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120 | 3475187d | bellard | |
121 | 3475187d | bellard | for (i = 0; i < max && str[i] != '\0'; i++) { |
122 | 819385c5 | bellard | m48t59_write(nvram, addr + i, str[i]); |
123 | 3475187d | bellard | } |
124 | 819385c5 | bellard | m48t59_write(nvram, addr + max - 1, '\0'); |
125 | 3475187d | bellard | } |
126 | 3475187d | bellard | |
127 | 83469015 | bellard | int NVRAM_get_string (m48t59_t *nvram, uint8_t *dst, uint16_t addr, int max) |
128 | 83469015 | bellard | { |
129 | 83469015 | bellard | int i;
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130 | 83469015 | bellard | |
131 | 83469015 | bellard | memset(dst, 0, max);
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132 | 83469015 | bellard | for (i = 0; i < max; i++) { |
133 | 83469015 | bellard | dst[i] = NVRAM_get_byte(nvram, addr + i); |
134 | 83469015 | bellard | if (dst[i] == '\0') |
135 | 83469015 | bellard | break;
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136 | 83469015 | bellard | } |
137 | 83469015 | bellard | |
138 | 83469015 | bellard | return i;
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139 | 83469015 | bellard | } |
140 | 83469015 | bellard | |
141 | 83469015 | bellard | static uint16_t NVRAM_crc_update (uint16_t prev, uint16_t value)
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142 | 83469015 | bellard | { |
143 | 83469015 | bellard | uint16_t tmp; |
144 | 83469015 | bellard | uint16_t pd, pd1, pd2; |
145 | 83469015 | bellard | |
146 | 83469015 | bellard | tmp = prev >> 8;
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147 | 83469015 | bellard | pd = prev ^ value; |
148 | 83469015 | bellard | pd1 = pd & 0x000F;
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149 | 83469015 | bellard | pd2 = ((pd >> 4) & 0x000F) ^ pd1; |
150 | 83469015 | bellard | tmp ^= (pd1 << 3) | (pd1 << 8); |
151 | 83469015 | bellard | tmp ^= pd2 | (pd2 << 7) | (pd2 << 12); |
152 | 83469015 | bellard | |
153 | 83469015 | bellard | return tmp;
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154 | 83469015 | bellard | } |
155 | 83469015 | bellard | |
156 | 83469015 | bellard | uint16_t NVRAM_compute_crc (m48t59_t *nvram, uint32_t start, uint32_t count) |
157 | 83469015 | bellard | { |
158 | 83469015 | bellard | uint32_t i; |
159 | 83469015 | bellard | uint16_t crc = 0xFFFF;
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160 | 83469015 | bellard | int odd;
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161 | 83469015 | bellard | |
162 | 83469015 | bellard | odd = count & 1;
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163 | 83469015 | bellard | count &= ~1;
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164 | 83469015 | bellard | for (i = 0; i != count; i++) { |
165 | f930d07e | blueswir1 | crc = NVRAM_crc_update(crc, NVRAM_get_word(nvram, start + i)); |
166 | 83469015 | bellard | } |
167 | 83469015 | bellard | if (odd) {
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168 | f930d07e | blueswir1 | crc = NVRAM_crc_update(crc, NVRAM_get_byte(nvram, start + i) << 8);
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169 | 83469015 | bellard | } |
170 | 83469015 | bellard | |
171 | 83469015 | bellard | return crc;
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172 | 83469015 | bellard | } |
173 | 3475187d | bellard | |
174 | 66508601 | blueswir1 | static uint32_t nvram_set_var (m48t59_t *nvram, uint32_t addr,
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175 | 66508601 | blueswir1 | const unsigned char *str) |
176 | 66508601 | blueswir1 | { |
177 | 66508601 | blueswir1 | uint32_t len; |
178 | 66508601 | blueswir1 | |
179 | 66508601 | blueswir1 | len = strlen(str) + 1;
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180 | 66508601 | blueswir1 | NVRAM_set_string(nvram, addr, str, len); |
181 | 66508601 | blueswir1 | |
182 | 66508601 | blueswir1 | return addr + len;
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183 | 66508601 | blueswir1 | } |
184 | 66508601 | blueswir1 | |
185 | 66508601 | blueswir1 | static void nvram_finish_partition (m48t59_t *nvram, uint32_t start, |
186 | 66508601 | blueswir1 | uint32_t end) |
187 | 66508601 | blueswir1 | { |
188 | 66508601 | blueswir1 | unsigned int i, sum; |
189 | 66508601 | blueswir1 | |
190 | 66508601 | blueswir1 | // Length divided by 16
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191 | 66508601 | blueswir1 | m48t59_write(nvram, start + 2, ((end - start) >> 12) & 0xff); |
192 | 66508601 | blueswir1 | m48t59_write(nvram, start + 3, ((end - start) >> 4) & 0xff); |
193 | 66508601 | blueswir1 | // Checksum
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194 | 66508601 | blueswir1 | sum = m48t59_read(nvram, start); |
195 | 66508601 | blueswir1 | for (i = 0; i < 14; i++) { |
196 | 66508601 | blueswir1 | sum += m48t59_read(nvram, start + 2 + i);
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197 | 66508601 | blueswir1 | sum = (sum + ((sum & 0xff00) >> 8)) & 0xff; |
198 | 66508601 | blueswir1 | } |
199 | 66508601 | blueswir1 | m48t59_write(nvram, start + 1, sum & 0xff); |
200 | 66508601 | blueswir1 | } |
201 | 66508601 | blueswir1 | |
202 | 3475187d | bellard | extern int nographic; |
203 | 3475187d | bellard | |
204 | 83469015 | bellard | int sun4u_NVRAM_set_params (m48t59_t *nvram, uint16_t NVRAM_size,
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205 | 83469015 | bellard | const unsigned char *arch, |
206 | 83469015 | bellard | uint32_t RAM_size, int boot_device,
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207 | 83469015 | bellard | uint32_t kernel_image, uint32_t kernel_size, |
208 | 83469015 | bellard | const char *cmdline, |
209 | 83469015 | bellard | uint32_t initrd_image, uint32_t initrd_size, |
210 | 83469015 | bellard | uint32_t NVRAM_image, |
211 | 83469015 | bellard | int width, int height, int depth) |
212 | 83469015 | bellard | { |
213 | 83469015 | bellard | uint16_t crc; |
214 | 66508601 | blueswir1 | unsigned int i; |
215 | 66508601 | blueswir1 | uint32_t start, end; |
216 | 83469015 | bellard | |
217 | 83469015 | bellard | /* Set parameters for Open Hack'Ware BIOS */
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218 | 83469015 | bellard | NVRAM_set_string(nvram, 0x00, "QEMU_BIOS", 16); |
219 | 83469015 | bellard | NVRAM_set_lword(nvram, 0x10, 0x00000002); /* structure v2 */ |
220 | 83469015 | bellard | NVRAM_set_word(nvram, 0x14, NVRAM_size);
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221 | 83469015 | bellard | NVRAM_set_string(nvram, 0x20, arch, 16); |
222 | 83469015 | bellard | NVRAM_set_byte(nvram, 0x2f, nographic & 0xff); |
223 | 83469015 | bellard | NVRAM_set_lword(nvram, 0x30, RAM_size);
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224 | 83469015 | bellard | NVRAM_set_byte(nvram, 0x34, boot_device);
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225 | 83469015 | bellard | NVRAM_set_lword(nvram, 0x38, kernel_image);
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226 | 83469015 | bellard | NVRAM_set_lword(nvram, 0x3C, kernel_size);
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227 | 3475187d | bellard | if (cmdline) {
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228 | 83469015 | bellard | /* XXX: put the cmdline in NVRAM too ? */
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229 | 83469015 | bellard | strcpy(phys_ram_base + CMDLINE_ADDR, cmdline); |
230 | 83469015 | bellard | NVRAM_set_lword(nvram, 0x40, CMDLINE_ADDR);
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231 | 83469015 | bellard | NVRAM_set_lword(nvram, 0x44, strlen(cmdline));
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232 | 83469015 | bellard | } else {
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233 | 83469015 | bellard | NVRAM_set_lword(nvram, 0x40, 0); |
234 | 83469015 | bellard | NVRAM_set_lword(nvram, 0x44, 0); |
235 | 3475187d | bellard | } |
236 | 83469015 | bellard | NVRAM_set_lword(nvram, 0x48, initrd_image);
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237 | 83469015 | bellard | NVRAM_set_lword(nvram, 0x4C, initrd_size);
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238 | 83469015 | bellard | NVRAM_set_lword(nvram, 0x50, NVRAM_image);
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239 | 83469015 | bellard | |
240 | 83469015 | bellard | NVRAM_set_word(nvram, 0x54, width);
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241 | 83469015 | bellard | NVRAM_set_word(nvram, 0x56, height);
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242 | 83469015 | bellard | NVRAM_set_word(nvram, 0x58, depth);
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243 | 83469015 | bellard | crc = NVRAM_compute_crc(nvram, 0x00, 0xF8); |
244 | 83469015 | bellard | NVRAM_set_word(nvram, 0xFC, crc);
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245 | 83469015 | bellard | |
246 | 66508601 | blueswir1 | // OpenBIOS nvram variables
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247 | 66508601 | blueswir1 | // Variable partition
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248 | f19e918d | blueswir1 | start = 256;
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249 | 66508601 | blueswir1 | m48t59_write(nvram, start, 0x70);
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250 | 66508601 | blueswir1 | NVRAM_set_string(nvram, start + 4, "system", 12); |
251 | 66508601 | blueswir1 | |
252 | 66508601 | blueswir1 | end = start + 16;
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253 | 66508601 | blueswir1 | for (i = 0; i < nb_prom_envs; i++) |
254 | 66508601 | blueswir1 | end = nvram_set_var(nvram, end, prom_envs[i]); |
255 | 66508601 | blueswir1 | |
256 | 66508601 | blueswir1 | m48t59_write(nvram, end++ , 0);
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257 | 66508601 | blueswir1 | end = start + ((end - start + 15) & ~15); |
258 | 66508601 | blueswir1 | nvram_finish_partition(nvram, start, end); |
259 | 66508601 | blueswir1 | |
260 | 66508601 | blueswir1 | // free partition
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261 | 66508601 | blueswir1 | start = end; |
262 | 66508601 | blueswir1 | m48t59_write(nvram, start, 0x7f);
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263 | 66508601 | blueswir1 | NVRAM_set_string(nvram, start + 4, "free", 12); |
264 | 66508601 | blueswir1 | |
265 | 66508601 | blueswir1 | end = 0x1fd0;
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266 | 66508601 | blueswir1 | nvram_finish_partition(nvram, start, end); |
267 | 66508601 | blueswir1 | |
268 | 83469015 | bellard | return 0; |
269 | 3475187d | bellard | } |
270 | 3475187d | bellard | |
271 | 3475187d | bellard | void pic_info()
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272 | 3475187d | bellard | { |
273 | 3475187d | bellard | } |
274 | 3475187d | bellard | |
275 | 3475187d | bellard | void irq_info()
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276 | 3475187d | bellard | { |
277 | 3475187d | bellard | } |
278 | 3475187d | bellard | |
279 | 83469015 | bellard | void qemu_system_powerdown(void) |
280 | 3475187d | bellard | { |
281 | 3475187d | bellard | } |
282 | 3475187d | bellard | |
283 | c68ea704 | bellard | static void main_cpu_reset(void *opaque) |
284 | c68ea704 | bellard | { |
285 | c68ea704 | bellard | CPUState *env = opaque; |
286 | 20c9f095 | blueswir1 | |
287 | c68ea704 | bellard | cpu_reset(env); |
288 | 20c9f095 | blueswir1 | ptimer_set_limit(env->tick, 0x7fffffffffffffffULL, 1); |
289 | 20c9f095 | blueswir1 | ptimer_run(env->tick, 0);
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290 | 20c9f095 | blueswir1 | ptimer_set_limit(env->stick, 0x7fffffffffffffffULL, 1); |
291 | 20c9f095 | blueswir1 | ptimer_run(env->stick, 0);
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292 | 20c9f095 | blueswir1 | ptimer_set_limit(env->hstick, 0x7fffffffffffffffULL, 1); |
293 | 20c9f095 | blueswir1 | ptimer_run(env->hstick, 0);
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294 | 20c9f095 | blueswir1 | } |
295 | 20c9f095 | blueswir1 | |
296 | 20c9f095 | blueswir1 | void tick_irq(void *opaque) |
297 | 20c9f095 | blueswir1 | { |
298 | 20c9f095 | blueswir1 | CPUState *env = opaque; |
299 | 20c9f095 | blueswir1 | |
300 | 20c9f095 | blueswir1 | cpu_interrupt(env, CPU_INTERRUPT_TIMER); |
301 | 20c9f095 | blueswir1 | } |
302 | 20c9f095 | blueswir1 | |
303 | 20c9f095 | blueswir1 | void stick_irq(void *opaque) |
304 | 20c9f095 | blueswir1 | { |
305 | 20c9f095 | blueswir1 | CPUState *env = opaque; |
306 | 20c9f095 | blueswir1 | |
307 | 20c9f095 | blueswir1 | cpu_interrupt(env, CPU_INTERRUPT_TIMER); |
308 | 20c9f095 | blueswir1 | } |
309 | 20c9f095 | blueswir1 | |
310 | 20c9f095 | blueswir1 | void hstick_irq(void *opaque) |
311 | 20c9f095 | blueswir1 | { |
312 | 20c9f095 | blueswir1 | CPUState *env = opaque; |
313 | 20c9f095 | blueswir1 | |
314 | 20c9f095 | blueswir1 | cpu_interrupt(env, CPU_INTERRUPT_TIMER); |
315 | c68ea704 | bellard | } |
316 | c68ea704 | bellard | |
317 | f19e918d | blueswir1 | static void dummy_cpu_set_irq(void *opaque, int irq, int level) |
318 | f19e918d | blueswir1 | { |
319 | f19e918d | blueswir1 | } |
320 | f19e918d | blueswir1 | |
321 | 83469015 | bellard | static const int ide_iobase[2] = { 0x1f0, 0x170 }; |
322 | 83469015 | bellard | static const int ide_iobase2[2] = { 0x3f6, 0x376 }; |
323 | 83469015 | bellard | static const int ide_irq[2] = { 14, 15 }; |
324 | 3475187d | bellard | |
325 | 83469015 | bellard | static const int serial_io[MAX_SERIAL_PORTS] = { 0x3f8, 0x2f8, 0x3e8, 0x2e8 }; |
326 | 83469015 | bellard | static const int serial_irq[MAX_SERIAL_PORTS] = { 4, 3, 4, 3 }; |
327 | 83469015 | bellard | |
328 | 83469015 | bellard | static const int parallel_io[MAX_PARALLEL_PORTS] = { 0x378, 0x278, 0x3bc }; |
329 | 83469015 | bellard | static const int parallel_irq[MAX_PARALLEL_PORTS] = { 7, 7, 7 }; |
330 | 83469015 | bellard | |
331 | 83469015 | bellard | static fdctrl_t *floppy_controller;
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332 | 3475187d | bellard | |
333 | 3475187d | bellard | /* Sun4u hardware initialisation */
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334 | 3475187d | bellard | static void sun4u_init(int ram_size, int vga_ram_size, int boot_device, |
335 | 3475187d | bellard | DisplayState *ds, const char **fd_filename, int snapshot, |
336 | 3475187d | bellard | const char *kernel_filename, const char *kernel_cmdline, |
337 | 94fc95cd | j_mayer | const char *initrd_filename, const char *cpu_model) |
338 | 3475187d | bellard | { |
339 | c68ea704 | bellard | CPUState *env; |
340 | 3475187d | bellard | char buf[1024]; |
341 | 83469015 | bellard | m48t59_t *nvram; |
342 | 3475187d | bellard | int ret, linux_boot;
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343 | 3475187d | bellard | unsigned int i; |
344 | 83469015 | bellard | long prom_offset, initrd_size, kernel_size;
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345 | 83469015 | bellard | PCIBus *pci_bus; |
346 | 62724a37 | blueswir1 | const sparc_def_t *def;
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347 | 20c9f095 | blueswir1 | QEMUBH *bh; |
348 | f19e918d | blueswir1 | qemu_irq *irq; |
349 | 3475187d | bellard | |
350 | 3475187d | bellard | linux_boot = (kernel_filename != NULL);
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351 | 3475187d | bellard | |
352 | 62724a37 | blueswir1 | /* init CPUs */
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353 | 62724a37 | blueswir1 | if (cpu_model == NULL) |
354 | 62724a37 | blueswir1 | cpu_model = "TI UltraSparc II";
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355 | 62724a37 | blueswir1 | sparc_find_by_name(cpu_model, &def); |
356 | 62724a37 | blueswir1 | if (def == NULL) { |
357 | 62724a37 | blueswir1 | fprintf(stderr, "Unable to find Sparc CPU definition\n");
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358 | 62724a37 | blueswir1 | exit(1);
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359 | 62724a37 | blueswir1 | } |
360 | c68ea704 | bellard | env = cpu_init(); |
361 | 952a328f | blueswir1 | cpu_sparc_register(env, def, 0);
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362 | 20c9f095 | blueswir1 | bh = qemu_bh_new(tick_irq, env); |
363 | 20c9f095 | blueswir1 | env->tick = ptimer_init(bh); |
364 | 20c9f095 | blueswir1 | ptimer_set_period(env->tick, 1ULL);
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365 | 20c9f095 | blueswir1 | |
366 | 20c9f095 | blueswir1 | bh = qemu_bh_new(stick_irq, env); |
367 | 20c9f095 | blueswir1 | env->stick = ptimer_init(bh); |
368 | 20c9f095 | blueswir1 | ptimer_set_period(env->stick, 1ULL);
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369 | 20c9f095 | blueswir1 | |
370 | 20c9f095 | blueswir1 | bh = qemu_bh_new(hstick_irq, env); |
371 | 20c9f095 | blueswir1 | env->hstick = ptimer_init(bh); |
372 | 20c9f095 | blueswir1 | ptimer_set_period(env->hstick, 1ULL);
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373 | c68ea704 | bellard | register_savevm("cpu", 0, 3, cpu_save, cpu_load, env); |
374 | c68ea704 | bellard | qemu_register_reset(main_cpu_reset, env); |
375 | 20c9f095 | blueswir1 | main_cpu_reset(env); |
376 | c68ea704 | bellard | |
377 | 3475187d | bellard | /* allocate RAM */
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378 | 3475187d | bellard | cpu_register_physical_memory(0, ram_size, 0); |
379 | 3475187d | bellard | |
380 | 83469015 | bellard | prom_offset = ram_size + vga_ram_size; |
381 | 5fafdf24 | ths | cpu_register_physical_memory(PROM_ADDR, |
382 | 5fafdf24 | ths | (PROM_SIZE_MAX + TARGET_PAGE_SIZE) & TARGET_PAGE_MASK, |
383 | b3783731 | bellard | prom_offset | IO_MEM_ROM); |
384 | 3475187d | bellard | |
385 | 1192dad8 | j_mayer | if (bios_name == NULL) |
386 | 1192dad8 | j_mayer | bios_name = PROM_FILENAME; |
387 | 1192dad8 | j_mayer | snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name); |
388 | f19e918d | blueswir1 | ret = load_elf(buf, PROM_ADDR - PROM_VADDR, NULL, NULL, NULL); |
389 | 3475187d | bellard | if (ret < 0) { |
390 | f930d07e | blueswir1 | fprintf(stderr, "qemu: could not load prom '%s'\n",
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391 | f930d07e | blueswir1 | buf); |
392 | f930d07e | blueswir1 | exit(1);
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393 | 3475187d | bellard | } |
394 | 3475187d | bellard | |
395 | 3475187d | bellard | kernel_size = 0;
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396 | 83469015 | bellard | initrd_size = 0;
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397 | 3475187d | bellard | if (linux_boot) {
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398 | b3783731 | bellard | /* XXX: put correct offset */
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399 | 74287114 | ths | kernel_size = load_elf(kernel_filename, 0, NULL, NULL, NULL); |
400 | 3475187d | bellard | if (kernel_size < 0) |
401 | f930d07e | blueswir1 | kernel_size = load_aout(kernel_filename, phys_ram_base + KERNEL_LOAD_ADDR); |
402 | f930d07e | blueswir1 | if (kernel_size < 0) |
403 | f930d07e | blueswir1 | kernel_size = load_image(kernel_filename, phys_ram_base + KERNEL_LOAD_ADDR); |
404 | 3475187d | bellard | if (kernel_size < 0) { |
405 | 5fafdf24 | ths | fprintf(stderr, "qemu: could not load kernel '%s'\n",
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406 | 3475187d | bellard | kernel_filename); |
407 | f930d07e | blueswir1 | exit(1);
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408 | 3475187d | bellard | } |
409 | 3475187d | bellard | |
410 | 3475187d | bellard | /* load initrd */
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411 | 3475187d | bellard | if (initrd_filename) {
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412 | 3475187d | bellard | initrd_size = load_image(initrd_filename, phys_ram_base + INITRD_LOAD_ADDR); |
413 | 3475187d | bellard | if (initrd_size < 0) { |
414 | 5fafdf24 | ths | fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
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415 | 3475187d | bellard | initrd_filename); |
416 | 3475187d | bellard | exit(1);
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417 | 3475187d | bellard | } |
418 | 3475187d | bellard | } |
419 | 3475187d | bellard | if (initrd_size > 0) { |
420 | f930d07e | blueswir1 | for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) { |
421 | f930d07e | blueswir1 | if (ldl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i)
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422 | f930d07e | blueswir1 | == 0x48647253) { // HdrS |
423 | f930d07e | blueswir1 | stl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i + 16, INITRD_LOAD_ADDR);
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424 | f930d07e | blueswir1 | stl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i + 20, initrd_size);
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425 | f930d07e | blueswir1 | break;
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426 | f930d07e | blueswir1 | } |
427 | f930d07e | blueswir1 | } |
428 | 3475187d | bellard | } |
429 | 3475187d | bellard | } |
430 | 502a5395 | pbrook | pci_bus = pci_apb_init(APB_SPECIAL_BASE, APB_MEM_BASE, NULL);
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431 | 83469015 | bellard | isa_mem_base = VGA_BASE; |
432 | 75956cf0 | pbrook | pci_cirrus_vga_init(pci_bus, ds, phys_ram_base + ram_size, ram_size, vga_ram_size); |
433 | 83469015 | bellard | |
434 | 83469015 | bellard | for(i = 0; i < MAX_SERIAL_PORTS; i++) { |
435 | 83469015 | bellard | if (serial_hds[i]) {
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436 | d537cf6c | pbrook | serial_init(serial_io[i], NULL/*serial_irq[i]*/, serial_hds[i]); |
437 | 83469015 | bellard | } |
438 | 83469015 | bellard | } |
439 | 83469015 | bellard | |
440 | 83469015 | bellard | for(i = 0; i < MAX_PARALLEL_PORTS; i++) { |
441 | 83469015 | bellard | if (parallel_hds[i]) {
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442 | d537cf6c | pbrook | parallel_init(parallel_io[i], NULL/*parallel_irq[i]*/, parallel_hds[i]); |
443 | 83469015 | bellard | } |
444 | 83469015 | bellard | } |
445 | 83469015 | bellard | |
446 | 83469015 | bellard | for(i = 0; i < nb_nics; i++) { |
447 | a41b2ff2 | pbrook | if (!nd_table[i].model)
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448 | a41b2ff2 | pbrook | nd_table[i].model = "ne2k_pci";
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449 | f930d07e | blueswir1 | pci_nic_init(pci_bus, &nd_table[i], -1);
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450 | 83469015 | bellard | } |
451 | 83469015 | bellard | |
452 | f19e918d | blueswir1 | irq = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, 32); |
453 | f19e918d | blueswir1 | // XXX pci_cmd646_ide_init(pci_bus, bs_table, 1);
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454 | f19e918d | blueswir1 | pci_piix3_ide_init(pci_bus, bs_table, -1, irq);
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455 | d537cf6c | pbrook | /* FIXME: wire up interrupts. */
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456 | d537cf6c | pbrook | i8042_init(NULL/*1*/, NULL/*12*/, 0x60); |
457 | d537cf6c | pbrook | floppy_controller = fdctrl_init(NULL/*6*/, 2, 0, 0x3f0, fd_table); |
458 | d537cf6c | pbrook | nvram = m48t59_init(NULL/*8*/, 0, 0x0074, NVRAM_SIZE, 59); |
459 | 83469015 | bellard | sun4u_NVRAM_set_params(nvram, NVRAM_SIZE, "Sun4u", ram_size, boot_device,
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460 | 83469015 | bellard | KERNEL_LOAD_ADDR, kernel_size, |
461 | 83469015 | bellard | kernel_cmdline, |
462 | 83469015 | bellard | INITRD_LOAD_ADDR, initrd_size, |
463 | 83469015 | bellard | /* XXX: need an option to load a NVRAM image */
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464 | 83469015 | bellard | 0,
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465 | 83469015 | bellard | graphic_width, graphic_height, graphic_depth); |
466 | 83469015 | bellard | |
467 | 3475187d | bellard | } |
468 | 3475187d | bellard | |
469 | 3475187d | bellard | QEMUMachine sun4u_machine = { |
470 | 3475187d | bellard | "sun4u",
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471 | 3475187d | bellard | "Sun4u platform",
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472 | 3475187d | bellard | sun4u_init, |
473 | 3475187d | bellard | }; |