Revision a4bb6c3e target-ppc/translate.c

b/target-ppc/translate.c
4695 4695
#endif
4696 4696
}
4697 4697

  
4698
/* TLB management - PowerPC BookE implementation */
4698
/* TLB management - PowerPC 440 implementation */
4699 4699
/* tlbre */
4700
GEN_HANDLER(tlbre_booke, 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE)
4700
GEN_HANDLER(tlbre_440, 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE)
4701 4701
{
4702 4702
#if defined(CONFIG_USER_ONLY)
4703 4703
    RET_PRIVOPC(ctx);
......
4708 4708
    }
4709 4709
    switch (rB(ctx->opcode)) {
4710 4710
    case 0:
4711
        gen_op_load_gpr_T0(rA(ctx->opcode));
4712
        gen_op_booke_tlbre0();
4713
        gen_op_store_T0_gpr(rD(ctx->opcode));
4714
        break;
4715 4711
    case 1:
4716
        gen_op_load_gpr_T0(rA(ctx->opcode));
4717
        gen_op_booke_tlbre1();
4718
        gen_op_store_T0_gpr(rD(ctx->opcode));
4719
        break;
4720 4712
    case 2:
4721 4713
        gen_op_load_gpr_T0(rA(ctx->opcode));
4722
        gen_op_booke_tlbre2();
4714
        gen_op_440_tlbre(rB(ctx->opcode));
4723 4715
        gen_op_store_T0_gpr(rD(ctx->opcode));
4724 4716
        break;
4725 4717
    default:
......
4730 4722
}
4731 4723

  
4732 4724
/* tlbsx - tlbsx. */
4733
GEN_HANDLER(tlbsx_booke, 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE)
4725
GEN_HANDLER(tlbsx_440, 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE)
4734 4726
{
4735 4727
#if defined(CONFIG_USER_ONLY)
4736 4728
    RET_PRIVOPC(ctx);
......
4741 4733
    }
4742 4734
    gen_addr_reg_index(ctx);
4743 4735
    if (Rc(ctx->opcode))
4744
        gen_op_booke_tlbsx_();
4736
        gen_op_440_tlbsx_();
4745 4737
    else
4746
        gen_op_booke_tlbsx();
4738
        gen_op_440_tlbsx();
4747 4739
    gen_op_store_T0_gpr(rD(ctx->opcode));
4748 4740
#endif
4749 4741
}
4750 4742

  
4751 4743
/* tlbwe */
4752
GEN_HANDLER(tlbwe_booke, 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE)
4744
GEN_HANDLER(tlbwe_440, 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE)
4753 4745
{
4754 4746
#if defined(CONFIG_USER_ONLY)
4755 4747
    RET_PRIVOPC(ctx);
......
4760 4752
    }
4761 4753
    switch (rB(ctx->opcode)) {
4762 4754
    case 0:
4763
        gen_op_load_gpr_T0(rA(ctx->opcode));
4764
        gen_op_load_gpr_T1(rS(ctx->opcode));
4765
        gen_op_booke_tlbwe0();
4766
        break;
4767 4755
    case 1:
4768
        gen_op_load_gpr_T0(rA(ctx->opcode));
4769
        gen_op_load_gpr_T1(rS(ctx->opcode));
4770
        gen_op_booke_tlbwe1();
4771
        break;
4772 4756
    case 2:
4773 4757
        gen_op_load_gpr_T0(rA(ctx->opcode));
4774 4758
        gen_op_load_gpr_T1(rS(ctx->opcode));
4775
        gen_op_booke_tlbwe2();
4759
        gen_op_440_tlbwe(rB(ctx->opcode));
4776 4760
        break;
4777 4761
    default:
4778 4762
        RET_INVAL(ctx);

Also available in: Unified diff