root / hw / net / mipsnet.c @ a4dbb8bd
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#include "hw/hw.h" |
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#include "net/net.h" |
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#include "trace.h" |
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#include "hw/sysbus.h" |
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|
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/* MIPSnet register offsets */
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|
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#define MIPSNET_DEV_ID 0x00 |
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#define MIPSNET_BUSY 0x08 |
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#define MIPSNET_RX_DATA_COUNT 0x0c |
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#define MIPSNET_TX_DATA_COUNT 0x10 |
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#define MIPSNET_INT_CTL 0x14 |
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# define MIPSNET_INTCTL_TXDONE 0x00000001 |
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# define MIPSNET_INTCTL_RXDONE 0x00000002 |
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# define MIPSNET_INTCTL_TESTBIT 0x80000000 |
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#define MIPSNET_INTERRUPT_INFO 0x18 |
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#define MIPSNET_RX_DATA_BUFFER 0x1c |
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#define MIPSNET_TX_DATA_BUFFER 0x20 |
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|
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#define MAX_ETH_FRAME_SIZE 1514 |
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#define TYPE_MIPS_NET "mipsnet" |
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#define MIPS_NET(obj) OBJECT_CHECK(MIPSnetState, (obj), TYPE_MIPS_NET)
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typedef struct MIPSnetState { |
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SysBusDevice parent_obj; |
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|
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uint32_t busy; |
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uint32_t rx_count; |
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uint32_t rx_read; |
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uint32_t tx_count; |
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uint32_t tx_written; |
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uint32_t intctl; |
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uint8_t rx_buffer[MAX_ETH_FRAME_SIZE]; |
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uint8_t tx_buffer[MAX_ETH_FRAME_SIZE]; |
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MemoryRegion io; |
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qemu_irq irq; |
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NICState *nic; |
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NICConf conf; |
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} MIPSnetState; |
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|
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static void mipsnet_reset(MIPSnetState *s) |
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{ |
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s->busy = 1;
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s->rx_count = 0;
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s->rx_read = 0;
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s->tx_count = 0;
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s->tx_written = 0;
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s->intctl = 0;
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memset(s->rx_buffer, 0, MAX_ETH_FRAME_SIZE);
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memset(s->tx_buffer, 0, MAX_ETH_FRAME_SIZE);
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} |
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static void mipsnet_update_irq(MIPSnetState *s) |
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{ |
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int isr = !!s->intctl;
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trace_mipsnet_irq(isr, s->intctl); |
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qemu_set_irq(s->irq, isr); |
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} |
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static int mipsnet_buffer_full(MIPSnetState *s) |
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{ |
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if (s->rx_count >= MAX_ETH_FRAME_SIZE)
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return 1; |
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return 0; |
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} |
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static int mipsnet_can_receive(NetClientState *nc) |
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{ |
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MIPSnetState *s = qemu_get_nic_opaque(nc); |
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if (s->busy)
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return 0; |
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return !mipsnet_buffer_full(s);
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} |
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static ssize_t mipsnet_receive(NetClientState *nc, const uint8_t *buf, size_t size) |
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{ |
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MIPSnetState *s = qemu_get_nic_opaque(nc); |
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|
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trace_mipsnet_receive(size); |
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if (!mipsnet_can_receive(nc))
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return -1; |
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s->busy = 1;
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/* Just accept everything. */
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/* Write packet data. */
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memcpy(s->rx_buffer, buf, size); |
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s->rx_count = size; |
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s->rx_read = 0;
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/* Now we can signal we have received something. */
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s->intctl |= MIPSNET_INTCTL_RXDONE; |
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mipsnet_update_irq(s); |
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return size;
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} |
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static uint64_t mipsnet_ioport_read(void *opaque, hwaddr addr, |
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unsigned int size) |
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{ |
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MIPSnetState *s = opaque; |
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int ret = 0; |
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addr &= 0x3f;
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switch (addr) {
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case MIPSNET_DEV_ID:
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ret = be32_to_cpu(0x4d495053); /* MIPS */ |
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break;
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case MIPSNET_DEV_ID + 4: |
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ret = be32_to_cpu(0x4e455430); /* NET0 */ |
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break;
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case MIPSNET_BUSY:
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ret = s->busy; |
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break;
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case MIPSNET_RX_DATA_COUNT:
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ret = s->rx_count; |
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break;
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case MIPSNET_TX_DATA_COUNT:
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ret = s->tx_count; |
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break;
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case MIPSNET_INT_CTL:
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ret = s->intctl; |
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s->intctl &= ~MIPSNET_INTCTL_TESTBIT; |
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break;
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case MIPSNET_INTERRUPT_INFO:
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/* XXX: This seems to be a per-VPE interrupt number. */
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ret = 0;
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break;
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case MIPSNET_RX_DATA_BUFFER:
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if (s->rx_count) {
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s->rx_count--; |
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ret = s->rx_buffer[s->rx_read++]; |
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} |
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break;
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/* Reads as zero. */
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case MIPSNET_TX_DATA_BUFFER:
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default:
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break;
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} |
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trace_mipsnet_read(addr, ret); |
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return ret;
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} |
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static void mipsnet_ioport_write(void *opaque, hwaddr addr, |
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uint64_t val, unsigned int size) |
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{ |
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MIPSnetState *s = opaque; |
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addr &= 0x3f;
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trace_mipsnet_write(addr, val); |
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switch (addr) {
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case MIPSNET_TX_DATA_COUNT:
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s->tx_count = (val <= MAX_ETH_FRAME_SIZE) ? val : 0;
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s->tx_written = 0;
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break;
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case MIPSNET_INT_CTL:
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if (val & MIPSNET_INTCTL_TXDONE) {
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s->intctl &= ~MIPSNET_INTCTL_TXDONE; |
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} else if (val & MIPSNET_INTCTL_RXDONE) { |
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s->intctl &= ~MIPSNET_INTCTL_RXDONE; |
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} else if (val & MIPSNET_INTCTL_TESTBIT) { |
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mipsnet_reset(s); |
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s->intctl |= MIPSNET_INTCTL_TESTBIT; |
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} else if (!val) { |
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/* ACK testbit interrupt, flag was cleared on read. */
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} |
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s->busy = !!s->intctl; |
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mipsnet_update_irq(s); |
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break;
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case MIPSNET_TX_DATA_BUFFER:
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s->tx_buffer[s->tx_written++] = val; |
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if (s->tx_written == s->tx_count) {
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/* Send buffer. */
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trace_mipsnet_send(s->tx_count); |
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qemu_send_packet(qemu_get_queue(s->nic), s->tx_buffer, s->tx_count); |
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s->tx_count = s->tx_written = 0;
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s->intctl |= MIPSNET_INTCTL_TXDONE; |
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s->busy = 1;
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mipsnet_update_irq(s); |
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} |
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break;
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/* Read-only registers */
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case MIPSNET_DEV_ID:
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case MIPSNET_BUSY:
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case MIPSNET_RX_DATA_COUNT:
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case MIPSNET_INTERRUPT_INFO:
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case MIPSNET_RX_DATA_BUFFER:
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default:
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break;
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} |
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} |
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static const VMStateDescription vmstate_mipsnet = { |
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.name = "mipsnet",
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.version_id = 0,
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.minimum_version_id = 0,
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.minimum_version_id_old = 0,
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.fields = (VMStateField[]) { |
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VMSTATE_UINT32(busy, MIPSnetState), |
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VMSTATE_UINT32(rx_count, MIPSnetState), |
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VMSTATE_UINT32(rx_read, MIPSnetState), |
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VMSTATE_UINT32(tx_count, MIPSnetState), |
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VMSTATE_UINT32(tx_written, MIPSnetState), |
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VMSTATE_UINT32(intctl, MIPSnetState), |
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VMSTATE_BUFFER(rx_buffer, MIPSnetState), |
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VMSTATE_BUFFER(tx_buffer, MIPSnetState), |
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VMSTATE_END_OF_LIST() |
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} |
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}; |
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static void mipsnet_cleanup(NetClientState *nc) |
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{ |
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MIPSnetState *s = qemu_get_nic_opaque(nc); |
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s->nic = NULL;
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} |
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static NetClientInfo net_mipsnet_info = {
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.type = NET_CLIENT_OPTIONS_KIND_NIC, |
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.size = sizeof(NICState),
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.can_receive = mipsnet_can_receive, |
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.receive = mipsnet_receive, |
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.cleanup = mipsnet_cleanup, |
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}; |
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static const MemoryRegionOps mipsnet_ioport_ops = { |
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.read = mipsnet_ioport_read, |
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.write = mipsnet_ioport_write, |
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.impl.min_access_size = 1,
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.impl.max_access_size = 4,
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}; |
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static int mipsnet_sysbus_init(SysBusDevice *sbd) |
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{ |
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DeviceState *dev = DEVICE(sbd); |
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MIPSnetState *s = MIPS_NET(dev); |
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memory_region_init_io(&s->io, OBJECT(dev), &mipsnet_ioport_ops, s, |
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"mipsnet-io", 36); |
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sysbus_init_mmio(sbd, &s->io); |
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sysbus_init_irq(sbd, &s->irq); |
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s->nic = qemu_new_nic(&net_mipsnet_info, &s->conf, |
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object_get_typename(OBJECT(dev)), dev->id, s); |
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qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a); |
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|
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return 0; |
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} |
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static void mipsnet_sysbus_reset(DeviceState *dev) |
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{ |
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MIPSnetState *s = MIPS_NET(dev); |
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mipsnet_reset(s); |
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} |
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|
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static Property mipsnet_properties[] = {
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DEFINE_NIC_PROPERTIES(MIPSnetState, conf), |
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DEFINE_PROP_END_OF_LIST(), |
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}; |
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|
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static void mipsnet_class_init(ObjectClass *klass, void *data) |
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{ |
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DeviceClass *dc = DEVICE_CLASS(klass); |
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SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); |
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k->init = mipsnet_sysbus_init; |
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set_bit(DEVICE_CATEGORY_NETWORK, dc->categories); |
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dc->desc = "MIPS Simulator network device";
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dc->reset = mipsnet_sysbus_reset; |
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dc->vmsd = &vmstate_mipsnet; |
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dc->props = mipsnet_properties; |
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} |
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|
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static const TypeInfo mipsnet_info = { |
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.name = TYPE_MIPS_NET, |
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.parent = TYPE_SYS_BUS_DEVICE, |
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.instance_size = sizeof(MIPSnetState),
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.class_init = mipsnet_class_init, |
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}; |
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|
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static void mipsnet_register_types(void) |
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{ |
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type_register_static(&mipsnet_info); |
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} |
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|
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type_init(mipsnet_register_types) |