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1 | 80cabfad | bellard | /*
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2 | 80cabfad | bellard | * QEMU NE2000 emulation
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3 | 80cabfad | bellard | *
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4 | 80cabfad | bellard | * Copyright (c) 2003-2004 Fabrice Bellard
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5 | 80cabfad | bellard | *
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6 | 80cabfad | bellard | * Permission is hereby granted, free of charge, to any person obtaining a copy
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7 | 80cabfad | bellard | * of this software and associated documentation files (the "Software"), to deal
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8 | 80cabfad | bellard | * in the Software without restriction, including without limitation the rights
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9 | 80cabfad | bellard | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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10 | 80cabfad | bellard | * copies of the Software, and to permit persons to whom the Software is
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11 | 80cabfad | bellard | * furnished to do so, subject to the following conditions:
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12 | 80cabfad | bellard | *
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13 | 80cabfad | bellard | * The above copyright notice and this permission notice shall be included in
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14 | 80cabfad | bellard | * all copies or substantial portions of the Software.
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15 | 80cabfad | bellard | *
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16 | 80cabfad | bellard | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 | 80cabfad | bellard | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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18 | 80cabfad | bellard | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 | 80cabfad | bellard | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 | 80cabfad | bellard | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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21 | 80cabfad | bellard | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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22 | 80cabfad | bellard | * THE SOFTWARE.
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23 | 80cabfad | bellard | */
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24 | 80cabfad | bellard | #include "vl.h" |
25 | 80cabfad | bellard | |
26 | 80cabfad | bellard | /* debug NE2000 card */
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27 | 80cabfad | bellard | //#define DEBUG_NE2000
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28 | 80cabfad | bellard | |
29 | b41a2cd1 | bellard | #define MAX_ETH_FRAME_SIZE 1514 |
30 | 80cabfad | bellard | |
31 | 80cabfad | bellard | #define E8390_CMD 0x00 /* The command register (for all pages) */ |
32 | 80cabfad | bellard | /* Page 0 register offsets. */
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33 | 80cabfad | bellard | #define EN0_CLDALO 0x01 /* Low byte of current local dma addr RD */ |
34 | 80cabfad | bellard | #define EN0_STARTPG 0x01 /* Starting page of ring bfr WR */ |
35 | 80cabfad | bellard | #define EN0_CLDAHI 0x02 /* High byte of current local dma addr RD */ |
36 | 80cabfad | bellard | #define EN0_STOPPG 0x02 /* Ending page +1 of ring bfr WR */ |
37 | 80cabfad | bellard | #define EN0_BOUNDARY 0x03 /* Boundary page of ring bfr RD WR */ |
38 | 80cabfad | bellard | #define EN0_TSR 0x04 /* Transmit status reg RD */ |
39 | 80cabfad | bellard | #define EN0_TPSR 0x04 /* Transmit starting page WR */ |
40 | 80cabfad | bellard | #define EN0_NCR 0x05 /* Number of collision reg RD */ |
41 | 80cabfad | bellard | #define EN0_TCNTLO 0x05 /* Low byte of tx byte count WR */ |
42 | 80cabfad | bellard | #define EN0_FIFO 0x06 /* FIFO RD */ |
43 | 80cabfad | bellard | #define EN0_TCNTHI 0x06 /* High byte of tx byte count WR */ |
44 | 80cabfad | bellard | #define EN0_ISR 0x07 /* Interrupt status reg RD WR */ |
45 | 80cabfad | bellard | #define EN0_CRDALO 0x08 /* low byte of current remote dma address RD */ |
46 | 80cabfad | bellard | #define EN0_RSARLO 0x08 /* Remote start address reg 0 */ |
47 | 80cabfad | bellard | #define EN0_CRDAHI 0x09 /* high byte, current remote dma address RD */ |
48 | 80cabfad | bellard | #define EN0_RSARHI 0x09 /* Remote start address reg 1 */ |
49 | 80cabfad | bellard | #define EN0_RCNTLO 0x0a /* Remote byte count reg WR */ |
50 | 80cabfad | bellard | #define EN0_RCNTHI 0x0b /* Remote byte count reg WR */ |
51 | 80cabfad | bellard | #define EN0_RSR 0x0c /* rx status reg RD */ |
52 | 80cabfad | bellard | #define EN0_RXCR 0x0c /* RX configuration reg WR */ |
53 | 80cabfad | bellard | #define EN0_TXCR 0x0d /* TX configuration reg WR */ |
54 | 80cabfad | bellard | #define EN0_COUNTER0 0x0d /* Rcv alignment error counter RD */ |
55 | 80cabfad | bellard | #define EN0_DCFG 0x0e /* Data configuration reg WR */ |
56 | 80cabfad | bellard | #define EN0_COUNTER1 0x0e /* Rcv CRC error counter RD */ |
57 | 80cabfad | bellard | #define EN0_IMR 0x0f /* Interrupt mask reg WR */ |
58 | 80cabfad | bellard | #define EN0_COUNTER2 0x0f /* Rcv missed frame error counter RD */ |
59 | 80cabfad | bellard | |
60 | 80cabfad | bellard | #define EN1_PHYS 0x11 |
61 | 80cabfad | bellard | #define EN1_CURPAG 0x17 |
62 | 80cabfad | bellard | #define EN1_MULT 0x18 |
63 | 80cabfad | bellard | |
64 | 80cabfad | bellard | /* Register accessed at EN_CMD, the 8390 base addr. */
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65 | 80cabfad | bellard | #define E8390_STOP 0x01 /* Stop and reset the chip */ |
66 | 80cabfad | bellard | #define E8390_START 0x02 /* Start the chip, clear reset */ |
67 | 80cabfad | bellard | #define E8390_TRANS 0x04 /* Transmit a frame */ |
68 | 80cabfad | bellard | #define E8390_RREAD 0x08 /* Remote read */ |
69 | 80cabfad | bellard | #define E8390_RWRITE 0x10 /* Remote write */ |
70 | 80cabfad | bellard | #define E8390_NODMA 0x20 /* Remote DMA */ |
71 | 80cabfad | bellard | #define E8390_PAGE0 0x00 /* Select page chip registers */ |
72 | 80cabfad | bellard | #define E8390_PAGE1 0x40 /* using the two high-order bits */ |
73 | 80cabfad | bellard | #define E8390_PAGE2 0x80 /* Page 3 is invalid. */ |
74 | 80cabfad | bellard | |
75 | 80cabfad | bellard | /* Bits in EN0_ISR - Interrupt status register */
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76 | 80cabfad | bellard | #define ENISR_RX 0x01 /* Receiver, no error */ |
77 | 80cabfad | bellard | #define ENISR_TX 0x02 /* Transmitter, no error */ |
78 | 80cabfad | bellard | #define ENISR_RX_ERR 0x04 /* Receiver, with error */ |
79 | 80cabfad | bellard | #define ENISR_TX_ERR 0x08 /* Transmitter, with error */ |
80 | 80cabfad | bellard | #define ENISR_OVER 0x10 /* Receiver overwrote the ring */ |
81 | 80cabfad | bellard | #define ENISR_COUNTERS 0x20 /* Counters need emptying */ |
82 | 80cabfad | bellard | #define ENISR_RDC 0x40 /* remote dma complete */ |
83 | 80cabfad | bellard | #define ENISR_RESET 0x80 /* Reset completed */ |
84 | 80cabfad | bellard | #define ENISR_ALL 0x3f /* Interrupts we will enable */ |
85 | 80cabfad | bellard | |
86 | 80cabfad | bellard | /* Bits in received packet status byte and EN0_RSR*/
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87 | 80cabfad | bellard | #define ENRSR_RXOK 0x01 /* Received a good packet */ |
88 | 80cabfad | bellard | #define ENRSR_CRC 0x02 /* CRC error */ |
89 | 80cabfad | bellard | #define ENRSR_FAE 0x04 /* frame alignment error */ |
90 | 80cabfad | bellard | #define ENRSR_FO 0x08 /* FIFO overrun */ |
91 | 80cabfad | bellard | #define ENRSR_MPA 0x10 /* missed pkt */ |
92 | 80cabfad | bellard | #define ENRSR_PHY 0x20 /* physical/multicast address */ |
93 | 80cabfad | bellard | #define ENRSR_DIS 0x40 /* receiver disable. set in monitor mode */ |
94 | 80cabfad | bellard | #define ENRSR_DEF 0x80 /* deferring */ |
95 | 80cabfad | bellard | |
96 | 80cabfad | bellard | /* Transmitted packet status, EN0_TSR. */
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97 | 80cabfad | bellard | #define ENTSR_PTX 0x01 /* Packet transmitted without error */ |
98 | 80cabfad | bellard | #define ENTSR_ND 0x02 /* The transmit wasn't deferred. */ |
99 | 80cabfad | bellard | #define ENTSR_COL 0x04 /* The transmit collided at least once. */ |
100 | 80cabfad | bellard | #define ENTSR_ABT 0x08 /* The transmit collided 16 times, and was deferred. */ |
101 | 80cabfad | bellard | #define ENTSR_CRS 0x10 /* The carrier sense was lost. */ |
102 | 80cabfad | bellard | #define ENTSR_FU 0x20 /* A "FIFO underrun" occurred during transmit. */ |
103 | 80cabfad | bellard | #define ENTSR_CDH 0x40 /* The collision detect "heartbeat" signal was lost. */ |
104 | 80cabfad | bellard | #define ENTSR_OWC 0x80 /* There was an out-of-window collision. */ |
105 | 80cabfad | bellard | |
106 | 80cabfad | bellard | #define NE2000_MEM_SIZE 32768 |
107 | 80cabfad | bellard | |
108 | 80cabfad | bellard | typedef struct NE2000State { |
109 | 80cabfad | bellard | uint8_t cmd; |
110 | 80cabfad | bellard | uint32_t start; |
111 | 80cabfad | bellard | uint32_t stop; |
112 | 80cabfad | bellard | uint8_t boundary; |
113 | 80cabfad | bellard | uint8_t tsr; |
114 | 80cabfad | bellard | uint8_t tpsr; |
115 | 80cabfad | bellard | uint16_t tcnt; |
116 | 80cabfad | bellard | uint16_t rcnt; |
117 | 80cabfad | bellard | uint32_t rsar; |
118 | 80cabfad | bellard | uint8_t isr; |
119 | 80cabfad | bellard | uint8_t dcfg; |
120 | 80cabfad | bellard | uint8_t imr; |
121 | 80cabfad | bellard | uint8_t phys[6]; /* mac address */ |
122 | 80cabfad | bellard | uint8_t curpag; |
123 | 80cabfad | bellard | uint8_t mult[8]; /* multicast mask array */ |
124 | 80cabfad | bellard | int irq;
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125 | b41a2cd1 | bellard | NetDriverState *nd; |
126 | 80cabfad | bellard | uint8_t mem[NE2000_MEM_SIZE]; |
127 | 80cabfad | bellard | } NE2000State; |
128 | 80cabfad | bellard | |
129 | 80cabfad | bellard | static void ne2000_reset(NE2000State *s) |
130 | 80cabfad | bellard | { |
131 | 80cabfad | bellard | int i;
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132 | 80cabfad | bellard | |
133 | 80cabfad | bellard | s->isr = ENISR_RESET; |
134 | b41a2cd1 | bellard | memcpy(s->mem, s->nd->macaddr, 6);
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135 | 80cabfad | bellard | s->mem[14] = 0x57; |
136 | 80cabfad | bellard | s->mem[15] = 0x57; |
137 | 80cabfad | bellard | |
138 | 80cabfad | bellard | /* duplicate prom data */
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139 | 80cabfad | bellard | for(i = 15;i >= 0; i--) { |
140 | 80cabfad | bellard | s->mem[2 * i] = s->mem[i];
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141 | 80cabfad | bellard | s->mem[2 * i + 1] = s->mem[i]; |
142 | 80cabfad | bellard | } |
143 | 80cabfad | bellard | } |
144 | 80cabfad | bellard | |
145 | 80cabfad | bellard | static void ne2000_update_irq(NE2000State *s) |
146 | 80cabfad | bellard | { |
147 | 80cabfad | bellard | int isr;
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148 | 80cabfad | bellard | isr = s->isr & s->imr; |
149 | a541f297 | bellard | #if defined(DEBUG_NE2000)
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150 | a541f297 | bellard | printf("NE2000: Set IRQ line %d to %d (%02x %02x)\n",
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151 | a541f297 | bellard | s->irq, isr ? 1 : 0, s->isr, s->imr); |
152 | a541f297 | bellard | #endif
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153 | 80cabfad | bellard | if (isr)
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154 | 80cabfad | bellard | pic_set_irq(s->irq, 1);
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155 | 80cabfad | bellard | else
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156 | 80cabfad | bellard | pic_set_irq(s->irq, 0);
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157 | 80cabfad | bellard | } |
158 | 80cabfad | bellard | |
159 | b41a2cd1 | bellard | /* return the max buffer size if the NE2000 can receive more data */
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160 | b41a2cd1 | bellard | static int ne2000_can_receive(void *opaque) |
161 | 80cabfad | bellard | { |
162 | b41a2cd1 | bellard | NE2000State *s = opaque; |
163 | 80cabfad | bellard | int avail, index, boundary;
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164 | 80cabfad | bellard | |
165 | 80cabfad | bellard | if (s->cmd & E8390_STOP)
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166 | 80cabfad | bellard | return 0; |
167 | 80cabfad | bellard | index = s->curpag << 8;
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168 | 80cabfad | bellard | boundary = s->boundary << 8;
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169 | 80cabfad | bellard | if (index < boundary)
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170 | 80cabfad | bellard | avail = boundary - index; |
171 | 80cabfad | bellard | else
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172 | 80cabfad | bellard | avail = (s->stop - s->start) - (index - boundary); |
173 | 80cabfad | bellard | if (avail < (MAX_ETH_FRAME_SIZE + 4)) |
174 | 80cabfad | bellard | return 0; |
175 | b41a2cd1 | bellard | return MAX_ETH_FRAME_SIZE;
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176 | 80cabfad | bellard | } |
177 | 80cabfad | bellard | |
178 | b41a2cd1 | bellard | #define MIN_BUF_SIZE 60 |
179 | b41a2cd1 | bellard | |
180 | b41a2cd1 | bellard | static void ne2000_receive(void *opaque, const uint8_t *buf, int size) |
181 | 80cabfad | bellard | { |
182 | b41a2cd1 | bellard | NE2000State *s = opaque; |
183 | 80cabfad | bellard | uint8_t *p; |
184 | 80cabfad | bellard | int total_len, next, avail, len, index;
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185 | b41a2cd1 | bellard | uint8_t buf1[60];
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186 | b41a2cd1 | bellard | |
187 | 80cabfad | bellard | #if defined(DEBUG_NE2000)
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188 | 80cabfad | bellard | printf("NE2000: received len=%d\n", size);
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189 | 80cabfad | bellard | #endif
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190 | 80cabfad | bellard | |
191 | b41a2cd1 | bellard | /* if too small buffer, then expand it */
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192 | b41a2cd1 | bellard | if (size < MIN_BUF_SIZE) {
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193 | b41a2cd1 | bellard | memcpy(buf1, buf, size); |
194 | b41a2cd1 | bellard | memset(buf1 + size, 0, MIN_BUF_SIZE - size);
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195 | b41a2cd1 | bellard | buf = buf1; |
196 | b41a2cd1 | bellard | size = MIN_BUF_SIZE; |
197 | b41a2cd1 | bellard | } |
198 | b41a2cd1 | bellard | |
199 | 80cabfad | bellard | index = s->curpag << 8;
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200 | 80cabfad | bellard | /* 4 bytes for header */
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201 | 80cabfad | bellard | total_len = size + 4;
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202 | 80cabfad | bellard | /* address for next packet (4 bytes for CRC) */
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203 | 80cabfad | bellard | next = index + ((total_len + 4 + 255) & ~0xff); |
204 | 80cabfad | bellard | if (next >= s->stop)
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205 | 80cabfad | bellard | next -= (s->stop - s->start); |
206 | 80cabfad | bellard | /* prepare packet header */
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207 | 80cabfad | bellard | p = s->mem + index; |
208 | 80cabfad | bellard | p[0] = ENRSR_RXOK; /* receive status */ |
209 | 80cabfad | bellard | p[1] = next >> 8; |
210 | 80cabfad | bellard | p[2] = total_len;
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211 | 80cabfad | bellard | p[3] = total_len >> 8; |
212 | 80cabfad | bellard | index += 4;
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213 | 80cabfad | bellard | |
214 | 80cabfad | bellard | /* write packet data */
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215 | 80cabfad | bellard | while (size > 0) { |
216 | 80cabfad | bellard | avail = s->stop - index; |
217 | 80cabfad | bellard | len = size; |
218 | 80cabfad | bellard | if (len > avail)
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219 | 80cabfad | bellard | len = avail; |
220 | 80cabfad | bellard | memcpy(s->mem + index, buf, len); |
221 | 80cabfad | bellard | buf += len; |
222 | 80cabfad | bellard | index += len; |
223 | 80cabfad | bellard | if (index == s->stop)
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224 | 80cabfad | bellard | index = s->start; |
225 | 80cabfad | bellard | size -= len; |
226 | 80cabfad | bellard | } |
227 | 80cabfad | bellard | s->curpag = next >> 8;
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228 | 80cabfad | bellard | |
229 | 80cabfad | bellard | /* now we can signal we have receive something */
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230 | 80cabfad | bellard | s->isr |= ENISR_RX; |
231 | 80cabfad | bellard | ne2000_update_irq(s); |
232 | 80cabfad | bellard | } |
233 | 80cabfad | bellard | |
234 | b41a2cd1 | bellard | static void ne2000_ioport_write(void *opaque, uint32_t addr, uint32_t val) |
235 | 80cabfad | bellard | { |
236 | b41a2cd1 | bellard | NE2000State *s = opaque; |
237 | 80cabfad | bellard | int offset, page;
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238 | 80cabfad | bellard | |
239 | 80cabfad | bellard | addr &= 0xf;
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240 | 80cabfad | bellard | #ifdef DEBUG_NE2000
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241 | 80cabfad | bellard | printf("NE2000: write addr=0x%x val=0x%02x\n", addr, val);
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242 | 80cabfad | bellard | #endif
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243 | 80cabfad | bellard | if (addr == E8390_CMD) {
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244 | 80cabfad | bellard | /* control register */
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245 | 80cabfad | bellard | s->cmd = val; |
246 | 80cabfad | bellard | if (val & E8390_START) {
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247 | 80cabfad | bellard | /* test specific case: zero length transfert */
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248 | 80cabfad | bellard | if ((val & (E8390_RREAD | E8390_RWRITE)) &&
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249 | 80cabfad | bellard | s->rcnt == 0) {
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250 | 80cabfad | bellard | s->isr |= ENISR_RDC; |
251 | 80cabfad | bellard | ne2000_update_irq(s); |
252 | 80cabfad | bellard | } |
253 | 80cabfad | bellard | if (val & E8390_TRANS) {
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254 | b41a2cd1 | bellard | net_send_packet(s->nd, s->mem + (s->tpsr << 8), s->tcnt);
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255 | 80cabfad | bellard | /* signal end of transfert */
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256 | 80cabfad | bellard | s->tsr = ENTSR_PTX; |
257 | 80cabfad | bellard | s->isr |= ENISR_TX; |
258 | 80cabfad | bellard | ne2000_update_irq(s); |
259 | 80cabfad | bellard | } |
260 | 80cabfad | bellard | } |
261 | 80cabfad | bellard | } else {
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262 | 80cabfad | bellard | page = s->cmd >> 6;
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263 | 80cabfad | bellard | offset = addr | (page << 4);
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264 | 80cabfad | bellard | switch(offset) {
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265 | 80cabfad | bellard | case EN0_STARTPG:
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266 | 80cabfad | bellard | s->start = val << 8;
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267 | 80cabfad | bellard | break;
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268 | 80cabfad | bellard | case EN0_STOPPG:
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269 | 80cabfad | bellard | s->stop = val << 8;
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270 | 80cabfad | bellard | break;
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271 | 80cabfad | bellard | case EN0_BOUNDARY:
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272 | 80cabfad | bellard | s->boundary = val; |
273 | 80cabfad | bellard | break;
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274 | 80cabfad | bellard | case EN0_IMR:
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275 | 80cabfad | bellard | s->imr = val; |
276 | 80cabfad | bellard | ne2000_update_irq(s); |
277 | 80cabfad | bellard | break;
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278 | 80cabfad | bellard | case EN0_TPSR:
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279 | 80cabfad | bellard | s->tpsr = val; |
280 | 80cabfad | bellard | break;
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281 | 80cabfad | bellard | case EN0_TCNTLO:
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282 | 80cabfad | bellard | s->tcnt = (s->tcnt & 0xff00) | val;
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283 | 80cabfad | bellard | break;
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284 | 80cabfad | bellard | case EN0_TCNTHI:
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285 | 80cabfad | bellard | s->tcnt = (s->tcnt & 0x00ff) | (val << 8); |
286 | 80cabfad | bellard | break;
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287 | 80cabfad | bellard | case EN0_RSARLO:
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288 | 80cabfad | bellard | s->rsar = (s->rsar & 0xff00) | val;
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289 | 80cabfad | bellard | break;
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290 | 80cabfad | bellard | case EN0_RSARHI:
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291 | 80cabfad | bellard | s->rsar = (s->rsar & 0x00ff) | (val << 8); |
292 | 80cabfad | bellard | break;
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293 | 80cabfad | bellard | case EN0_RCNTLO:
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294 | 80cabfad | bellard | s->rcnt = (s->rcnt & 0xff00) | val;
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295 | 80cabfad | bellard | break;
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296 | 80cabfad | bellard | case EN0_RCNTHI:
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297 | 80cabfad | bellard | s->rcnt = (s->rcnt & 0x00ff) | (val << 8); |
298 | 80cabfad | bellard | break;
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299 | 80cabfad | bellard | case EN0_DCFG:
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300 | 80cabfad | bellard | s->dcfg = val; |
301 | 80cabfad | bellard | break;
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302 | 80cabfad | bellard | case EN0_ISR:
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303 | 80cabfad | bellard | s->isr &= ~val; |
304 | 80cabfad | bellard | ne2000_update_irq(s); |
305 | 80cabfad | bellard | break;
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306 | 80cabfad | bellard | case EN1_PHYS ... EN1_PHYS + 5: |
307 | 80cabfad | bellard | s->phys[offset - EN1_PHYS] = val; |
308 | 80cabfad | bellard | break;
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309 | 80cabfad | bellard | case EN1_CURPAG:
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310 | 80cabfad | bellard | s->curpag = val; |
311 | 80cabfad | bellard | break;
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312 | 80cabfad | bellard | case EN1_MULT ... EN1_MULT + 7: |
313 | 80cabfad | bellard | s->mult[offset - EN1_MULT] = val; |
314 | 80cabfad | bellard | break;
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315 | 80cabfad | bellard | } |
316 | 80cabfad | bellard | } |
317 | 80cabfad | bellard | } |
318 | 80cabfad | bellard | |
319 | b41a2cd1 | bellard | static uint32_t ne2000_ioport_read(void *opaque, uint32_t addr) |
320 | 80cabfad | bellard | { |
321 | b41a2cd1 | bellard | NE2000State *s = opaque; |
322 | 80cabfad | bellard | int offset, page, ret;
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323 | 80cabfad | bellard | |
324 | 80cabfad | bellard | addr &= 0xf;
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325 | 80cabfad | bellard | if (addr == E8390_CMD) {
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326 | 80cabfad | bellard | ret = s->cmd; |
327 | 80cabfad | bellard | } else {
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328 | 80cabfad | bellard | page = s->cmd >> 6;
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329 | 80cabfad | bellard | offset = addr | (page << 4);
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330 | 80cabfad | bellard | switch(offset) {
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331 | 80cabfad | bellard | case EN0_TSR:
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332 | 80cabfad | bellard | ret = s->tsr; |
333 | 80cabfad | bellard | break;
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334 | 80cabfad | bellard | case EN0_BOUNDARY:
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335 | 80cabfad | bellard | ret = s->boundary; |
336 | 80cabfad | bellard | break;
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337 | 80cabfad | bellard | case EN0_ISR:
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338 | 80cabfad | bellard | ret = s->isr; |
339 | 80cabfad | bellard | break;
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340 | 80cabfad | bellard | case EN1_PHYS ... EN1_PHYS + 5: |
341 | 80cabfad | bellard | ret = s->phys[offset - EN1_PHYS]; |
342 | 80cabfad | bellard | break;
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343 | 80cabfad | bellard | case EN1_CURPAG:
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344 | 80cabfad | bellard | ret = s->curpag; |
345 | 80cabfad | bellard | break;
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346 | 80cabfad | bellard | case EN1_MULT ... EN1_MULT + 7: |
347 | 80cabfad | bellard | ret = s->mult[offset - EN1_MULT]; |
348 | 80cabfad | bellard | break;
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349 | 80cabfad | bellard | default:
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350 | 80cabfad | bellard | ret = 0x00;
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351 | 80cabfad | bellard | break;
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352 | 80cabfad | bellard | } |
353 | 80cabfad | bellard | } |
354 | 80cabfad | bellard | #ifdef DEBUG_NE2000
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355 | 80cabfad | bellard | printf("NE2000: read addr=0x%x val=%02x\n", addr, ret);
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356 | 80cabfad | bellard | #endif
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357 | 80cabfad | bellard | return ret;
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358 | 80cabfad | bellard | } |
359 | 80cabfad | bellard | |
360 | b41a2cd1 | bellard | static void ne2000_asic_ioport_write(void *opaque, uint32_t addr, uint32_t val) |
361 | 80cabfad | bellard | { |
362 | b41a2cd1 | bellard | NE2000State *s = opaque; |
363 | 80cabfad | bellard | uint8_t *p; |
364 | 80cabfad | bellard | |
365 | 80cabfad | bellard | #ifdef DEBUG_NE2000
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366 | 80cabfad | bellard | printf("NE2000: asic write val=0x%04x\n", val);
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367 | 80cabfad | bellard | #endif
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368 | 80cabfad | bellard | p = s->mem + s->rsar; |
369 | 80cabfad | bellard | if (s->dcfg & 0x01) { |
370 | 80cabfad | bellard | /* 16 bit access */
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371 | 80cabfad | bellard | p[0] = val;
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372 | 80cabfad | bellard | p[1] = val >> 8; |
373 | 80cabfad | bellard | s->rsar += 2;
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374 | 80cabfad | bellard | s->rcnt -= 2;
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375 | 80cabfad | bellard | } else {
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376 | 80cabfad | bellard | /* 8 bit access */
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377 | 80cabfad | bellard | p[0] = val;
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378 | 80cabfad | bellard | s->rsar++; |
379 | 80cabfad | bellard | s->rcnt--; |
380 | 80cabfad | bellard | } |
381 | 80cabfad | bellard | /* wrap */
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382 | 80cabfad | bellard | if (s->rsar == s->stop)
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383 | 80cabfad | bellard | s->rsar = s->start; |
384 | 80cabfad | bellard | if (s->rcnt == 0) { |
385 | 80cabfad | bellard | /* signal end of transfert */
|
386 | 80cabfad | bellard | s->isr |= ENISR_RDC; |
387 | 80cabfad | bellard | ne2000_update_irq(s); |
388 | 80cabfad | bellard | } |
389 | 80cabfad | bellard | } |
390 | 80cabfad | bellard | |
391 | b41a2cd1 | bellard | static uint32_t ne2000_asic_ioport_read(void *opaque, uint32_t addr) |
392 | 80cabfad | bellard | { |
393 | b41a2cd1 | bellard | NE2000State *s = opaque; |
394 | 80cabfad | bellard | uint8_t *p; |
395 | 80cabfad | bellard | int ret;
|
396 | 80cabfad | bellard | |
397 | 80cabfad | bellard | p = s->mem + s->rsar; |
398 | 80cabfad | bellard | if (s->dcfg & 0x01) { |
399 | 80cabfad | bellard | /* 16 bit access */
|
400 | 80cabfad | bellard | ret = p[0] | (p[1] << 8); |
401 | 80cabfad | bellard | s->rsar += 2;
|
402 | 80cabfad | bellard | s->rcnt -= 2;
|
403 | 80cabfad | bellard | } else {
|
404 | 80cabfad | bellard | /* 8 bit access */
|
405 | 80cabfad | bellard | ret = p[0];
|
406 | 80cabfad | bellard | s->rsar++; |
407 | 80cabfad | bellard | s->rcnt--; |
408 | 80cabfad | bellard | } |
409 | 80cabfad | bellard | /* wrap */
|
410 | 80cabfad | bellard | if (s->rsar == s->stop)
|
411 | 80cabfad | bellard | s->rsar = s->start; |
412 | 80cabfad | bellard | if (s->rcnt == 0) { |
413 | 80cabfad | bellard | /* signal end of transfert */
|
414 | 80cabfad | bellard | s->isr |= ENISR_RDC; |
415 | 80cabfad | bellard | ne2000_update_irq(s); |
416 | 80cabfad | bellard | } |
417 | 80cabfad | bellard | #ifdef DEBUG_NE2000
|
418 | 80cabfad | bellard | printf("NE2000: asic read val=0x%04x\n", ret);
|
419 | 80cabfad | bellard | #endif
|
420 | 80cabfad | bellard | return ret;
|
421 | 80cabfad | bellard | } |
422 | 80cabfad | bellard | |
423 | b41a2cd1 | bellard | static void ne2000_reset_ioport_write(void *opaque, uint32_t addr, uint32_t val) |
424 | 80cabfad | bellard | { |
425 | 80cabfad | bellard | /* nothing to do (end of reset pulse) */
|
426 | 80cabfad | bellard | } |
427 | 80cabfad | bellard | |
428 | b41a2cd1 | bellard | static uint32_t ne2000_reset_ioport_read(void *opaque, uint32_t addr) |
429 | 80cabfad | bellard | { |
430 | b41a2cd1 | bellard | NE2000State *s = opaque; |
431 | 80cabfad | bellard | ne2000_reset(s); |
432 | 80cabfad | bellard | return 0; |
433 | 80cabfad | bellard | } |
434 | 80cabfad | bellard | |
435 | b41a2cd1 | bellard | void ne2000_init(int base, int irq, NetDriverState *nd) |
436 | 80cabfad | bellard | { |
437 | b41a2cd1 | bellard | NE2000State *s; |
438 | 80cabfad | bellard | |
439 | b41a2cd1 | bellard | s = qemu_mallocz(sizeof(NE2000State));
|
440 | b41a2cd1 | bellard | if (!s)
|
441 | b41a2cd1 | bellard | return;
|
442 | b41a2cd1 | bellard | |
443 | b41a2cd1 | bellard | register_ioport_write(base, 16, 1, ne2000_ioport_write, s); |
444 | b41a2cd1 | bellard | register_ioport_read(base, 16, 1, ne2000_ioport_read, s); |
445 | 80cabfad | bellard | |
446 | b41a2cd1 | bellard | register_ioport_write(base + 0x10, 1, 1, ne2000_asic_ioport_write, s); |
447 | b41a2cd1 | bellard | register_ioport_read(base + 0x10, 1, 1, ne2000_asic_ioport_read, s); |
448 | b41a2cd1 | bellard | register_ioport_write(base + 0x10, 2, 2, ne2000_asic_ioport_write, s); |
449 | b41a2cd1 | bellard | register_ioport_read(base + 0x10, 2, 2, ne2000_asic_ioport_read, s); |
450 | 80cabfad | bellard | |
451 | b41a2cd1 | bellard | register_ioport_write(base + 0x1f, 1, 1, ne2000_reset_ioport_write, s); |
452 | b41a2cd1 | bellard | register_ioport_read(base + 0x1f, 1, 1, ne2000_reset_ioport_read, s); |
453 | 80cabfad | bellard | s->irq = irq; |
454 | b41a2cd1 | bellard | s->nd = nd; |
455 | 80cabfad | bellard | |
456 | 80cabfad | bellard | ne2000_reset(s); |
457 | b41a2cd1 | bellard | |
458 | b0a21b53 | bellard | qemu_add_fd_read_handler(nd->fd, ne2000_can_receive, ne2000_receive, s); |
459 | 80cabfad | bellard | } |