root / target-mips / op_helper.c @ a569557f
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1 | 6af0bf9c | bellard | /*
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2 | 6af0bf9c | bellard | * MIPS emulation helpers for qemu.
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3 | 5fafdf24 | ths | *
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4 | 6af0bf9c | bellard | * Copyright (c) 2004-2005 Jocelyn Mayer
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5 | 6af0bf9c | bellard | *
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6 | 6af0bf9c | bellard | * This library is free software; you can redistribute it and/or
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7 | 6af0bf9c | bellard | * modify it under the terms of the GNU Lesser General Public
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8 | 6af0bf9c | bellard | * License as published by the Free Software Foundation; either
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9 | 6af0bf9c | bellard | * version 2 of the License, or (at your option) any later version.
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10 | 6af0bf9c | bellard | *
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11 | 6af0bf9c | bellard | * This library is distributed in the hope that it will be useful,
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12 | 6af0bf9c | bellard | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 | 6af0bf9c | bellard | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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14 | 6af0bf9c | bellard | * Lesser General Public License for more details.
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15 | 6af0bf9c | bellard | *
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16 | 6af0bf9c | bellard | * You should have received a copy of the GNU Lesser General Public
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17 | 6af0bf9c | bellard | * License along with this library; if not, write to the Free Software
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18 | 6af0bf9c | bellard | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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19 | 6af0bf9c | bellard | */
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20 | 2d0e944d | ths | #include <stdlib.h> |
21 | 6af0bf9c | bellard | #include "exec.h" |
22 | 6af0bf9c | bellard | |
23 | 05f778c8 | ths | #include "host-utils.h" |
24 | 05f778c8 | ths | |
25 | 6af0bf9c | bellard | /*****************************************************************************/
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26 | 6af0bf9c | bellard | /* Exceptions processing helpers */
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27 | 6af0bf9c | bellard | |
28 | 6af0bf9c | bellard | void do_raise_exception_err (uint32_t exception, int error_code) |
29 | 6af0bf9c | bellard | { |
30 | 6af0bf9c | bellard | #if 1 |
31 | 6af0bf9c | bellard | if (logfile && exception < 0x100) |
32 | 6af0bf9c | bellard | fprintf(logfile, "%s: %d %d\n", __func__, exception, error_code);
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33 | 6af0bf9c | bellard | #endif
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34 | 6af0bf9c | bellard | env->exception_index = exception; |
35 | 6af0bf9c | bellard | env->error_code = error_code; |
36 | 6af0bf9c | bellard | T0 = 0;
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37 | 6af0bf9c | bellard | cpu_loop_exit(); |
38 | 6af0bf9c | bellard | } |
39 | 6af0bf9c | bellard | |
40 | 6af0bf9c | bellard | void do_raise_exception (uint32_t exception)
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41 | 6af0bf9c | bellard | { |
42 | 6af0bf9c | bellard | do_raise_exception_err(exception, 0);
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43 | 6af0bf9c | bellard | } |
44 | 6af0bf9c | bellard | |
45 | 48d38ca5 | ths | void do_interrupt_restart (void) |
46 | 48d38ca5 | ths | { |
47 | 48d38ca5 | ths | if (!(env->CP0_Status & (1 << CP0St_EXL)) && |
48 | 48d38ca5 | ths | !(env->CP0_Status & (1 << CP0St_ERL)) &&
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49 | 48d38ca5 | ths | !(env->hflags & MIPS_HFLAG_DM) && |
50 | 48d38ca5 | ths | (env->CP0_Status & (1 << CP0St_IE)) &&
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51 | 48d38ca5 | ths | (env->CP0_Status & env->CP0_Cause & CP0Ca_IP_mask)) { |
52 | 48d38ca5 | ths | env->CP0_Cause &= ~(0x1f << CP0Ca_EC);
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53 | 48d38ca5 | ths | do_raise_exception(EXCP_EXT_INTERRUPT); |
54 | 48d38ca5 | ths | } |
55 | 48d38ca5 | ths | } |
56 | 48d38ca5 | ths | |
57 | 4ad40f36 | bellard | void do_restore_state (void *pc_ptr) |
58 | 4ad40f36 | bellard | { |
59 | a607922c | bellard | TranslationBlock *tb; |
60 | a607922c | bellard | unsigned long pc = (unsigned long) pc_ptr; |
61 | a607922c | bellard | |
62 | a607922c | bellard | tb = tb_find_pc (pc); |
63 | a607922c | bellard | if (tb) {
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64 | a607922c | bellard | cpu_restore_state (tb, env, pc, NULL);
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65 | a607922c | bellard | } |
66 | 4ad40f36 | bellard | } |
67 | 4ad40f36 | bellard | |
68 | 30898801 | ths | void do_clo (void) |
69 | 30898801 | ths | { |
70 | 30898801 | ths | T0 = clo32(T0); |
71 | 30898801 | ths | } |
72 | 30898801 | ths | |
73 | 30898801 | ths | void do_clz (void) |
74 | 30898801 | ths | { |
75 | 30898801 | ths | T0 = clz32(T0); |
76 | 30898801 | ths | } |
77 | 30898801 | ths | |
78 | d26bc211 | ths | #if defined(TARGET_MIPS64)
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79 | c570fd16 | ths | #if TARGET_LONG_BITS > HOST_LONG_BITS
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80 | c570fd16 | ths | /* Those might call libgcc functions. */
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81 | c570fd16 | ths | void do_dsll (void) |
82 | c570fd16 | ths | { |
83 | c570fd16 | ths | T0 = T0 << T1; |
84 | c570fd16 | ths | } |
85 | c570fd16 | ths | |
86 | c570fd16 | ths | void do_dsll32 (void) |
87 | c570fd16 | ths | { |
88 | c570fd16 | ths | T0 = T0 << (T1 + 32);
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89 | c570fd16 | ths | } |
90 | c570fd16 | ths | |
91 | c570fd16 | ths | void do_dsra (void) |
92 | c570fd16 | ths | { |
93 | c570fd16 | ths | T0 = (int64_t)T0 >> T1; |
94 | c570fd16 | ths | } |
95 | c570fd16 | ths | |
96 | c570fd16 | ths | void do_dsra32 (void) |
97 | c570fd16 | ths | { |
98 | c570fd16 | ths | T0 = (int64_t)T0 >> (T1 + 32);
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99 | c570fd16 | ths | } |
100 | c570fd16 | ths | |
101 | c570fd16 | ths | void do_dsrl (void) |
102 | c570fd16 | ths | { |
103 | c570fd16 | ths | T0 = T0 >> T1; |
104 | c570fd16 | ths | } |
105 | c570fd16 | ths | |
106 | c570fd16 | ths | void do_dsrl32 (void) |
107 | c570fd16 | ths | { |
108 | c570fd16 | ths | T0 = T0 >> (T1 + 32);
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109 | c570fd16 | ths | } |
110 | c570fd16 | ths | |
111 | c570fd16 | ths | void do_drotr (void) |
112 | c570fd16 | ths | { |
113 | c570fd16 | ths | target_ulong tmp; |
114 | c570fd16 | ths | |
115 | c570fd16 | ths | if (T1) {
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116 | c6d6dd7c | ths | tmp = T0 << (0x40 - T1);
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117 | c6d6dd7c | ths | T0 = (T0 >> T1) | tmp; |
118 | 5a63bcb2 | ths | } |
119 | c570fd16 | ths | } |
120 | c570fd16 | ths | |
121 | c570fd16 | ths | void do_drotr32 (void) |
122 | c570fd16 | ths | { |
123 | c570fd16 | ths | target_ulong tmp; |
124 | c570fd16 | ths | |
125 | c6d6dd7c | ths | tmp = T0 << (0x40 - (32 + T1)); |
126 | c6d6dd7c | ths | T0 = (T0 >> (32 + T1)) | tmp;
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127 | c570fd16 | ths | } |
128 | c570fd16 | ths | |
129 | c570fd16 | ths | void do_dsllv (void) |
130 | c570fd16 | ths | { |
131 | c570fd16 | ths | T0 = T1 << (T0 & 0x3F);
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132 | c570fd16 | ths | } |
133 | c570fd16 | ths | |
134 | c570fd16 | ths | void do_dsrav (void) |
135 | c570fd16 | ths | { |
136 | c570fd16 | ths | T0 = (int64_t)T1 >> (T0 & 0x3F);
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137 | c570fd16 | ths | } |
138 | c570fd16 | ths | |
139 | c570fd16 | ths | void do_dsrlv (void) |
140 | c570fd16 | ths | { |
141 | c570fd16 | ths | T0 = T1 >> (T0 & 0x3F);
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142 | c570fd16 | ths | } |
143 | c570fd16 | ths | |
144 | c570fd16 | ths | void do_drotrv (void) |
145 | c570fd16 | ths | { |
146 | c570fd16 | ths | target_ulong tmp; |
147 | c570fd16 | ths | |
148 | c570fd16 | ths | T0 &= 0x3F;
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149 | c570fd16 | ths | if (T0) {
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150 | c6d6dd7c | ths | tmp = T1 << (0x40 - T0);
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151 | c6d6dd7c | ths | T0 = (T1 >> T0) | tmp; |
152 | c570fd16 | ths | } else
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153 | c6d6dd7c | ths | T0 = T1; |
154 | c570fd16 | ths | } |
155 | 05f778c8 | ths | |
156 | 95af5ce5 | ths | #endif /* TARGET_LONG_BITS > HOST_LONG_BITS */ |
157 | 95af5ce5 | ths | |
158 | 05f778c8 | ths | void do_dclo (void) |
159 | 05f778c8 | ths | { |
160 | 05f778c8 | ths | T0 = clo64(T0); |
161 | 05f778c8 | ths | } |
162 | 05f778c8 | ths | |
163 | 05f778c8 | ths | void do_dclz (void) |
164 | 05f778c8 | ths | { |
165 | 05f778c8 | ths | T0 = clz64(T0); |
166 | 05f778c8 | ths | } |
167 | 05f778c8 | ths | |
168 | d26bc211 | ths | #endif /* TARGET_MIPS64 */ |
169 | c570fd16 | ths | |
170 | 6af0bf9c | bellard | /* 64 bits arithmetic for 32 bits hosts */
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171 | c570fd16 | ths | #if TARGET_LONG_BITS > HOST_LONG_BITS
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172 | aa343735 | ths | static always_inline uint64_t get_HILO (void) |
173 | 6af0bf9c | bellard | { |
174 | d0dc7dc3 | ths | return (env->HI[env->current_tc][0] << 32) | (uint32_t)env->LO[env->current_tc][0]; |
175 | 6af0bf9c | bellard | } |
176 | 6af0bf9c | bellard | |
177 | aa343735 | ths | static always_inline void set_HILO (uint64_t HILO) |
178 | 6af0bf9c | bellard | { |
179 | d0dc7dc3 | ths | env->LO[env->current_tc][0] = (int32_t)HILO;
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180 | d0dc7dc3 | ths | env->HI[env->current_tc][0] = (int32_t)(HILO >> 32); |
181 | 6af0bf9c | bellard | } |
182 | 6af0bf9c | bellard | |
183 | e9c71dd1 | ths | static always_inline void set_HIT0_LO (uint64_t HILO) |
184 | e9c71dd1 | ths | { |
185 | d0dc7dc3 | ths | env->LO[env->current_tc][0] = (int32_t)(HILO & 0xFFFFFFFF); |
186 | d0dc7dc3 | ths | T0 = env->HI[env->current_tc][0] = (int32_t)(HILO >> 32); |
187 | e9c71dd1 | ths | } |
188 | e9c71dd1 | ths | |
189 | e9c71dd1 | ths | static always_inline void set_HI_LOT0 (uint64_t HILO) |
190 | e9c71dd1 | ths | { |
191 | d0dc7dc3 | ths | T0 = env->LO[env->current_tc][0] = (int32_t)(HILO & 0xFFFFFFFF); |
192 | d0dc7dc3 | ths | env->HI[env->current_tc][0] = (int32_t)(HILO >> 32); |
193 | e9c71dd1 | ths | } |
194 | e9c71dd1 | ths | |
195 | 6af0bf9c | bellard | void do_mult (void) |
196 | 6af0bf9c | bellard | { |
197 | 4ad40f36 | bellard | set_HILO((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1); |
198 | 6af0bf9c | bellard | } |
199 | 6af0bf9c | bellard | |
200 | 6af0bf9c | bellard | void do_multu (void) |
201 | 6af0bf9c | bellard | { |
202 | c570fd16 | ths | set_HILO((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1); |
203 | 6af0bf9c | bellard | } |
204 | 6af0bf9c | bellard | |
205 | 6af0bf9c | bellard | void do_madd (void) |
206 | 6af0bf9c | bellard | { |
207 | 6af0bf9c | bellard | int64_t tmp; |
208 | 6af0bf9c | bellard | |
209 | 4ad40f36 | bellard | tmp = ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1); |
210 | 6af0bf9c | bellard | set_HILO((int64_t)get_HILO() + tmp); |
211 | 6af0bf9c | bellard | } |
212 | 6af0bf9c | bellard | |
213 | 6af0bf9c | bellard | void do_maddu (void) |
214 | 6af0bf9c | bellard | { |
215 | 6af0bf9c | bellard | uint64_t tmp; |
216 | 6af0bf9c | bellard | |
217 | c570fd16 | ths | tmp = ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1); |
218 | 6af0bf9c | bellard | set_HILO(get_HILO() + tmp); |
219 | 6af0bf9c | bellard | } |
220 | 6af0bf9c | bellard | |
221 | 6af0bf9c | bellard | void do_msub (void) |
222 | 6af0bf9c | bellard | { |
223 | 6af0bf9c | bellard | int64_t tmp; |
224 | 6af0bf9c | bellard | |
225 | 4ad40f36 | bellard | tmp = ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1); |
226 | 6af0bf9c | bellard | set_HILO((int64_t)get_HILO() - tmp); |
227 | 6af0bf9c | bellard | } |
228 | 6af0bf9c | bellard | |
229 | 6af0bf9c | bellard | void do_msubu (void) |
230 | 6af0bf9c | bellard | { |
231 | 6af0bf9c | bellard | uint64_t tmp; |
232 | 6af0bf9c | bellard | |
233 | c570fd16 | ths | tmp = ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1); |
234 | 6af0bf9c | bellard | set_HILO(get_HILO() - tmp); |
235 | 6af0bf9c | bellard | } |
236 | e9c71dd1 | ths | |
237 | e9c71dd1 | ths | /* Multiplication variants of the vr54xx. */
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238 | e9c71dd1 | ths | void do_muls (void) |
239 | e9c71dd1 | ths | { |
240 | e9c71dd1 | ths | set_HI_LOT0(0 - ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1));
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241 | e9c71dd1 | ths | } |
242 | e9c71dd1 | ths | |
243 | e9c71dd1 | ths | void do_mulsu (void) |
244 | e9c71dd1 | ths | { |
245 | e9c71dd1 | ths | set_HI_LOT0(0 - ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1));
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246 | e9c71dd1 | ths | } |
247 | e9c71dd1 | ths | |
248 | e9c71dd1 | ths | void do_macc (void) |
249 | e9c71dd1 | ths | { |
250 | e9c71dd1 | ths | set_HI_LOT0(((int64_t)get_HILO()) + ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1)); |
251 | e9c71dd1 | ths | } |
252 | e9c71dd1 | ths | |
253 | e9c71dd1 | ths | void do_macchi (void) |
254 | e9c71dd1 | ths | { |
255 | e9c71dd1 | ths | set_HIT0_LO(((int64_t)get_HILO()) + ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1)); |
256 | e9c71dd1 | ths | } |
257 | e9c71dd1 | ths | |
258 | e9c71dd1 | ths | void do_maccu (void) |
259 | e9c71dd1 | ths | { |
260 | e9c71dd1 | ths | set_HI_LOT0(((uint64_t)get_HILO()) + ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1)); |
261 | e9c71dd1 | ths | } |
262 | e9c71dd1 | ths | |
263 | e9c71dd1 | ths | void do_macchiu (void) |
264 | e9c71dd1 | ths | { |
265 | e9c71dd1 | ths | set_HIT0_LO(((uint64_t)get_HILO()) + ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1)); |
266 | e9c71dd1 | ths | } |
267 | e9c71dd1 | ths | |
268 | e9c71dd1 | ths | void do_msac (void) |
269 | e9c71dd1 | ths | { |
270 | e9c71dd1 | ths | set_HI_LOT0(((int64_t)get_HILO()) - ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1)); |
271 | e9c71dd1 | ths | } |
272 | e9c71dd1 | ths | |
273 | e9c71dd1 | ths | void do_msachi (void) |
274 | e9c71dd1 | ths | { |
275 | e9c71dd1 | ths | set_HIT0_LO(((int64_t)get_HILO()) - ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1)); |
276 | e9c71dd1 | ths | } |
277 | e9c71dd1 | ths | |
278 | e9c71dd1 | ths | void do_msacu (void) |
279 | e9c71dd1 | ths | { |
280 | e9c71dd1 | ths | set_HI_LOT0(((uint64_t)get_HILO()) - ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1)); |
281 | e9c71dd1 | ths | } |
282 | e9c71dd1 | ths | |
283 | e9c71dd1 | ths | void do_msachiu (void) |
284 | e9c71dd1 | ths | { |
285 | e9c71dd1 | ths | set_HIT0_LO(((uint64_t)get_HILO()) - ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1)); |
286 | e9c71dd1 | ths | } |
287 | e9c71dd1 | ths | |
288 | e9c71dd1 | ths | void do_mulhi (void) |
289 | e9c71dd1 | ths | { |
290 | e9c71dd1 | ths | set_HIT0_LO((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1); |
291 | e9c71dd1 | ths | } |
292 | e9c71dd1 | ths | |
293 | e9c71dd1 | ths | void do_mulhiu (void) |
294 | e9c71dd1 | ths | { |
295 | e9c71dd1 | ths | set_HIT0_LO((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1); |
296 | e9c71dd1 | ths | } |
297 | e9c71dd1 | ths | |
298 | e9c71dd1 | ths | void do_mulshi (void) |
299 | e9c71dd1 | ths | { |
300 | e9c71dd1 | ths | set_HIT0_LO(0 - ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1));
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301 | e9c71dd1 | ths | } |
302 | e9c71dd1 | ths | |
303 | e9c71dd1 | ths | void do_mulshiu (void) |
304 | e9c71dd1 | ths | { |
305 | e9c71dd1 | ths | set_HIT0_LO(0 - ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1));
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306 | e9c71dd1 | ths | } |
307 | e9c71dd1 | ths | #endif /* TARGET_LONG_BITS > HOST_LONG_BITS */ |
308 | 6af0bf9c | bellard | |
309 | 5fafdf24 | ths | #if defined(CONFIG_USER_ONLY)
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310 | 873eb012 | ths | void do_mfc0_random (void) |
311 | 048f6b4d | bellard | { |
312 | 873eb012 | ths | cpu_abort(env, "mfc0 random\n");
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313 | 048f6b4d | bellard | } |
314 | 873eb012 | ths | |
315 | 873eb012 | ths | void do_mfc0_count (void) |
316 | 873eb012 | ths | { |
317 | 873eb012 | ths | cpu_abort(env, "mfc0 count\n");
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318 | 873eb012 | ths | } |
319 | 873eb012 | ths | |
320 | 8c0fdd85 | ths | void cpu_mips_store_count(CPUState *env, uint32_t value)
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321 | 048f6b4d | bellard | { |
322 | 8c0fdd85 | ths | cpu_abort(env, "mtc0 count\n");
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323 | 8c0fdd85 | ths | } |
324 | 8c0fdd85 | ths | |
325 | 8c0fdd85 | ths | void cpu_mips_store_compare(CPUState *env, uint32_t value)
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326 | 8c0fdd85 | ths | { |
327 | 8c0fdd85 | ths | cpu_abort(env, "mtc0 compare\n");
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328 | 8c0fdd85 | ths | } |
329 | 8c0fdd85 | ths | |
330 | 42532189 | ths | void cpu_mips_start_count(CPUState *env)
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331 | 42532189 | ths | { |
332 | 42532189 | ths | cpu_abort(env, "start count\n");
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333 | 42532189 | ths | } |
334 | 42532189 | ths | |
335 | 42532189 | ths | void cpu_mips_stop_count(CPUState *env)
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336 | 42532189 | ths | { |
337 | 42532189 | ths | cpu_abort(env, "stop count\n");
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338 | 42532189 | ths | } |
339 | 42532189 | ths | |
340 | 4de9b249 | ths | void cpu_mips_update_irq(CPUState *env)
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341 | 4de9b249 | ths | { |
342 | 4de9b249 | ths | cpu_abort(env, "mtc0 status / mtc0 cause\n");
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343 | 4de9b249 | ths | } |
344 | 4de9b249 | ths | |
345 | 8c0fdd85 | ths | void do_mtc0_status_debug(uint32_t old, uint32_t val)
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346 | 8c0fdd85 | ths | { |
347 | 7a387fff | ths | cpu_abort(env, "mtc0 status debug\n");
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348 | 8c0fdd85 | ths | } |
349 | 8c0fdd85 | ths | |
350 | 7a387fff | ths | void do_mtc0_status_irqraise_debug (void) |
351 | 8c0fdd85 | ths | { |
352 | 7a387fff | ths | cpu_abort(env, "mtc0 status irqraise debug\n");
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353 | 048f6b4d | bellard | } |
354 | 048f6b4d | bellard | |
355 | 8c0fdd85 | ths | void cpu_mips_tlb_flush (CPUState *env, int flush_global) |
356 | 8c0fdd85 | ths | { |
357 | 8c0fdd85 | ths | cpu_abort(env, "mips_tlb_flush\n");
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358 | 8c0fdd85 | ths | } |
359 | 8c0fdd85 | ths | |
360 | 048f6b4d | bellard | #else
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361 | 048f6b4d | bellard | |
362 | 6af0bf9c | bellard | /* CP0 helpers */
|
363 | 873eb012 | ths | void do_mfc0_random (void) |
364 | 6af0bf9c | bellard | { |
365 | 5dc4b744 | ths | T0 = (int32_t)cpu_mips_get_random(env); |
366 | 873eb012 | ths | } |
367 | 6af0bf9c | bellard | |
368 | 873eb012 | ths | void do_mfc0_count (void) |
369 | 873eb012 | ths | { |
370 | 5dc4b744 | ths | T0 = (int32_t)cpu_mips_get_count(env); |
371 | 6af0bf9c | bellard | } |
372 | 6af0bf9c | bellard | |
373 | 8c0fdd85 | ths | void do_mtc0_status_debug(uint32_t old, uint32_t val)
|
374 | 6af0bf9c | bellard | { |
375 | f41c52f1 | ths | fprintf(logfile, "Status %08x (%08x) => %08x (%08x) Cause %08x",
|
376 | f41c52f1 | ths | old, old & env->CP0_Cause & CP0Ca_IP_mask, |
377 | f41c52f1 | ths | val, val & env->CP0_Cause & CP0Ca_IP_mask, |
378 | f41c52f1 | ths | env->CP0_Cause); |
379 | 623a930e | ths | switch (env->hflags & MIPS_HFLAG_KSU) {
|
380 | 623a930e | ths | case MIPS_HFLAG_UM: fputs(", UM\n", logfile); break; |
381 | 623a930e | ths | case MIPS_HFLAG_SM: fputs(", SM\n", logfile); break; |
382 | 623a930e | ths | case MIPS_HFLAG_KM: fputs("\n", logfile); break; |
383 | 623a930e | ths | default: cpu_abort(env, "Invalid MMU mode!\n"); break; |
384 | 623a930e | ths | } |
385 | 8c0fdd85 | ths | } |
386 | 8c0fdd85 | ths | |
387 | 8c0fdd85 | ths | void do_mtc0_status_irqraise_debug(void) |
388 | 8c0fdd85 | ths | { |
389 | 8c0fdd85 | ths | fprintf(logfile, "Raise pending IRQs\n");
|
390 | 6af0bf9c | bellard | } |
391 | 6af0bf9c | bellard | |
392 | 6ea83fed | bellard | void fpu_handle_exception(void) |
393 | 6ea83fed | bellard | { |
394 | 6ea83fed | bellard | #ifdef CONFIG_SOFTFLOAT
|
395 | ead9360e | ths | int flags = get_float_exception_flags(&env->fpu->fp_status);
|
396 | 6ea83fed | bellard | unsigned int cpuflags = 0, enable, cause = 0; |
397 | 6ea83fed | bellard | |
398 | ead9360e | ths | enable = GET_FP_ENABLE(env->fpu->fcr31); |
399 | 6ea83fed | bellard | |
400 | 3b46e624 | ths | /* determine current flags */
|
401 | 6ea83fed | bellard | if (flags & float_flag_invalid) {
|
402 | 6ea83fed | bellard | cpuflags |= FP_INVALID; |
403 | 6ea83fed | bellard | cause |= FP_INVALID & enable; |
404 | 6ea83fed | bellard | } |
405 | 6ea83fed | bellard | if (flags & float_flag_divbyzero) {
|
406 | 3b46e624 | ths | cpuflags |= FP_DIV0; |
407 | 6ea83fed | bellard | cause |= FP_DIV0 & enable; |
408 | 6ea83fed | bellard | } |
409 | 6ea83fed | bellard | if (flags & float_flag_overflow) {
|
410 | 3b46e624 | ths | cpuflags |= FP_OVERFLOW; |
411 | 6ea83fed | bellard | cause |= FP_OVERFLOW & enable; |
412 | 6ea83fed | bellard | } |
413 | 6ea83fed | bellard | if (flags & float_flag_underflow) {
|
414 | 3b46e624 | ths | cpuflags |= FP_UNDERFLOW; |
415 | 6ea83fed | bellard | cause |= FP_UNDERFLOW & enable; |
416 | 6ea83fed | bellard | } |
417 | 6ea83fed | bellard | if (flags & float_flag_inexact) {
|
418 | 5fafdf24 | ths | cpuflags |= FP_INEXACT; |
419 | 6ea83fed | bellard | cause |= FP_INEXACT & enable; |
420 | 6ea83fed | bellard | } |
421 | ead9360e | ths | SET_FP_FLAGS(env->fpu->fcr31, cpuflags); |
422 | ead9360e | ths | SET_FP_CAUSE(env->fpu->fcr31, cause); |
423 | 6ea83fed | bellard | #else
|
424 | ead9360e | ths | SET_FP_FLAGS(env->fpu->fcr31, 0);
|
425 | ead9360e | ths | SET_FP_CAUSE(env->fpu->fcr31, 0);
|
426 | 6ea83fed | bellard | #endif
|
427 | 6ea83fed | bellard | } |
428 | 6ea83fed | bellard | |
429 | 6af0bf9c | bellard | /* TLB management */
|
430 | 814b9a47 | ths | void cpu_mips_tlb_flush (CPUState *env, int flush_global) |
431 | 814b9a47 | ths | { |
432 | 814b9a47 | ths | /* Flush qemu's TLB and discard all shadowed entries. */
|
433 | 814b9a47 | ths | tlb_flush (env, flush_global); |
434 | ead9360e | ths | env->tlb->tlb_in_use = env->tlb->nb_tlb; |
435 | 814b9a47 | ths | } |
436 | 814b9a47 | ths | |
437 | 29929e34 | ths | static void r4k_mips_tlb_flush_extra (CPUState *env, int first) |
438 | 814b9a47 | ths | { |
439 | 814b9a47 | ths | /* Discard entries from env->tlb[first] onwards. */
|
440 | ead9360e | ths | while (env->tlb->tlb_in_use > first) {
|
441 | ead9360e | ths | r4k_invalidate_tlb(env, --env->tlb->tlb_in_use, 0);
|
442 | 814b9a47 | ths | } |
443 | 814b9a47 | ths | } |
444 | 814b9a47 | ths | |
445 | 29929e34 | ths | static void r4k_fill_tlb (int idx) |
446 | 6af0bf9c | bellard | { |
447 | 29929e34 | ths | r4k_tlb_t *tlb; |
448 | 6af0bf9c | bellard | |
449 | 6af0bf9c | bellard | /* XXX: detect conflicting TLBs and raise a MCHECK exception when needed */
|
450 | ead9360e | ths | tlb = &env->tlb->mmu.r4k.tlb[idx]; |
451 | f2e9ebef | ths | tlb->VPN = env->CP0_EntryHi & (TARGET_PAGE_MASK << 1);
|
452 | d26bc211 | ths | #if defined(TARGET_MIPS64)
|
453 | e034e2c3 | ths | tlb->VPN &= env->SEGMask; |
454 | 100ce988 | ths | #endif
|
455 | 98c1b82b | pbrook | tlb->ASID = env->CP0_EntryHi & 0xFF;
|
456 | 3b1c8be4 | ths | tlb->PageMask = env->CP0_PageMask; |
457 | 6af0bf9c | bellard | tlb->G = env->CP0_EntryLo0 & env->CP0_EntryLo1 & 1;
|
458 | 98c1b82b | pbrook | tlb->V0 = (env->CP0_EntryLo0 & 2) != 0; |
459 | 98c1b82b | pbrook | tlb->D0 = (env->CP0_EntryLo0 & 4) != 0; |
460 | 98c1b82b | pbrook | tlb->C0 = (env->CP0_EntryLo0 >> 3) & 0x7; |
461 | 6af0bf9c | bellard | tlb->PFN[0] = (env->CP0_EntryLo0 >> 6) << 12; |
462 | 98c1b82b | pbrook | tlb->V1 = (env->CP0_EntryLo1 & 2) != 0; |
463 | 98c1b82b | pbrook | tlb->D1 = (env->CP0_EntryLo1 & 4) != 0; |
464 | 98c1b82b | pbrook | tlb->C1 = (env->CP0_EntryLo1 >> 3) & 0x7; |
465 | 6af0bf9c | bellard | tlb->PFN[1] = (env->CP0_EntryLo1 >> 6) << 12; |
466 | 6af0bf9c | bellard | } |
467 | 6af0bf9c | bellard | |
468 | 29929e34 | ths | void r4k_do_tlbwi (void) |
469 | 6af0bf9c | bellard | { |
470 | 814b9a47 | ths | /* Discard cached TLB entries. We could avoid doing this if the
|
471 | 814b9a47 | ths | tlbwi is just upgrading access permissions on the current entry;
|
472 | 814b9a47 | ths | that might be a further win. */
|
473 | ead9360e | ths | r4k_mips_tlb_flush_extra (env, env->tlb->nb_tlb); |
474 | 814b9a47 | ths | |
475 | ead9360e | ths | r4k_invalidate_tlb(env, env->CP0_Index % env->tlb->nb_tlb, 0);
|
476 | ead9360e | ths | r4k_fill_tlb(env->CP0_Index % env->tlb->nb_tlb); |
477 | 6af0bf9c | bellard | } |
478 | 6af0bf9c | bellard | |
479 | 29929e34 | ths | void r4k_do_tlbwr (void) |
480 | 6af0bf9c | bellard | { |
481 | 6af0bf9c | bellard | int r = cpu_mips_get_random(env);
|
482 | 6af0bf9c | bellard | |
483 | 29929e34 | ths | r4k_invalidate_tlb(env, r, 1);
|
484 | 29929e34 | ths | r4k_fill_tlb(r); |
485 | 6af0bf9c | bellard | } |
486 | 6af0bf9c | bellard | |
487 | 29929e34 | ths | void r4k_do_tlbp (void) |
488 | 6af0bf9c | bellard | { |
489 | 29929e34 | ths | r4k_tlb_t *tlb; |
490 | f2e9ebef | ths | target_ulong mask; |
491 | 6af0bf9c | bellard | target_ulong tag; |
492 | f2e9ebef | ths | target_ulong VPN; |
493 | 6af0bf9c | bellard | uint8_t ASID; |
494 | 6af0bf9c | bellard | int i;
|
495 | 6af0bf9c | bellard | |
496 | 3d9fb9fe | bellard | ASID = env->CP0_EntryHi & 0xFF;
|
497 | ead9360e | ths | for (i = 0; i < env->tlb->nb_tlb; i++) { |
498 | ead9360e | ths | tlb = &env->tlb->mmu.r4k.tlb[i]; |
499 | f2e9ebef | ths | /* 1k pages are not supported. */
|
500 | f2e9ebef | ths | mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
|
501 | f2e9ebef | ths | tag = env->CP0_EntryHi & ~mask; |
502 | f2e9ebef | ths | VPN = tlb->VPN & ~mask; |
503 | 6af0bf9c | bellard | /* Check ASID, virtual page number & size */
|
504 | f2e9ebef | ths | if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag) { |
505 | 6af0bf9c | bellard | /* TLB match */
|
506 | 9c2149c8 | ths | env->CP0_Index = i; |
507 | 6af0bf9c | bellard | break;
|
508 | 6af0bf9c | bellard | } |
509 | 6af0bf9c | bellard | } |
510 | ead9360e | ths | if (i == env->tlb->nb_tlb) {
|
511 | 814b9a47 | ths | /* No match. Discard any shadow entries, if any of them match. */
|
512 | ead9360e | ths | for (i = env->tlb->nb_tlb; i < env->tlb->tlb_in_use; i++) {
|
513 | ead9360e | ths | tlb = &env->tlb->mmu.r4k.tlb[i]; |
514 | f2e9ebef | ths | /* 1k pages are not supported. */
|
515 | f2e9ebef | ths | mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
|
516 | f2e9ebef | ths | tag = env->CP0_EntryHi & ~mask; |
517 | f2e9ebef | ths | VPN = tlb->VPN & ~mask; |
518 | 814b9a47 | ths | /* Check ASID, virtual page number & size */
|
519 | f2e9ebef | ths | if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag) { |
520 | 29929e34 | ths | r4k_mips_tlb_flush_extra (env, i); |
521 | 814b9a47 | ths | break;
|
522 | 814b9a47 | ths | } |
523 | 814b9a47 | ths | } |
524 | 814b9a47 | ths | |
525 | 9c2149c8 | ths | env->CP0_Index |= 0x80000000;
|
526 | 6af0bf9c | bellard | } |
527 | 6af0bf9c | bellard | } |
528 | 6af0bf9c | bellard | |
529 | 29929e34 | ths | void r4k_do_tlbr (void) |
530 | 6af0bf9c | bellard | { |
531 | 29929e34 | ths | r4k_tlb_t *tlb; |
532 | 09c56b84 | pbrook | uint8_t ASID; |
533 | 6af0bf9c | bellard | |
534 | 09c56b84 | pbrook | ASID = env->CP0_EntryHi & 0xFF;
|
535 | ead9360e | ths | tlb = &env->tlb->mmu.r4k.tlb[env->CP0_Index % env->tlb->nb_tlb]; |
536 | 4ad40f36 | bellard | |
537 | 4ad40f36 | bellard | /* If this will change the current ASID, flush qemu's TLB. */
|
538 | 814b9a47 | ths | if (ASID != tlb->ASID)
|
539 | 814b9a47 | ths | cpu_mips_tlb_flush (env, 1);
|
540 | 814b9a47 | ths | |
541 | ead9360e | ths | r4k_mips_tlb_flush_extra(env, env->tlb->nb_tlb); |
542 | 4ad40f36 | bellard | |
543 | 6af0bf9c | bellard | env->CP0_EntryHi = tlb->VPN | tlb->ASID; |
544 | 3b1c8be4 | ths | env->CP0_PageMask = tlb->PageMask; |
545 | 7495fd0f | ths | env->CP0_EntryLo0 = tlb->G | (tlb->V0 << 1) | (tlb->D0 << 2) | |
546 | 7495fd0f | ths | (tlb->C0 << 3) | (tlb->PFN[0] >> 6); |
547 | 7495fd0f | ths | env->CP0_EntryLo1 = tlb->G | (tlb->V1 << 1) | (tlb->D1 << 2) | |
548 | 7495fd0f | ths | (tlb->C1 << 3) | (tlb->PFN[1] >> 6); |
549 | 6af0bf9c | bellard | } |
550 | 6af0bf9c | bellard | |
551 | 048f6b4d | bellard | #endif /* !CONFIG_USER_ONLY */ |
552 | 048f6b4d | bellard | |
553 | c570fd16 | ths | void dump_ldst (const unsigned char *func) |
554 | 6af0bf9c | bellard | { |
555 | 6af0bf9c | bellard | if (loglevel)
|
556 | 3594c774 | ths | fprintf(logfile, "%s => " TARGET_FMT_lx " " TARGET_FMT_lx "\n", __func__, T0, T1); |
557 | 6af0bf9c | bellard | } |
558 | 6af0bf9c | bellard | |
559 | 6af0bf9c | bellard | void dump_sc (void) |
560 | 6af0bf9c | bellard | { |
561 | 6af0bf9c | bellard | if (loglevel) {
|
562 | 3594c774 | ths | fprintf(logfile, "%s " TARGET_FMT_lx " at " TARGET_FMT_lx " (" TARGET_FMT_lx ")\n", __func__, |
563 | 6af0bf9c | bellard | T1, T0, env->CP0_LLAddr); |
564 | 6af0bf9c | bellard | } |
565 | 6af0bf9c | bellard | } |
566 | 6af0bf9c | bellard | |
567 | f41c52f1 | ths | void debug_pre_eret (void) |
568 | 6af0bf9c | bellard | { |
569 | f41c52f1 | ths | fprintf(logfile, "ERET: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx, |
570 | ead9360e | ths | env->PC[env->current_tc], env->CP0_EPC); |
571 | f41c52f1 | ths | if (env->CP0_Status & (1 << CP0St_ERL)) |
572 | f41c52f1 | ths | fprintf(logfile, " ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC);
|
573 | f41c52f1 | ths | if (env->hflags & MIPS_HFLAG_DM)
|
574 | f41c52f1 | ths | fprintf(logfile, " DEPC " TARGET_FMT_lx, env->CP0_DEPC);
|
575 | f41c52f1 | ths | fputs("\n", logfile);
|
576 | f41c52f1 | ths | } |
577 | f41c52f1 | ths | |
578 | f41c52f1 | ths | void debug_post_eret (void) |
579 | f41c52f1 | ths | { |
580 | 744e0915 | ths | fprintf(logfile, " => PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx, |
581 | ead9360e | ths | env->PC[env->current_tc], env->CP0_EPC); |
582 | f41c52f1 | ths | if (env->CP0_Status & (1 << CP0St_ERL)) |
583 | f41c52f1 | ths | fprintf(logfile, " ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC);
|
584 | f41c52f1 | ths | if (env->hflags & MIPS_HFLAG_DM)
|
585 | f41c52f1 | ths | fprintf(logfile, " DEPC " TARGET_FMT_lx, env->CP0_DEPC);
|
586 | 623a930e | ths | switch (env->hflags & MIPS_HFLAG_KSU) {
|
587 | 623a930e | ths | case MIPS_HFLAG_UM: fputs(", UM\n", logfile); break; |
588 | 623a930e | ths | case MIPS_HFLAG_SM: fputs(", SM\n", logfile); break; |
589 | 623a930e | ths | case MIPS_HFLAG_KM: fputs("\n", logfile); break; |
590 | 623a930e | ths | default: cpu_abort(env, "Invalid MMU mode!\n"); break; |
591 | 623a930e | ths | } |
592 | 6af0bf9c | bellard | } |
593 | 6af0bf9c | bellard | |
594 | 6af0bf9c | bellard | void do_pmon (int function) |
595 | 6af0bf9c | bellard | { |
596 | 6af0bf9c | bellard | function /= 2;
|
597 | 6af0bf9c | bellard | switch (function) {
|
598 | 6af0bf9c | bellard | case 2: /* TODO: char inbyte(int waitflag); */ |
599 | d0dc7dc3 | ths | if (env->gpr[env->current_tc][4] == 0) |
600 | d0dc7dc3 | ths | env->gpr[env->current_tc][2] = -1; |
601 | 6af0bf9c | bellard | /* Fall through */
|
602 | 6af0bf9c | bellard | case 11: /* TODO: char inbyte (void); */ |
603 | d0dc7dc3 | ths | env->gpr[env->current_tc][2] = -1; |
604 | 6af0bf9c | bellard | break;
|
605 | 6af0bf9c | bellard | case 3: |
606 | 6af0bf9c | bellard | case 12: |
607 | d0dc7dc3 | ths | printf("%c", (char)(env->gpr[env->current_tc][4] & 0xFF)); |
608 | 6af0bf9c | bellard | break;
|
609 | 6af0bf9c | bellard | case 17: |
610 | 6af0bf9c | bellard | break;
|
611 | 6af0bf9c | bellard | case 158: |
612 | 6af0bf9c | bellard | { |
613 | d0dc7dc3 | ths | unsigned char *fmt = (void *)(unsigned long)env->gpr[env->current_tc][4]; |
614 | 6af0bf9c | bellard | printf("%s", fmt);
|
615 | 6af0bf9c | bellard | } |
616 | 6af0bf9c | bellard | break;
|
617 | 6af0bf9c | bellard | } |
618 | 6af0bf9c | bellard | } |
619 | e37e863f | bellard | |
620 | 5fafdf24 | ths | #if !defined(CONFIG_USER_ONLY)
|
621 | e37e863f | bellard | |
622 | 4ad40f36 | bellard | static void do_unaligned_access (target_ulong addr, int is_write, int is_user, void *retaddr); |
623 | 4ad40f36 | bellard | |
624 | e37e863f | bellard | #define MMUSUFFIX _mmu
|
625 | 4ad40f36 | bellard | #define ALIGNED_ONLY
|
626 | e37e863f | bellard | |
627 | e37e863f | bellard | #define SHIFT 0 |
628 | e37e863f | bellard | #include "softmmu_template.h" |
629 | e37e863f | bellard | |
630 | e37e863f | bellard | #define SHIFT 1 |
631 | e37e863f | bellard | #include "softmmu_template.h" |
632 | e37e863f | bellard | |
633 | e37e863f | bellard | #define SHIFT 2 |
634 | e37e863f | bellard | #include "softmmu_template.h" |
635 | e37e863f | bellard | |
636 | e37e863f | bellard | #define SHIFT 3 |
637 | e37e863f | bellard | #include "softmmu_template.h" |
638 | e37e863f | bellard | |
639 | 4ad40f36 | bellard | static void do_unaligned_access (target_ulong addr, int is_write, int is_user, void *retaddr) |
640 | 4ad40f36 | bellard | { |
641 | 4ad40f36 | bellard | env->CP0_BadVAddr = addr; |
642 | 4ad40f36 | bellard | do_restore_state (retaddr); |
643 | 4ad40f36 | bellard | do_raise_exception ((is_write == 1) ? EXCP_AdES : EXCP_AdEL);
|
644 | 4ad40f36 | bellard | } |
645 | 4ad40f36 | bellard | |
646 | 6ebbf390 | j_mayer | void tlb_fill (target_ulong addr, int is_write, int mmu_idx, void *retaddr) |
647 | e37e863f | bellard | { |
648 | e37e863f | bellard | TranslationBlock *tb; |
649 | e37e863f | bellard | CPUState *saved_env; |
650 | e37e863f | bellard | unsigned long pc; |
651 | e37e863f | bellard | int ret;
|
652 | e37e863f | bellard | |
653 | e37e863f | bellard | /* XXX: hack to restore env in all cases, even if not called from
|
654 | e37e863f | bellard | generated code */
|
655 | e37e863f | bellard | saved_env = env; |
656 | e37e863f | bellard | env = cpu_single_env; |
657 | 6ebbf390 | j_mayer | ret = cpu_mips_handle_mmu_fault(env, addr, is_write, mmu_idx, 1);
|
658 | e37e863f | bellard | if (ret) {
|
659 | e37e863f | bellard | if (retaddr) {
|
660 | e37e863f | bellard | /* now we have a real cpu fault */
|
661 | e37e863f | bellard | pc = (unsigned long)retaddr; |
662 | e37e863f | bellard | tb = tb_find_pc(pc); |
663 | e37e863f | bellard | if (tb) {
|
664 | e37e863f | bellard | /* the PC is inside the translated code. It means that we have
|
665 | e37e863f | bellard | a virtual CPU fault */
|
666 | e37e863f | bellard | cpu_restore_state(tb, env, pc, NULL);
|
667 | e37e863f | bellard | } |
668 | e37e863f | bellard | } |
669 | e37e863f | bellard | do_raise_exception_err(env->exception_index, env->error_code); |
670 | e37e863f | bellard | } |
671 | e37e863f | bellard | env = saved_env; |
672 | e37e863f | bellard | } |
673 | e37e863f | bellard | |
674 | 647de6ca | ths | void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec, |
675 | 647de6ca | ths | int unused)
|
676 | 647de6ca | ths | { |
677 | 647de6ca | ths | if (is_exec)
|
678 | 647de6ca | ths | do_raise_exception(EXCP_IBE); |
679 | 647de6ca | ths | else
|
680 | 647de6ca | ths | do_raise_exception(EXCP_DBE); |
681 | 647de6ca | ths | } |
682 | e37e863f | bellard | #endif
|
683 | fd4a04eb | ths | |
684 | fd4a04eb | ths | /* Complex FPU operations which may need stack space. */
|
685 | fd4a04eb | ths | |
686 | f090c9d4 | pbrook | #define FLOAT_ONE32 make_float32(0x3f8 << 20) |
687 | f090c9d4 | pbrook | #define FLOAT_ONE64 make_float64(0x3ffULL << 52) |
688 | f090c9d4 | pbrook | #define FLOAT_TWO32 make_float32(1 << 30) |
689 | f090c9d4 | pbrook | #define FLOAT_TWO64 make_float64(1ULL << 62) |
690 | 54454097 | ths | #define FLOAT_QNAN32 0x7fbfffff |
691 | 54454097 | ths | #define FLOAT_QNAN64 0x7ff7ffffffffffffULL |
692 | 54454097 | ths | #define FLOAT_SNAN32 0x7fffffff |
693 | 54454097 | ths | #define FLOAT_SNAN64 0x7fffffffffffffffULL |
694 | 8dfdb87c | ths | |
695 | fd4a04eb | ths | /* convert MIPS rounding mode in FCR31 to IEEE library */
|
696 | fd4a04eb | ths | unsigned int ieee_rm[] = { |
697 | fd4a04eb | ths | float_round_nearest_even, |
698 | fd4a04eb | ths | float_round_to_zero, |
699 | fd4a04eb | ths | float_round_up, |
700 | fd4a04eb | ths | float_round_down |
701 | fd4a04eb | ths | }; |
702 | fd4a04eb | ths | |
703 | fd4a04eb | ths | #define RESTORE_ROUNDING_MODE \
|
704 | ead9360e | ths | set_float_rounding_mode(ieee_rm[env->fpu->fcr31 & 3], &env->fpu->fp_status)
|
705 | fd4a04eb | ths | |
706 | ead9360e | ths | void do_cfc1 (int reg) |
707 | fd4a04eb | ths | { |
708 | ead9360e | ths | switch (reg) {
|
709 | ead9360e | ths | case 0: |
710 | ead9360e | ths | T0 = (int32_t)env->fpu->fcr0; |
711 | ead9360e | ths | break;
|
712 | ead9360e | ths | case 25: |
713 | ead9360e | ths | T0 = ((env->fpu->fcr31 >> 24) & 0xfe) | ((env->fpu->fcr31 >> 23) & 0x1); |
714 | ead9360e | ths | break;
|
715 | ead9360e | ths | case 26: |
716 | ead9360e | ths | T0 = env->fpu->fcr31 & 0x0003f07c;
|
717 | ead9360e | ths | break;
|
718 | ead9360e | ths | case 28: |
719 | ead9360e | ths | T0 = (env->fpu->fcr31 & 0x00000f83) | ((env->fpu->fcr31 >> 22) & 0x4); |
720 | ead9360e | ths | break;
|
721 | ead9360e | ths | default:
|
722 | ead9360e | ths | T0 = (int32_t)env->fpu->fcr31; |
723 | ead9360e | ths | break;
|
724 | ead9360e | ths | } |
725 | ead9360e | ths | } |
726 | ead9360e | ths | |
727 | ead9360e | ths | void do_ctc1 (int reg) |
728 | ead9360e | ths | { |
729 | ead9360e | ths | switch(reg) {
|
730 | fd4a04eb | ths | case 25: |
731 | fd4a04eb | ths | if (T0 & 0xffffff00) |
732 | fd4a04eb | ths | return;
|
733 | ead9360e | ths | env->fpu->fcr31 = (env->fpu->fcr31 & 0x017fffff) | ((T0 & 0xfe) << 24) | |
734 | fd4a04eb | ths | ((T0 & 0x1) << 23); |
735 | fd4a04eb | ths | break;
|
736 | fd4a04eb | ths | case 26: |
737 | fd4a04eb | ths | if (T0 & 0x007c0000) |
738 | fd4a04eb | ths | return;
|
739 | ead9360e | ths | env->fpu->fcr31 = (env->fpu->fcr31 & 0xfffc0f83) | (T0 & 0x0003f07c); |
740 | fd4a04eb | ths | break;
|
741 | fd4a04eb | ths | case 28: |
742 | fd4a04eb | ths | if (T0 & 0x007c0000) |
743 | fd4a04eb | ths | return;
|
744 | ead9360e | ths | env->fpu->fcr31 = (env->fpu->fcr31 & 0xfefff07c) | (T0 & 0x00000f83) | |
745 | fd4a04eb | ths | ((T0 & 0x4) << 22); |
746 | fd4a04eb | ths | break;
|
747 | fd4a04eb | ths | case 31: |
748 | fd4a04eb | ths | if (T0 & 0x007c0000) |
749 | fd4a04eb | ths | return;
|
750 | ead9360e | ths | env->fpu->fcr31 = T0; |
751 | fd4a04eb | ths | break;
|
752 | fd4a04eb | ths | default:
|
753 | fd4a04eb | ths | return;
|
754 | fd4a04eb | ths | } |
755 | fd4a04eb | ths | /* set rounding mode */
|
756 | fd4a04eb | ths | RESTORE_ROUNDING_MODE; |
757 | ead9360e | ths | set_float_exception_flags(0, &env->fpu->fp_status);
|
758 | ead9360e | ths | if ((GET_FP_ENABLE(env->fpu->fcr31) | 0x20) & GET_FP_CAUSE(env->fpu->fcr31)) |
759 | fd4a04eb | ths | do_raise_exception(EXCP_FPE); |
760 | fd4a04eb | ths | } |
761 | fd4a04eb | ths | |
762 | aa343735 | ths | static always_inline char ieee_ex_to_mips(char xcpt) |
763 | fd4a04eb | ths | { |
764 | fd4a04eb | ths | return (xcpt & float_flag_inexact) >> 5 | |
765 | fd4a04eb | ths | (xcpt & float_flag_underflow) >> 3 |
|
766 | fd4a04eb | ths | (xcpt & float_flag_overflow) >> 1 |
|
767 | fd4a04eb | ths | (xcpt & float_flag_divbyzero) << 1 |
|
768 | fd4a04eb | ths | (xcpt & float_flag_invalid) << 4;
|
769 | fd4a04eb | ths | } |
770 | fd4a04eb | ths | |
771 | aa343735 | ths | static always_inline char mips_ex_to_ieee(char xcpt) |
772 | fd4a04eb | ths | { |
773 | fd4a04eb | ths | return (xcpt & FP_INEXACT) << 5 | |
774 | fd4a04eb | ths | (xcpt & FP_UNDERFLOW) << 3 |
|
775 | fd4a04eb | ths | (xcpt & FP_OVERFLOW) << 1 |
|
776 | fd4a04eb | ths | (xcpt & FP_DIV0) >> 1 |
|
777 | fd4a04eb | ths | (xcpt & FP_INVALID) >> 4;
|
778 | fd4a04eb | ths | } |
779 | fd4a04eb | ths | |
780 | aa343735 | ths | static always_inline void update_fcr31(void) |
781 | fd4a04eb | ths | { |
782 | ead9360e | ths | int tmp = ieee_ex_to_mips(get_float_exception_flags(&env->fpu->fp_status));
|
783 | fd4a04eb | ths | |
784 | ead9360e | ths | SET_FP_CAUSE(env->fpu->fcr31, tmp); |
785 | ead9360e | ths | if (GET_FP_ENABLE(env->fpu->fcr31) & tmp)
|
786 | fd4a04eb | ths | do_raise_exception(EXCP_FPE); |
787 | fd4a04eb | ths | else
|
788 | ead9360e | ths | UPDATE_FP_FLAGS(env->fpu->fcr31, tmp); |
789 | fd4a04eb | ths | } |
790 | fd4a04eb | ths | |
791 | fd4a04eb | ths | #define FLOAT_OP(name, p) void do_float_##name##_##p(void) |
792 | fd4a04eb | ths | |
793 | fd4a04eb | ths | FLOAT_OP(cvtd, s) |
794 | fd4a04eb | ths | { |
795 | ead9360e | ths | set_float_exception_flags(0, &env->fpu->fp_status);
|
796 | ead9360e | ths | FDT2 = float32_to_float64(FST0, &env->fpu->fp_status); |
797 | fd4a04eb | ths | update_fcr31(); |
798 | fd4a04eb | ths | } |
799 | fd4a04eb | ths | FLOAT_OP(cvtd, w) |
800 | fd4a04eb | ths | { |
801 | ead9360e | ths | set_float_exception_flags(0, &env->fpu->fp_status);
|
802 | ead9360e | ths | FDT2 = int32_to_float64(WT0, &env->fpu->fp_status); |
803 | fd4a04eb | ths | update_fcr31(); |
804 | fd4a04eb | ths | } |
805 | fd4a04eb | ths | FLOAT_OP(cvtd, l) |
806 | fd4a04eb | ths | { |
807 | ead9360e | ths | set_float_exception_flags(0, &env->fpu->fp_status);
|
808 | ead9360e | ths | FDT2 = int64_to_float64(DT0, &env->fpu->fp_status); |
809 | fd4a04eb | ths | update_fcr31(); |
810 | fd4a04eb | ths | } |
811 | fd4a04eb | ths | FLOAT_OP(cvtl, d) |
812 | fd4a04eb | ths | { |
813 | ead9360e | ths | set_float_exception_flags(0, &env->fpu->fp_status);
|
814 | ead9360e | ths | DT2 = float64_to_int64(FDT0, &env->fpu->fp_status); |
815 | fd4a04eb | ths | update_fcr31(); |
816 | ead9360e | ths | if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
|
817 | 54454097 | ths | DT2 = FLOAT_SNAN64; |
818 | fd4a04eb | ths | } |
819 | fd4a04eb | ths | FLOAT_OP(cvtl, s) |
820 | fd4a04eb | ths | { |
821 | ead9360e | ths | set_float_exception_flags(0, &env->fpu->fp_status);
|
822 | ead9360e | ths | DT2 = float32_to_int64(FST0, &env->fpu->fp_status); |
823 | fd4a04eb | ths | update_fcr31(); |
824 | ead9360e | ths | if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
|
825 | 54454097 | ths | DT2 = FLOAT_SNAN64; |
826 | fd4a04eb | ths | } |
827 | fd4a04eb | ths | |
828 | fd4a04eb | ths | FLOAT_OP(cvtps, pw) |
829 | fd4a04eb | ths | { |
830 | ead9360e | ths | set_float_exception_flags(0, &env->fpu->fp_status);
|
831 | ead9360e | ths | FST2 = int32_to_float32(WT0, &env->fpu->fp_status); |
832 | ead9360e | ths | FSTH2 = int32_to_float32(WTH0, &env->fpu->fp_status); |
833 | fd4a04eb | ths | update_fcr31(); |
834 | fd4a04eb | ths | } |
835 | fd4a04eb | ths | FLOAT_OP(cvtpw, ps) |
836 | fd4a04eb | ths | { |
837 | ead9360e | ths | set_float_exception_flags(0, &env->fpu->fp_status);
|
838 | ead9360e | ths | WT2 = float32_to_int32(FST0, &env->fpu->fp_status); |
839 | ead9360e | ths | WTH2 = float32_to_int32(FSTH0, &env->fpu->fp_status); |
840 | fd4a04eb | ths | update_fcr31(); |
841 | ead9360e | ths | if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
|
842 | 54454097 | ths | WT2 = FLOAT_SNAN32; |
843 | fd4a04eb | ths | } |
844 | fd4a04eb | ths | FLOAT_OP(cvts, d) |
845 | fd4a04eb | ths | { |
846 | ead9360e | ths | set_float_exception_flags(0, &env->fpu->fp_status);
|
847 | ead9360e | ths | FST2 = float64_to_float32(FDT0, &env->fpu->fp_status); |
848 | fd4a04eb | ths | update_fcr31(); |
849 | fd4a04eb | ths | } |
850 | fd4a04eb | ths | FLOAT_OP(cvts, w) |
851 | fd4a04eb | ths | { |
852 | ead9360e | ths | set_float_exception_flags(0, &env->fpu->fp_status);
|
853 | ead9360e | ths | FST2 = int32_to_float32(WT0, &env->fpu->fp_status); |
854 | fd4a04eb | ths | update_fcr31(); |
855 | fd4a04eb | ths | } |
856 | fd4a04eb | ths | FLOAT_OP(cvts, l) |
857 | fd4a04eb | ths | { |
858 | ead9360e | ths | set_float_exception_flags(0, &env->fpu->fp_status);
|
859 | ead9360e | ths | FST2 = int64_to_float32(DT0, &env->fpu->fp_status); |
860 | fd4a04eb | ths | update_fcr31(); |
861 | fd4a04eb | ths | } |
862 | fd4a04eb | ths | FLOAT_OP(cvts, pl) |
863 | fd4a04eb | ths | { |
864 | ead9360e | ths | set_float_exception_flags(0, &env->fpu->fp_status);
|
865 | fd4a04eb | ths | WT2 = WT0; |
866 | fd4a04eb | ths | update_fcr31(); |
867 | fd4a04eb | ths | } |
868 | fd4a04eb | ths | FLOAT_OP(cvts, pu) |
869 | fd4a04eb | ths | { |
870 | ead9360e | ths | set_float_exception_flags(0, &env->fpu->fp_status);
|
871 | fd4a04eb | ths | WT2 = WTH0; |
872 | fd4a04eb | ths | update_fcr31(); |
873 | fd4a04eb | ths | } |
874 | fd4a04eb | ths | FLOAT_OP(cvtw, s) |
875 | fd4a04eb | ths | { |
876 | ead9360e | ths | set_float_exception_flags(0, &env->fpu->fp_status);
|
877 | ead9360e | ths | WT2 = float32_to_int32(FST0, &env->fpu->fp_status); |
878 | fd4a04eb | ths | update_fcr31(); |
879 | ead9360e | ths | if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
|
880 | 54454097 | ths | WT2 = FLOAT_SNAN32; |
881 | fd4a04eb | ths | } |
882 | fd4a04eb | ths | FLOAT_OP(cvtw, d) |
883 | fd4a04eb | ths | { |
884 | ead9360e | ths | set_float_exception_flags(0, &env->fpu->fp_status);
|
885 | ead9360e | ths | WT2 = float64_to_int32(FDT0, &env->fpu->fp_status); |
886 | fd4a04eb | ths | update_fcr31(); |
887 | ead9360e | ths | if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
|
888 | 54454097 | ths | WT2 = FLOAT_SNAN32; |
889 | fd4a04eb | ths | } |
890 | fd4a04eb | ths | |
891 | fd4a04eb | ths | FLOAT_OP(roundl, d) |
892 | fd4a04eb | ths | { |
893 | ead9360e | ths | set_float_rounding_mode(float_round_nearest_even, &env->fpu->fp_status); |
894 | ead9360e | ths | DT2 = float64_to_int64(FDT0, &env->fpu->fp_status); |
895 | fd4a04eb | ths | RESTORE_ROUNDING_MODE; |
896 | fd4a04eb | ths | update_fcr31(); |
897 | ead9360e | ths | if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
|
898 | 54454097 | ths | DT2 = FLOAT_SNAN64; |
899 | fd4a04eb | ths | } |
900 | fd4a04eb | ths | FLOAT_OP(roundl, s) |
901 | fd4a04eb | ths | { |
902 | ead9360e | ths | set_float_rounding_mode(float_round_nearest_even, &env->fpu->fp_status); |
903 | ead9360e | ths | DT2 = float32_to_int64(FST0, &env->fpu->fp_status); |
904 | fd4a04eb | ths | RESTORE_ROUNDING_MODE; |
905 | fd4a04eb | ths | update_fcr31(); |
906 | ead9360e | ths | if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
|
907 | 54454097 | ths | DT2 = FLOAT_SNAN64; |
908 | fd4a04eb | ths | } |
909 | fd4a04eb | ths | FLOAT_OP(roundw, d) |
910 | fd4a04eb | ths | { |
911 | ead9360e | ths | set_float_rounding_mode(float_round_nearest_even, &env->fpu->fp_status); |
912 | ead9360e | ths | WT2 = float64_to_int32(FDT0, &env->fpu->fp_status); |
913 | fd4a04eb | ths | RESTORE_ROUNDING_MODE; |
914 | fd4a04eb | ths | update_fcr31(); |
915 | ead9360e | ths | if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
|
916 | 54454097 | ths | WT2 = FLOAT_SNAN32; |
917 | fd4a04eb | ths | } |
918 | fd4a04eb | ths | FLOAT_OP(roundw, s) |
919 | fd4a04eb | ths | { |
920 | ead9360e | ths | set_float_rounding_mode(float_round_nearest_even, &env->fpu->fp_status); |
921 | ead9360e | ths | WT2 = float32_to_int32(FST0, &env->fpu->fp_status); |
922 | fd4a04eb | ths | RESTORE_ROUNDING_MODE; |
923 | fd4a04eb | ths | update_fcr31(); |
924 | ead9360e | ths | if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
|
925 | 54454097 | ths | WT2 = FLOAT_SNAN32; |
926 | fd4a04eb | ths | } |
927 | fd4a04eb | ths | |
928 | fd4a04eb | ths | FLOAT_OP(truncl, d) |
929 | fd4a04eb | ths | { |
930 | ead9360e | ths | DT2 = float64_to_int64_round_to_zero(FDT0, &env->fpu->fp_status); |
931 | fd4a04eb | ths | update_fcr31(); |
932 | ead9360e | ths | if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
|
933 | 54454097 | ths | DT2 = FLOAT_SNAN64; |
934 | fd4a04eb | ths | } |
935 | fd4a04eb | ths | FLOAT_OP(truncl, s) |
936 | fd4a04eb | ths | { |
937 | ead9360e | ths | DT2 = float32_to_int64_round_to_zero(FST0, &env->fpu->fp_status); |
938 | fd4a04eb | ths | update_fcr31(); |
939 | ead9360e | ths | if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
|
940 | 54454097 | ths | DT2 = FLOAT_SNAN64; |
941 | fd4a04eb | ths | } |
942 | fd4a04eb | ths | FLOAT_OP(truncw, d) |
943 | fd4a04eb | ths | { |
944 | ead9360e | ths | WT2 = float64_to_int32_round_to_zero(FDT0, &env->fpu->fp_status); |
945 | fd4a04eb | ths | update_fcr31(); |
946 | ead9360e | ths | if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
|
947 | 54454097 | ths | WT2 = FLOAT_SNAN32; |
948 | fd4a04eb | ths | } |
949 | fd4a04eb | ths | FLOAT_OP(truncw, s) |
950 | fd4a04eb | ths | { |
951 | ead9360e | ths | WT2 = float32_to_int32_round_to_zero(FST0, &env->fpu->fp_status); |
952 | fd4a04eb | ths | update_fcr31(); |
953 | ead9360e | ths | if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
|
954 | 54454097 | ths | WT2 = FLOAT_SNAN32; |
955 | fd4a04eb | ths | } |
956 | fd4a04eb | ths | |
957 | fd4a04eb | ths | FLOAT_OP(ceill, d) |
958 | fd4a04eb | ths | { |
959 | ead9360e | ths | set_float_rounding_mode(float_round_up, &env->fpu->fp_status); |
960 | ead9360e | ths | DT2 = float64_to_int64(FDT0, &env->fpu->fp_status); |
961 | fd4a04eb | ths | RESTORE_ROUNDING_MODE; |
962 | fd4a04eb | ths | update_fcr31(); |
963 | ead9360e | ths | if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
|
964 | 54454097 | ths | DT2 = FLOAT_SNAN64; |
965 | fd4a04eb | ths | } |
966 | fd4a04eb | ths | FLOAT_OP(ceill, s) |
967 | fd4a04eb | ths | { |
968 | ead9360e | ths | set_float_rounding_mode(float_round_up, &env->fpu->fp_status); |
969 | ead9360e | ths | DT2 = float32_to_int64(FST0, &env->fpu->fp_status); |
970 | fd4a04eb | ths | RESTORE_ROUNDING_MODE; |
971 | fd4a04eb | ths | update_fcr31(); |
972 | ead9360e | ths | if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
|
973 | 54454097 | ths | DT2 = FLOAT_SNAN64; |
974 | fd4a04eb | ths | } |
975 | fd4a04eb | ths | FLOAT_OP(ceilw, d) |
976 | fd4a04eb | ths | { |
977 | ead9360e | ths | set_float_rounding_mode(float_round_up, &env->fpu->fp_status); |
978 | ead9360e | ths | WT2 = float64_to_int32(FDT0, &env->fpu->fp_status); |
979 | fd4a04eb | ths | RESTORE_ROUNDING_MODE; |
980 | fd4a04eb | ths | update_fcr31(); |
981 | ead9360e | ths | if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
|
982 | 54454097 | ths | WT2 = FLOAT_SNAN32; |
983 | fd4a04eb | ths | } |
984 | fd4a04eb | ths | FLOAT_OP(ceilw, s) |
985 | fd4a04eb | ths | { |
986 | ead9360e | ths | set_float_rounding_mode(float_round_up, &env->fpu->fp_status); |
987 | ead9360e | ths | WT2 = float32_to_int32(FST0, &env->fpu->fp_status); |
988 | fd4a04eb | ths | RESTORE_ROUNDING_MODE; |
989 | fd4a04eb | ths | update_fcr31(); |
990 | ead9360e | ths | if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
|
991 | 54454097 | ths | WT2 = FLOAT_SNAN32; |
992 | fd4a04eb | ths | } |
993 | fd4a04eb | ths | |
994 | fd4a04eb | ths | FLOAT_OP(floorl, d) |
995 | fd4a04eb | ths | { |
996 | ead9360e | ths | set_float_rounding_mode(float_round_down, &env->fpu->fp_status); |
997 | ead9360e | ths | DT2 = float64_to_int64(FDT0, &env->fpu->fp_status); |
998 | fd4a04eb | ths | RESTORE_ROUNDING_MODE; |
999 | fd4a04eb | ths | update_fcr31(); |
1000 | ead9360e | ths | if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
|
1001 | 54454097 | ths | DT2 = FLOAT_SNAN64; |
1002 | fd4a04eb | ths | } |
1003 | fd4a04eb | ths | FLOAT_OP(floorl, s) |
1004 | fd4a04eb | ths | { |
1005 | ead9360e | ths | set_float_rounding_mode(float_round_down, &env->fpu->fp_status); |
1006 | ead9360e | ths | DT2 = float32_to_int64(FST0, &env->fpu->fp_status); |
1007 | fd4a04eb | ths | RESTORE_ROUNDING_MODE; |
1008 | fd4a04eb | ths | update_fcr31(); |
1009 | ead9360e | ths | if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
|
1010 | 54454097 | ths | DT2 = FLOAT_SNAN64; |
1011 | fd4a04eb | ths | } |
1012 | fd4a04eb | ths | FLOAT_OP(floorw, d) |
1013 | fd4a04eb | ths | { |
1014 | ead9360e | ths | set_float_rounding_mode(float_round_down, &env->fpu->fp_status); |
1015 | ead9360e | ths | WT2 = float64_to_int32(FDT0, &env->fpu->fp_status); |
1016 | fd4a04eb | ths | RESTORE_ROUNDING_MODE; |
1017 | fd4a04eb | ths | update_fcr31(); |
1018 | ead9360e | ths | if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
|
1019 | 54454097 | ths | WT2 = FLOAT_SNAN32; |
1020 | fd4a04eb | ths | } |
1021 | fd4a04eb | ths | FLOAT_OP(floorw, s) |
1022 | fd4a04eb | ths | { |
1023 | ead9360e | ths | set_float_rounding_mode(float_round_down, &env->fpu->fp_status); |
1024 | ead9360e | ths | WT2 = float32_to_int32(FST0, &env->fpu->fp_status); |
1025 | fd4a04eb | ths | RESTORE_ROUNDING_MODE; |
1026 | fd4a04eb | ths | update_fcr31(); |
1027 | ead9360e | ths | if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
|
1028 | 54454097 | ths | WT2 = FLOAT_SNAN32; |
1029 | fd4a04eb | ths | } |
1030 | fd4a04eb | ths | |
1031 | 8dfdb87c | ths | /* MIPS specific unary operations */
|
1032 | 8dfdb87c | ths | FLOAT_OP(recip, d) |
1033 | 8dfdb87c | ths | { |
1034 | ead9360e | ths | set_float_exception_flags(0, &env->fpu->fp_status);
|
1035 | ead9360e | ths | FDT2 = float64_div(FLOAT_ONE64, FDT0, &env->fpu->fp_status); |
1036 | 8dfdb87c | ths | update_fcr31(); |
1037 | 8dfdb87c | ths | } |
1038 | 8dfdb87c | ths | FLOAT_OP(recip, s) |
1039 | 8dfdb87c | ths | { |
1040 | ead9360e | ths | set_float_exception_flags(0, &env->fpu->fp_status);
|
1041 | ead9360e | ths | FST2 = float32_div(FLOAT_ONE32, FST0, &env->fpu->fp_status); |
1042 | 8dfdb87c | ths | update_fcr31(); |
1043 | 57fa1fb3 | ths | } |
1044 | 57fa1fb3 | ths | |
1045 | 8dfdb87c | ths | FLOAT_OP(rsqrt, d) |
1046 | 8dfdb87c | ths | { |
1047 | ead9360e | ths | set_float_exception_flags(0, &env->fpu->fp_status);
|
1048 | ead9360e | ths | FDT2 = float64_sqrt(FDT0, &env->fpu->fp_status); |
1049 | ead9360e | ths | FDT2 = float64_div(FLOAT_ONE64, FDT2, &env->fpu->fp_status); |
1050 | 8dfdb87c | ths | update_fcr31(); |
1051 | 8dfdb87c | ths | } |
1052 | 8dfdb87c | ths | FLOAT_OP(rsqrt, s) |
1053 | 8dfdb87c | ths | { |
1054 | ead9360e | ths | set_float_exception_flags(0, &env->fpu->fp_status);
|
1055 | ead9360e | ths | FST2 = float32_sqrt(FST0, &env->fpu->fp_status); |
1056 | ead9360e | ths | FST2 = float32_div(FLOAT_ONE32, FST2, &env->fpu->fp_status); |
1057 | 8dfdb87c | ths | update_fcr31(); |
1058 | 8dfdb87c | ths | } |
1059 | 8dfdb87c | ths | |
1060 | 8dfdb87c | ths | FLOAT_OP(recip1, d) |
1061 | 8dfdb87c | ths | { |
1062 | ead9360e | ths | set_float_exception_flags(0, &env->fpu->fp_status);
|
1063 | ead9360e | ths | FDT2 = float64_div(FLOAT_ONE64, FDT0, &env->fpu->fp_status); |
1064 | 8dfdb87c | ths | update_fcr31(); |
1065 | 8dfdb87c | ths | } |
1066 | 8dfdb87c | ths | FLOAT_OP(recip1, s) |
1067 | 8dfdb87c | ths | { |
1068 | ead9360e | ths | set_float_exception_flags(0, &env->fpu->fp_status);
|
1069 | ead9360e | ths | FST2 = float32_div(FLOAT_ONE32, FST0, &env->fpu->fp_status); |
1070 | 8dfdb87c | ths | update_fcr31(); |
1071 | 8dfdb87c | ths | } |
1072 | 8dfdb87c | ths | FLOAT_OP(recip1, ps) |
1073 | 8dfdb87c | ths | { |
1074 | ead9360e | ths | set_float_exception_flags(0, &env->fpu->fp_status);
|
1075 | ead9360e | ths | FST2 = float32_div(FLOAT_ONE32, FST0, &env->fpu->fp_status); |
1076 | ead9360e | ths | FSTH2 = float32_div(FLOAT_ONE32, FSTH0, &env->fpu->fp_status); |
1077 | 8dfdb87c | ths | update_fcr31(); |
1078 | 8dfdb87c | ths | } |
1079 | 8dfdb87c | ths | |
1080 | 8dfdb87c | ths | FLOAT_OP(rsqrt1, d) |
1081 | 8dfdb87c | ths | { |
1082 | ead9360e | ths | set_float_exception_flags(0, &env->fpu->fp_status);
|
1083 | ead9360e | ths | FDT2 = float64_sqrt(FDT0, &env->fpu->fp_status); |
1084 | ead9360e | ths | FDT2 = float64_div(FLOAT_ONE64, FDT2, &env->fpu->fp_status); |
1085 | 8dfdb87c | ths | update_fcr31(); |
1086 | 8dfdb87c | ths | } |
1087 | 8dfdb87c | ths | FLOAT_OP(rsqrt1, s) |
1088 | 8dfdb87c | ths | { |
1089 | ead9360e | ths | set_float_exception_flags(0, &env->fpu->fp_status);
|
1090 | ead9360e | ths | FST2 = float32_sqrt(FST0, &env->fpu->fp_status); |
1091 | ead9360e | ths | FST2 = float32_div(FLOAT_ONE32, FST2, &env->fpu->fp_status); |
1092 | 8dfdb87c | ths | update_fcr31(); |
1093 | 8dfdb87c | ths | } |
1094 | 8dfdb87c | ths | FLOAT_OP(rsqrt1, ps) |
1095 | 8dfdb87c | ths | { |
1096 | ead9360e | ths | set_float_exception_flags(0, &env->fpu->fp_status);
|
1097 | ead9360e | ths | FST2 = float32_sqrt(FST0, &env->fpu->fp_status); |
1098 | ead9360e | ths | FSTH2 = float32_sqrt(FSTH0, &env->fpu->fp_status); |
1099 | ead9360e | ths | FST2 = float32_div(FLOAT_ONE32, FST2, &env->fpu->fp_status); |
1100 | ead9360e | ths | FSTH2 = float32_div(FLOAT_ONE32, FSTH2, &env->fpu->fp_status); |
1101 | 8dfdb87c | ths | update_fcr31(); |
1102 | 57fa1fb3 | ths | } |
1103 | 57fa1fb3 | ths | |
1104 | fd4a04eb | ths | /* binary operations */
|
1105 | fd4a04eb | ths | #define FLOAT_BINOP(name) \
|
1106 | fd4a04eb | ths | FLOAT_OP(name, d) \ |
1107 | fd4a04eb | ths | { \ |
1108 | ead9360e | ths | set_float_exception_flags(0, &env->fpu->fp_status); \
|
1109 | ead9360e | ths | FDT2 = float64_ ## name (FDT0, FDT1, &env->fpu->fp_status); \ |
1110 | ead9360e | ths | update_fcr31(); \ |
1111 | ead9360e | ths | if (GET_FP_CAUSE(env->fpu->fcr31) & FP_INVALID) \
|
1112 | 5747c073 | pbrook | DT2 = FLOAT_QNAN64; \ |
1113 | fd4a04eb | ths | } \ |
1114 | fd4a04eb | ths | FLOAT_OP(name, s) \ |
1115 | fd4a04eb | ths | { \ |
1116 | ead9360e | ths | set_float_exception_flags(0, &env->fpu->fp_status); \
|
1117 | ead9360e | ths | FST2 = float32_ ## name (FST0, FST1, &env->fpu->fp_status); \ |
1118 | ead9360e | ths | update_fcr31(); \ |
1119 | ead9360e | ths | if (GET_FP_CAUSE(env->fpu->fcr31) & FP_INVALID) \
|
1120 | 5747c073 | pbrook | WT2 = FLOAT_QNAN32; \ |
1121 | fd4a04eb | ths | } \ |
1122 | fd4a04eb | ths | FLOAT_OP(name, ps) \ |
1123 | fd4a04eb | ths | { \ |
1124 | ead9360e | ths | set_float_exception_flags(0, &env->fpu->fp_status); \
|
1125 | ead9360e | ths | FST2 = float32_ ## name (FST0, FST1, &env->fpu->fp_status); \ |
1126 | ead9360e | ths | FSTH2 = float32_ ## name (FSTH0, FSTH1, &env->fpu->fp_status); \ |
1127 | fd4a04eb | ths | update_fcr31(); \ |
1128 | ead9360e | ths | if (GET_FP_CAUSE(env->fpu->fcr31) & FP_INVALID) { \
|
1129 | 5747c073 | pbrook | WT2 = FLOAT_QNAN32; \ |
1130 | 5747c073 | pbrook | WTH2 = FLOAT_QNAN32; \ |
1131 | 3a5b360d | ths | } \ |
1132 | fd4a04eb | ths | } |
1133 | fd4a04eb | ths | FLOAT_BINOP(add) |
1134 | fd4a04eb | ths | FLOAT_BINOP(sub) |
1135 | fd4a04eb | ths | FLOAT_BINOP(mul) |
1136 | fd4a04eb | ths | FLOAT_BINOP(div) |
1137 | fd4a04eb | ths | #undef FLOAT_BINOP
|
1138 | fd4a04eb | ths | |
1139 | 8dfdb87c | ths | /* MIPS specific binary operations */
|
1140 | 8dfdb87c | ths | FLOAT_OP(recip2, d) |
1141 | 8dfdb87c | ths | { |
1142 | ead9360e | ths | set_float_exception_flags(0, &env->fpu->fp_status);
|
1143 | ead9360e | ths | FDT2 = float64_mul(FDT0, FDT2, &env->fpu->fp_status); |
1144 | 5747c073 | pbrook | FDT2 = float64_chs(float64_sub(FDT2, FLOAT_ONE64, &env->fpu->fp_status)); |
1145 | 8dfdb87c | ths | update_fcr31(); |
1146 | 8dfdb87c | ths | } |
1147 | 8dfdb87c | ths | FLOAT_OP(recip2, s) |
1148 | 8dfdb87c | ths | { |
1149 | ead9360e | ths | set_float_exception_flags(0, &env->fpu->fp_status);
|
1150 | ead9360e | ths | FST2 = float32_mul(FST0, FST2, &env->fpu->fp_status); |
1151 | 5747c073 | pbrook | FST2 = float32_chs(float32_sub(FST2, FLOAT_ONE32, &env->fpu->fp_status)); |
1152 | 8dfdb87c | ths | update_fcr31(); |
1153 | 8dfdb87c | ths | } |
1154 | 8dfdb87c | ths | FLOAT_OP(recip2, ps) |
1155 | 8dfdb87c | ths | { |
1156 | ead9360e | ths | set_float_exception_flags(0, &env->fpu->fp_status);
|
1157 | ead9360e | ths | FST2 = float32_mul(FST0, FST2, &env->fpu->fp_status); |
1158 | ead9360e | ths | FSTH2 = float32_mul(FSTH0, FSTH2, &env->fpu->fp_status); |
1159 | 5747c073 | pbrook | FST2 = float32_chs(float32_sub(FST2, FLOAT_ONE32, &env->fpu->fp_status)); |
1160 | 5747c073 | pbrook | FSTH2 = float32_chs(float32_sub(FSTH2, FLOAT_ONE32, &env->fpu->fp_status)); |
1161 | 8dfdb87c | ths | update_fcr31(); |
1162 | 8dfdb87c | ths | } |
1163 | 8dfdb87c | ths | |
1164 | 8dfdb87c | ths | FLOAT_OP(rsqrt2, d) |
1165 | 8dfdb87c | ths | { |
1166 | ead9360e | ths | set_float_exception_flags(0, &env->fpu->fp_status);
|
1167 | ead9360e | ths | FDT2 = float64_mul(FDT0, FDT2, &env->fpu->fp_status); |
1168 | ead9360e | ths | FDT2 = float64_sub(FDT2, FLOAT_ONE64, &env->fpu->fp_status); |
1169 | 5747c073 | pbrook | FDT2 = float64_chs(float64_div(FDT2, FLOAT_TWO64, &env->fpu->fp_status)); |
1170 | 8dfdb87c | ths | update_fcr31(); |
1171 | 8dfdb87c | ths | } |
1172 | 8dfdb87c | ths | FLOAT_OP(rsqrt2, s) |
1173 | 8dfdb87c | ths | { |
1174 | ead9360e | ths | set_float_exception_flags(0, &env->fpu->fp_status);
|
1175 | ead9360e | ths | FST2 = float32_mul(FST0, FST2, &env->fpu->fp_status); |
1176 | ead9360e | ths | FST2 = float32_sub(FST2, FLOAT_ONE32, &env->fpu->fp_status); |
1177 | 5747c073 | pbrook | FST2 = float32_chs(float32_div(FST2, FLOAT_TWO32, &env->fpu->fp_status)); |
1178 | 8dfdb87c | ths | update_fcr31(); |
1179 | 8dfdb87c | ths | } |
1180 | 8dfdb87c | ths | FLOAT_OP(rsqrt2, ps) |
1181 | 8dfdb87c | ths | { |
1182 | ead9360e | ths | set_float_exception_flags(0, &env->fpu->fp_status);
|
1183 | ead9360e | ths | FST2 = float32_mul(FST0, FST2, &env->fpu->fp_status); |
1184 | ead9360e | ths | FSTH2 = float32_mul(FSTH0, FSTH2, &env->fpu->fp_status); |
1185 | ead9360e | ths | FST2 = float32_sub(FST2, FLOAT_ONE32, &env->fpu->fp_status); |
1186 | ead9360e | ths | FSTH2 = float32_sub(FSTH2, FLOAT_ONE32, &env->fpu->fp_status); |
1187 | 5747c073 | pbrook | FST2 = float32_chs(float32_div(FST2, FLOAT_TWO32, &env->fpu->fp_status)); |
1188 | 5747c073 | pbrook | FSTH2 = float32_chs(float32_div(FSTH2, FLOAT_TWO32, &env->fpu->fp_status)); |
1189 | 8dfdb87c | ths | update_fcr31(); |
1190 | 57fa1fb3 | ths | } |
1191 | 57fa1fb3 | ths | |
1192 | fd4a04eb | ths | FLOAT_OP(addr, ps) |
1193 | fd4a04eb | ths | { |
1194 | ead9360e | ths | set_float_exception_flags(0, &env->fpu->fp_status);
|
1195 | ead9360e | ths | FST2 = float32_add (FST0, FSTH0, &env->fpu->fp_status); |
1196 | ead9360e | ths | FSTH2 = float32_add (FST1, FSTH1, &env->fpu->fp_status); |
1197 | fd4a04eb | ths | update_fcr31(); |
1198 | fd4a04eb | ths | } |
1199 | fd4a04eb | ths | |
1200 | 57fa1fb3 | ths | FLOAT_OP(mulr, ps) |
1201 | 57fa1fb3 | ths | { |
1202 | ead9360e | ths | set_float_exception_flags(0, &env->fpu->fp_status);
|
1203 | ead9360e | ths | FST2 = float32_mul (FST0, FSTH0, &env->fpu->fp_status); |
1204 | ead9360e | ths | FSTH2 = float32_mul (FST1, FSTH1, &env->fpu->fp_status); |
1205 | 57fa1fb3 | ths | update_fcr31(); |
1206 | 57fa1fb3 | ths | } |
1207 | 57fa1fb3 | ths | |
1208 | 8dfdb87c | ths | /* compare operations */
|
1209 | fd4a04eb | ths | #define FOP_COND_D(op, cond) \
|
1210 | fd4a04eb | ths | void do_cmp_d_ ## op (long cc) \ |
1211 | fd4a04eb | ths | { \ |
1212 | fd4a04eb | ths | int c = cond; \
|
1213 | fd4a04eb | ths | update_fcr31(); \ |
1214 | fd4a04eb | ths | if (c) \
|
1215 | ead9360e | ths | SET_FP_COND(cc, env->fpu); \ |
1216 | fd4a04eb | ths | else \
|
1217 | ead9360e | ths | CLEAR_FP_COND(cc, env->fpu); \ |
1218 | fd4a04eb | ths | } \ |
1219 | fd4a04eb | ths | void do_cmpabs_d_ ## op (long cc) \ |
1220 | fd4a04eb | ths | { \ |
1221 | fd4a04eb | ths | int c; \
|
1222 | 6b5435d7 | ths | FDT0 = float64_abs(FDT0); \ |
1223 | 6b5435d7 | ths | FDT1 = float64_abs(FDT1); \ |
1224 | fd4a04eb | ths | c = cond; \ |
1225 | fd4a04eb | ths | update_fcr31(); \ |
1226 | fd4a04eb | ths | if (c) \
|
1227 | ead9360e | ths | SET_FP_COND(cc, env->fpu); \ |
1228 | fd4a04eb | ths | else \
|
1229 | ead9360e | ths | CLEAR_FP_COND(cc, env->fpu); \ |
1230 | fd4a04eb | ths | } |
1231 | fd4a04eb | ths | |
1232 | fd4a04eb | ths | int float64_is_unordered(int sig, float64 a, float64 b STATUS_PARAM) |
1233 | fd4a04eb | ths | { |
1234 | fd4a04eb | ths | if (float64_is_signaling_nan(a) ||
|
1235 | fd4a04eb | ths | float64_is_signaling_nan(b) || |
1236 | fd4a04eb | ths | (sig && (float64_is_nan(a) || float64_is_nan(b)))) { |
1237 | fd4a04eb | ths | float_raise(float_flag_invalid, status); |
1238 | fd4a04eb | ths | return 1; |
1239 | fd4a04eb | ths | } else if (float64_is_nan(a) || float64_is_nan(b)) { |
1240 | fd4a04eb | ths | return 1; |
1241 | fd4a04eb | ths | } else {
|
1242 | fd4a04eb | ths | return 0; |
1243 | fd4a04eb | ths | } |
1244 | fd4a04eb | ths | } |
1245 | fd4a04eb | ths | |
1246 | fd4a04eb | ths | /* NOTE: the comma operator will make "cond" to eval to false,
|
1247 | fd4a04eb | ths | * but float*_is_unordered() is still called. */
|
1248 | ead9360e | ths | FOP_COND_D(f, (float64_is_unordered(0, FDT1, FDT0, &env->fpu->fp_status), 0)) |
1249 | ead9360e | ths | FOP_COND_D(un, float64_is_unordered(0, FDT1, FDT0, &env->fpu->fp_status))
|
1250 | ead9360e | ths | FOP_COND_D(eq, !float64_is_unordered(0, FDT1, FDT0, &env->fpu->fp_status) && float64_eq(FDT0, FDT1, &env->fpu->fp_status))
|
1251 | ead9360e | ths | FOP_COND_D(ueq, float64_is_unordered(0, FDT1, FDT0, &env->fpu->fp_status) || float64_eq(FDT0, FDT1, &env->fpu->fp_status))
|
1252 | ead9360e | ths | FOP_COND_D(olt, !float64_is_unordered(0, FDT1, FDT0, &env->fpu->fp_status) && float64_lt(FDT0, FDT1, &env->fpu->fp_status))
|
1253 | ead9360e | ths | FOP_COND_D(ult, float64_is_unordered(0, FDT1, FDT0, &env->fpu->fp_status) || float64_lt(FDT0, FDT1, &env->fpu->fp_status))
|
1254 | ead9360e | ths | FOP_COND_D(ole, !float64_is_unordered(0, FDT1, FDT0, &env->fpu->fp_status) && float64_le(FDT0, FDT1, &env->fpu->fp_status))
|
1255 | ead9360e | ths | FOP_COND_D(ule, float64_is_unordered(0, FDT1, FDT0, &env->fpu->fp_status) || float64_le(FDT0, FDT1, &env->fpu->fp_status))
|
1256 | fd4a04eb | ths | /* NOTE: the comma operator will make "cond" to eval to false,
|
1257 | fd4a04eb | ths | * but float*_is_unordered() is still called. */
|
1258 | ead9360e | ths | FOP_COND_D(sf, (float64_is_unordered(1, FDT1, FDT0, &env->fpu->fp_status), 0)) |
1259 | ead9360e | ths | FOP_COND_D(ngle,float64_is_unordered(1, FDT1, FDT0, &env->fpu->fp_status))
|
1260 | ead9360e | ths | FOP_COND_D(seq, !float64_is_unordered(1, FDT1, FDT0, &env->fpu->fp_status) && float64_eq(FDT0, FDT1, &env->fpu->fp_status))
|
1261 | ead9360e | ths | FOP_COND_D(ngl, float64_is_unordered(1, FDT1, FDT0, &env->fpu->fp_status) || float64_eq(FDT0, FDT1, &env->fpu->fp_status))
|
1262 | ead9360e | ths | FOP_COND_D(lt, !float64_is_unordered(1, FDT1, FDT0, &env->fpu->fp_status) && float64_lt(FDT0, FDT1, &env->fpu->fp_status))
|
1263 | ead9360e | ths | FOP_COND_D(nge, float64_is_unordered(1, FDT1, FDT0, &env->fpu->fp_status) || float64_lt(FDT0, FDT1, &env->fpu->fp_status))
|
1264 | ead9360e | ths | FOP_COND_D(le, !float64_is_unordered(1, FDT1, FDT0, &env->fpu->fp_status) && float64_le(FDT0, FDT1, &env->fpu->fp_status))
|
1265 | ead9360e | ths | FOP_COND_D(ngt, float64_is_unordered(1, FDT1, FDT0, &env->fpu->fp_status) || float64_le(FDT0, FDT1, &env->fpu->fp_status))
|
1266 | fd4a04eb | ths | |
1267 | fd4a04eb | ths | #define FOP_COND_S(op, cond) \
|
1268 | fd4a04eb | ths | void do_cmp_s_ ## op (long cc) \ |
1269 | fd4a04eb | ths | { \ |
1270 | fd4a04eb | ths | int c = cond; \
|
1271 | fd4a04eb | ths | update_fcr31(); \ |
1272 | fd4a04eb | ths | if (c) \
|
1273 | ead9360e | ths | SET_FP_COND(cc, env->fpu); \ |
1274 | fd4a04eb | ths | else \
|
1275 | ead9360e | ths | CLEAR_FP_COND(cc, env->fpu); \ |
1276 | fd4a04eb | ths | } \ |
1277 | fd4a04eb | ths | void do_cmpabs_s_ ## op (long cc) \ |
1278 | fd4a04eb | ths | { \ |
1279 | fd4a04eb | ths | int c; \
|
1280 | 5747c073 | pbrook | FST0 = float32_abs(FST0); \ |
1281 | 5747c073 | pbrook | FST1 = float32_abs(FST1); \ |
1282 | fd4a04eb | ths | c = cond; \ |
1283 | fd4a04eb | ths | update_fcr31(); \ |
1284 | fd4a04eb | ths | if (c) \
|
1285 | ead9360e | ths | SET_FP_COND(cc, env->fpu); \ |
1286 | fd4a04eb | ths | else \
|
1287 | ead9360e | ths | CLEAR_FP_COND(cc, env->fpu); \ |
1288 | fd4a04eb | ths | } |
1289 | fd4a04eb | ths | |
1290 | fd4a04eb | ths | flag float32_is_unordered(int sig, float32 a, float32 b STATUS_PARAM)
|
1291 | fd4a04eb | ths | { |
1292 | fd4a04eb | ths | if (float32_is_signaling_nan(a) ||
|
1293 | fd4a04eb | ths | float32_is_signaling_nan(b) || |
1294 | fd4a04eb | ths | (sig && (float32_is_nan(a) || float32_is_nan(b)))) { |
1295 | fd4a04eb | ths | float_raise(float_flag_invalid, status); |
1296 | fd4a04eb | ths | return 1; |
1297 | fd4a04eb | ths | } else if (float32_is_nan(a) || float32_is_nan(b)) { |
1298 | fd4a04eb | ths | return 1; |
1299 | fd4a04eb | ths | } else {
|
1300 | fd4a04eb | ths | return 0; |
1301 | fd4a04eb | ths | } |
1302 | fd4a04eb | ths | } |
1303 | fd4a04eb | ths | |
1304 | fd4a04eb | ths | /* NOTE: the comma operator will make "cond" to eval to false,
|
1305 | fd4a04eb | ths | * but float*_is_unordered() is still called. */
|
1306 | ead9360e | ths | FOP_COND_S(f, (float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status), 0)) |
1307 | ead9360e | ths | FOP_COND_S(un, float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status))
|
1308 | ead9360e | ths | FOP_COND_S(eq, !float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) && float32_eq(FST0, FST1, &env->fpu->fp_status))
|
1309 | ead9360e | ths | FOP_COND_S(ueq, float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) || float32_eq(FST0, FST1, &env->fpu->fp_status))
|
1310 | ead9360e | ths | FOP_COND_S(olt, !float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) && float32_lt(FST0, FST1, &env->fpu->fp_status))
|
1311 | ead9360e | ths | FOP_COND_S(ult, float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) || float32_lt(FST0, FST1, &env->fpu->fp_status))
|
1312 | ead9360e | ths | FOP_COND_S(ole, !float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) && float32_le(FST0, FST1, &env->fpu->fp_status))
|
1313 | ead9360e | ths | FOP_COND_S(ule, float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) || float32_le(FST0, FST1, &env->fpu->fp_status))
|
1314 | fd4a04eb | ths | /* NOTE: the comma operator will make "cond" to eval to false,
|
1315 | fd4a04eb | ths | * but float*_is_unordered() is still called. */
|
1316 | ead9360e | ths | FOP_COND_S(sf, (float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status), 0)) |
1317 | ead9360e | ths | FOP_COND_S(ngle,float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status))
|
1318 | ead9360e | ths | FOP_COND_S(seq, !float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) && float32_eq(FST0, FST1, &env->fpu->fp_status))
|
1319 | ead9360e | ths | FOP_COND_S(ngl, float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) || float32_eq(FST0, FST1, &env->fpu->fp_status))
|
1320 | ead9360e | ths | FOP_COND_S(lt, !float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) && float32_lt(FST0, FST1, &env->fpu->fp_status))
|
1321 | ead9360e | ths | FOP_COND_S(nge, float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) || float32_lt(FST0, FST1, &env->fpu->fp_status))
|
1322 | ead9360e | ths | FOP_COND_S(le, !float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) && float32_le(FST0, FST1, &env->fpu->fp_status))
|
1323 | ead9360e | ths | FOP_COND_S(ngt, float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) || float32_le(FST0, FST1, &env->fpu->fp_status))
|
1324 | fd4a04eb | ths | |
1325 | fd4a04eb | ths | #define FOP_COND_PS(op, condl, condh) \
|
1326 | fd4a04eb | ths | void do_cmp_ps_ ## op (long cc) \ |
1327 | fd4a04eb | ths | { \ |
1328 | fd4a04eb | ths | int cl = condl; \
|
1329 | fd4a04eb | ths | int ch = condh; \
|
1330 | fd4a04eb | ths | update_fcr31(); \ |
1331 | fd4a04eb | ths | if (cl) \
|
1332 | ead9360e | ths | SET_FP_COND(cc, env->fpu); \ |
1333 | fd4a04eb | ths | else \
|
1334 | ead9360e | ths | CLEAR_FP_COND(cc, env->fpu); \ |
1335 | fd4a04eb | ths | if (ch) \
|
1336 | ead9360e | ths | SET_FP_COND(cc + 1, env->fpu); \
|
1337 | fd4a04eb | ths | else \
|
1338 | ead9360e | ths | CLEAR_FP_COND(cc + 1, env->fpu); \
|
1339 | fd4a04eb | ths | } \ |
1340 | fd4a04eb | ths | void do_cmpabs_ps_ ## op (long cc) \ |
1341 | fd4a04eb | ths | { \ |
1342 | fd4a04eb | ths | int cl, ch; \
|
1343 | 5747c073 | pbrook | FST0 = float32_abs(FST0); \ |
1344 | 5747c073 | pbrook | FSTH0 = float32_abs(FSTH0); \ |
1345 | 5747c073 | pbrook | FST1 = float32_abs(FST1); \ |
1346 | 5747c073 | pbrook | FSTH1 = float32_abs(FSTH1); \ |
1347 | fd4a04eb | ths | cl = condl; \ |
1348 | fd4a04eb | ths | ch = condh; \ |
1349 | fd4a04eb | ths | update_fcr31(); \ |
1350 | fd4a04eb | ths | if (cl) \
|
1351 | ead9360e | ths | SET_FP_COND(cc, env->fpu); \ |
1352 | fd4a04eb | ths | else \
|
1353 | ead9360e | ths | CLEAR_FP_COND(cc, env->fpu); \ |
1354 | fd4a04eb | ths | if (ch) \
|
1355 | ead9360e | ths | SET_FP_COND(cc + 1, env->fpu); \
|
1356 | fd4a04eb | ths | else \
|
1357 | ead9360e | ths | CLEAR_FP_COND(cc + 1, env->fpu); \
|
1358 | fd4a04eb | ths | } |
1359 | fd4a04eb | ths | |
1360 | fd4a04eb | ths | /* NOTE: the comma operator will make "cond" to eval to false,
|
1361 | fd4a04eb | ths | * but float*_is_unordered() is still called. */
|
1362 | ead9360e | ths | FOP_COND_PS(f, (float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status), 0), |
1363 | ead9360e | ths | (float32_is_unordered(0, FSTH1, FSTH0, &env->fpu->fp_status), 0)) |
1364 | ead9360e | ths | FOP_COND_PS(un, float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status),
|
1365 | ead9360e | ths | float32_is_unordered(0, FSTH1, FSTH0, &env->fpu->fp_status))
|
1366 | ead9360e | ths | FOP_COND_PS(eq, !float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) && float32_eq(FST0, FST1, &env->fpu->fp_status),
|
1367 | ead9360e | ths | !float32_is_unordered(0, FSTH1, FSTH0, &env->fpu->fp_status) && float32_eq(FSTH0, FSTH1, &env->fpu->fp_status))
|
1368 | ead9360e | ths | FOP_COND_PS(ueq, float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) || float32_eq(FST0, FST1, &env->fpu->fp_status),
|
1369 | ead9360e | ths | float32_is_unordered(0, FSTH1, FSTH0, &env->fpu->fp_status) || float32_eq(FSTH0, FSTH1, &env->fpu->fp_status))
|
1370 | ead9360e | ths | FOP_COND_PS(olt, !float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) && float32_lt(FST0, FST1, &env->fpu->fp_status),
|
1371 | ead9360e | ths | !float32_is_unordered(0, FSTH1, FSTH0, &env->fpu->fp_status) && float32_lt(FSTH0, FSTH1, &env->fpu->fp_status))
|
1372 | ead9360e | ths | FOP_COND_PS(ult, float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) || float32_lt(FST0, FST1, &env->fpu->fp_status),
|
1373 | ead9360e | ths | float32_is_unordered(0, FSTH1, FSTH0, &env->fpu->fp_status) || float32_lt(FSTH0, FSTH1, &env->fpu->fp_status))
|
1374 | ead9360e | ths | FOP_COND_PS(ole, !float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) && float32_le(FST0, FST1, &env->fpu->fp_status),
|
1375 | ead9360e | ths | !float32_is_unordered(0, FSTH1, FSTH0, &env->fpu->fp_status) && float32_le(FSTH0, FSTH1, &env->fpu->fp_status))
|
1376 | ead9360e | ths | FOP_COND_PS(ule, float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) || float32_le(FST0, FST1, &env->fpu->fp_status),
|
1377 | ead9360e | ths | float32_is_unordered(0, FSTH1, FSTH0, &env->fpu->fp_status) || float32_le(FSTH0, FSTH1, &env->fpu->fp_status))
|
1378 | fd4a04eb | ths | /* NOTE: the comma operator will make "cond" to eval to false,
|
1379 | fd4a04eb | ths | * but float*_is_unordered() is still called. */
|
1380 | ead9360e | ths | FOP_COND_PS(sf, (float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status), 0), |
1381 | ead9360e | ths | (float32_is_unordered(1, FSTH1, FSTH0, &env->fpu->fp_status), 0)) |
1382 | ead9360e | ths | FOP_COND_PS(ngle,float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status),
|
1383 | ead9360e | ths | float32_is_unordered(1, FSTH1, FSTH0, &env->fpu->fp_status))
|
1384 | ead9360e | ths | FOP_COND_PS(seq, !float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) && float32_eq(FST0, FST1, &env->fpu->fp_status),
|
1385 | ead9360e | ths | !float32_is_unordered(1, FSTH1, FSTH0, &env->fpu->fp_status) && float32_eq(FSTH0, FSTH1, &env->fpu->fp_status))
|
1386 | ead9360e | ths | FOP_COND_PS(ngl, float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) || float32_eq(FST0, FST1, &env->fpu->fp_status),
|
1387 | ead9360e | ths | float32_is_unordered(1, FSTH1, FSTH0, &env->fpu->fp_status) || float32_eq(FSTH0, FSTH1, &env->fpu->fp_status))
|
1388 | ead9360e | ths | FOP_COND_PS(lt, !float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) && float32_lt(FST0, FST1, &env->fpu->fp_status),
|
1389 | ead9360e | ths | !float32_is_unordered(1, FSTH1, FSTH0, &env->fpu->fp_status) && float32_lt(FSTH0, FSTH1, &env->fpu->fp_status))
|
1390 | ead9360e | ths | FOP_COND_PS(nge, float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) || float32_lt(FST0, FST1, &env->fpu->fp_status),
|
1391 | ead9360e | ths | float32_is_unordered(1, FSTH1, FSTH0, &env->fpu->fp_status) || float32_lt(FSTH0, FSTH1, &env->fpu->fp_status))
|
1392 | ead9360e | ths | FOP_COND_PS(le, !float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) && float32_le(FST0, FST1, &env->fpu->fp_status),
|
1393 | ead9360e | ths | !float32_is_unordered(1, FSTH1, FSTH0, &env->fpu->fp_status) && float32_le(FSTH0, FSTH1, &env->fpu->fp_status))
|
1394 | ead9360e | ths | FOP_COND_PS(ngt, float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) || float32_le(FST0, FST1, &env->fpu->fp_status),
|
1395 | ead9360e | ths | float32_is_unordered(1, FSTH1, FSTH0, &env->fpu->fp_status) || float32_le(FSTH0, FSTH1, &env->fpu->fp_status)) |