root / hw / usb-uhci.c @ a594cfbf
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/*
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* USB UHCI controller emulation
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*
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* Copyright (c) 2005 Fabrice Bellard
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "vl.h" |
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//#define DEBUG
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//#define DEBUG_PACKET
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#define UHCI_CMD_GRESET (1 << 2) |
30 |
#define UHCI_CMD_HCRESET (1 << 1) |
31 |
#define UHCI_CMD_RS (1 << 0) |
32 |
|
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#define UHCI_STS_HCHALTED (1 << 5) |
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#define UHCI_STS_HCPERR (1 << 4) |
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#define UHCI_STS_HSERR (1 << 3) |
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#define UHCI_STS_RD (1 << 2) |
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#define UHCI_STS_USBERR (1 << 1) |
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#define UHCI_STS_USBINT (1 << 0) |
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|
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#define TD_CTRL_SPD (1 << 29) |
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#define TD_CTRL_ERROR_SHIFT 27 |
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#define TD_CTRL_IOS (1 << 25) |
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#define TD_CTRL_IOC (1 << 24) |
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#define TD_CTRL_ACTIVE (1 << 23) |
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#define TD_CTRL_STALL (1 << 22) |
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#define TD_CTRL_BABBLE (1 << 20) |
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#define TD_CTRL_NAK (1 << 19) |
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#define TD_CTRL_TIMEOUT (1 << 18) |
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|
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#define UHCI_PORT_RESET (1 << 9) |
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#define UHCI_PORT_LSDA (1 << 8) |
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#define UHCI_PORT_ENC (1 << 3) |
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#define UHCI_PORT_EN (1 << 2) |
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#define UHCI_PORT_CSC (1 << 1) |
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#define UHCI_PORT_CCS (1 << 0) |
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|
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#define FRAME_TIMER_FREQ 1000 |
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|
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#define FRAME_MAX_LOOPS 100 |
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#define NB_PORTS 2 |
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typedef struct UHCIPort { |
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USBPort port; |
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uint16_t ctrl; |
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} UHCIPort; |
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typedef struct UHCIState { |
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PCIDevice dev; |
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uint16_t cmd; /* cmd register */
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uint16_t status; |
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uint16_t intr; /* interrupt enable register */
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uint16_t frnum; /* frame number */
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uint32_t fl_base_addr; /* frame list base address */
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uint8_t sof_timing; |
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uint8_t status2; /* bit 0 and 1 are used to generate UHCI_STS_USBINT */
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QEMUTimer *frame_timer; |
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UHCIPort ports[NB_PORTS]; |
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} UHCIState; |
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typedef struct UHCI_TD { |
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uint32_t link; |
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uint32_t ctrl; /* see TD_CTRL_xxx */
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uint32_t token; |
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uint32_t buffer; |
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} UHCI_TD; |
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typedef struct UHCI_QH { |
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uint32_t link; |
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uint32_t el_link; |
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} UHCI_QH; |
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|
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static void uhci_attach(USBPort *port1, USBDevice *dev); |
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static void uhci_update_irq(UHCIState *s) |
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{ |
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int level;
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if (((s->status2 & 1) && (s->intr & (1 << 2))) || |
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((s->status2 & 2) && (s->intr & (1 << 3))) || |
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((s->status & UHCI_STS_USBERR) && (s->intr & (1 << 0))) || |
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((s->status & UHCI_STS_RD) && (s->intr & (1 << 1))) || |
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(s->status & UHCI_STS_HSERR) || |
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(s->status & UHCI_STS_HCPERR)) { |
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level = 1;
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} else {
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level = 0;
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} |
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pci_set_irq(&s->dev, 3, level);
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} |
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static void uhci_reset(UHCIState *s) |
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{ |
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uint8_t *pci_conf; |
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int i;
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UHCIPort *port; |
116 |
|
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pci_conf = s->dev.config; |
118 |
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pci_conf[0x6a] = 0x01; /* usb clock */ |
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pci_conf[0x6b] = 0x00; |
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s->cmd = 0;
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s->status = 0;
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s->status2 = 0;
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s->intr = 0;
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s->fl_base_addr = 0;
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s->sof_timing = 64;
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for(i = 0; i < NB_PORTS; i++) { |
128 |
port = &s->ports[i]; |
129 |
port->ctrl = 0x0080;
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if (port->port.dev)
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uhci_attach(&port->port, port->port.dev); |
132 |
} |
133 |
} |
134 |
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static void uhci_ioport_writeb(void *opaque, uint32_t addr, uint32_t val) |
136 |
{ |
137 |
UHCIState *s = opaque; |
138 |
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addr &= 0x1f;
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switch(addr) {
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case 0x0c: |
142 |
s->sof_timing = val; |
143 |
break;
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} |
145 |
} |
146 |
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static uint32_t uhci_ioport_readb(void *opaque, uint32_t addr) |
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{ |
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UHCIState *s = opaque; |
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uint32_t val; |
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addr &= 0x1f;
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switch(addr) {
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case 0x0c: |
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val = s->sof_timing; |
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default:
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val = 0xff;
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break;
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} |
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return val;
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} |
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static void uhci_ioport_writew(void *opaque, uint32_t addr, uint32_t val) |
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{ |
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UHCIState *s = opaque; |
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addr &= 0x1f;
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#ifdef DEBUG
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printf("uhci writew port=0x%04x val=0x%04x\n", addr, val);
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#endif
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switch(addr) {
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case 0x00: |
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if ((val & UHCI_CMD_RS) && !(s->cmd & UHCI_CMD_RS)) {
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/* start frame processing */
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qemu_mod_timer(s->frame_timer, qemu_get_clock(vm_clock)); |
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} |
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if (val & UHCI_CMD_GRESET) {
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UHCIPort *port; |
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USBDevice *dev; |
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int i;
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/* send reset on the USB bus */
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for(i = 0; i < NB_PORTS; i++) { |
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port = &s->ports[i]; |
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dev = port->port.dev; |
186 |
if (dev) {
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dev->handle_packet(dev, |
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USB_MSG_RESET, 0, 0, NULL, 0); |
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} |
190 |
} |
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uhci_reset(s); |
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return;
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} |
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if (val & UHCI_CMD_GRESET) {
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uhci_reset(s); |
196 |
return;
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} |
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s->cmd = val; |
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break;
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case 0x02: |
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s->status &= ~val; |
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/* XXX: the chip spec is not coherent, so we add a hidden
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register to distinguish between IOC and SPD */
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if (val & UHCI_STS_USBINT)
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s->status2 = 0;
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uhci_update_irq(s); |
207 |
break;
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case 0x04: |
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s->intr = val; |
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uhci_update_irq(s); |
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break;
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case 0x06: |
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if (s->status & UHCI_STS_HCHALTED)
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s->frnum = val & 0x7ff;
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break;
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case 0x10 ... 0x1f: |
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{ |
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UHCIPort *port; |
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USBDevice *dev; |
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int n;
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n = (addr >> 1) & 7; |
223 |
if (n >= NB_PORTS)
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return;
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port = &s->ports[n]; |
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dev = port->port.dev; |
227 |
if (dev) {
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/* port reset */
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if ( (val & UHCI_PORT_RESET) &&
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!(port->ctrl & UHCI_PORT_RESET) ) { |
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dev->handle_packet(dev, |
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USB_MSG_RESET, 0, 0, NULL, 0); |
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} |
234 |
} |
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port->ctrl = (port->ctrl & 0x01fb) | (val & ~0x01fb); |
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/* some bits are reset when a '1' is written to them */
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port->ctrl &= ~(val & 0x000a);
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} |
239 |
break;
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} |
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} |
242 |
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static uint32_t uhci_ioport_readw(void *opaque, uint32_t addr) |
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{ |
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UHCIState *s = opaque; |
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uint32_t val; |
247 |
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addr &= 0x1f;
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switch(addr) {
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case 0x00: |
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val = s->cmd; |
252 |
break;
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case 0x02: |
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val = s->status; |
255 |
break;
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case 0x04: |
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val = s->intr; |
258 |
break;
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case 0x06: |
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val = s->frnum; |
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break;
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case 0x10 ... 0x1f: |
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{ |
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UHCIPort *port; |
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int n;
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n = (addr >> 1) & 7; |
267 |
if (n >= NB_PORTS)
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goto read_default;
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port = &s->ports[n]; |
270 |
val = port->ctrl; |
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} |
272 |
break;
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default:
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read_default:
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val = 0xff7f; /* disabled port */ |
276 |
break;
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} |
278 |
#ifdef DEBUG
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printf("uhci readw port=0x%04x val=0x%04x\n", addr, val);
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#endif
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return val;
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} |
283 |
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static void uhci_ioport_writel(void *opaque, uint32_t addr, uint32_t val) |
285 |
{ |
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UHCIState *s = opaque; |
287 |
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addr &= 0x1f;
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#ifdef DEBUG
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printf("uhci writel port=0x%04x val=0x%08x\n", addr, val);
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#endif
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switch(addr) {
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case 0x08: |
294 |
s->fl_base_addr = val & ~0xfff;
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break;
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} |
297 |
} |
298 |
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static uint32_t uhci_ioport_readl(void *opaque, uint32_t addr) |
300 |
{ |
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UHCIState *s = opaque; |
302 |
uint32_t val; |
303 |
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addr &= 0x1f;
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switch(addr) {
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306 |
case 0x08: |
307 |
val = s->fl_base_addr; |
308 |
break;
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309 |
default:
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val = 0xffffffff;
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break;
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312 |
} |
313 |
return val;
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314 |
} |
315 |
|
316 |
static void uhci_attach(USBPort *port1, USBDevice *dev) |
317 |
{ |
318 |
UHCIState *s = port1->opaque; |
319 |
UHCIPort *port = &s->ports[port1->index]; |
320 |
|
321 |
if (dev) {
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322 |
if (port->port.dev) {
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323 |
usb_attach(port1, NULL);
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324 |
} |
325 |
/* set connect status */
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326 |
if (!(port->ctrl & UHCI_PORT_CCS)) {
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327 |
port->ctrl |= UHCI_PORT_CCS | UHCI_PORT_CSC; |
328 |
} |
329 |
/* update speed */
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330 |
if (dev->speed == USB_SPEED_LOW)
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331 |
port->ctrl |= UHCI_PORT_LSDA; |
332 |
else
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333 |
port->ctrl &= ~UHCI_PORT_LSDA; |
334 |
port->port.dev = dev; |
335 |
/* send the attach message */
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336 |
dev->handle_packet(dev, |
337 |
USB_MSG_ATTACH, 0, 0, NULL, 0); |
338 |
} else {
|
339 |
/* set connect status */
|
340 |
if (!(port->ctrl & UHCI_PORT_CCS)) {
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341 |
port->ctrl |= UHCI_PORT_CCS | UHCI_PORT_CSC; |
342 |
} |
343 |
/* disable port */
|
344 |
if (port->ctrl & UHCI_PORT_EN) {
|
345 |
port->ctrl &= ~UHCI_PORT_EN; |
346 |
port->ctrl |= UHCI_PORT_ENC; |
347 |
} |
348 |
dev = port->port.dev; |
349 |
if (dev) {
|
350 |
/* send the detach message */
|
351 |
dev->handle_packet(dev, |
352 |
USB_MSG_DETACH, 0, 0, NULL, 0); |
353 |
} |
354 |
port->port.dev = NULL;
|
355 |
} |
356 |
} |
357 |
|
358 |
static int uhci_broadcast_packet(UHCIState *s, uint8_t pid, |
359 |
uint8_t devaddr, uint8_t devep, |
360 |
uint8_t *data, int len)
|
361 |
{ |
362 |
UHCIPort *port; |
363 |
USBDevice *dev; |
364 |
int i, ret;
|
365 |
|
366 |
#ifdef DEBUG_PACKET
|
367 |
{ |
368 |
const char *pidstr; |
369 |
switch(pid) {
|
370 |
case USB_TOKEN_SETUP: pidstr = "SETUP"; break; |
371 |
case USB_TOKEN_IN: pidstr = "IN"; break; |
372 |
case USB_TOKEN_OUT: pidstr = "OUT"; break; |
373 |
default: pidstr = "?"; break; |
374 |
} |
375 |
printf("frame %d: pid=%s addr=0x%02x ep=%d len=%d\n",
|
376 |
s->frnum, pidstr, devaddr, devep, len); |
377 |
if (pid != USB_TOKEN_IN) {
|
378 |
printf(" data_out=");
|
379 |
for(i = 0; i < len; i++) { |
380 |
printf(" %02x", data[i]);
|
381 |
} |
382 |
printf("\n");
|
383 |
} |
384 |
} |
385 |
#endif
|
386 |
for(i = 0; i < NB_PORTS; i++) { |
387 |
port = &s->ports[i]; |
388 |
dev = port->port.dev; |
389 |
if (dev && (port->ctrl & UHCI_PORT_EN)) {
|
390 |
ret = dev->handle_packet(dev, pid, |
391 |
devaddr, devep, |
392 |
data, len); |
393 |
if (ret != USB_RET_NODEV) {
|
394 |
#ifdef DEBUG_PACKET
|
395 |
{ |
396 |
printf(" ret=%d ", ret);
|
397 |
if (pid == USB_TOKEN_IN && ret > 0) { |
398 |
printf("data_in=");
|
399 |
for(i = 0; i < ret; i++) { |
400 |
printf(" %02x", data[i]);
|
401 |
} |
402 |
} |
403 |
printf("\n");
|
404 |
} |
405 |
#endif
|
406 |
return ret;
|
407 |
} |
408 |
} |
409 |
} |
410 |
return USB_RET_NODEV;
|
411 |
} |
412 |
|
413 |
/* return -1 if fatal error (frame must be stopped)
|
414 |
0 if TD successful
|
415 |
1 if TD unsuccessful or inactive
|
416 |
*/
|
417 |
static int uhci_handle_td(UHCIState *s, UHCI_TD *td, int *int_mask) |
418 |
{ |
419 |
uint8_t pid; |
420 |
uint8_t buf[1280];
|
421 |
int len, max_len, err, ret;
|
422 |
|
423 |
if (td->ctrl & TD_CTRL_IOC) {
|
424 |
*int_mask |= 0x01;
|
425 |
} |
426 |
|
427 |
if (!(td->ctrl & TD_CTRL_ACTIVE))
|
428 |
return 1; |
429 |
|
430 |
/* TD is active */
|
431 |
max_len = ((td->token >> 21) + 1) & 0x7ff; |
432 |
pid = td->token & 0xff;
|
433 |
switch(pid) {
|
434 |
case USB_TOKEN_OUT:
|
435 |
case USB_TOKEN_SETUP:
|
436 |
cpu_physical_memory_read(td->buffer, buf, max_len); |
437 |
ret = uhci_broadcast_packet(s, pid, |
438 |
(td->token >> 8) & 0x7f, |
439 |
(td->token >> 15) & 0xf, |
440 |
buf, max_len); |
441 |
len = max_len; |
442 |
break;
|
443 |
case USB_TOKEN_IN:
|
444 |
ret = uhci_broadcast_packet(s, pid, |
445 |
(td->token >> 8) & 0x7f, |
446 |
(td->token >> 15) & 0xf, |
447 |
buf, max_len); |
448 |
if (ret >= 0) { |
449 |
len = ret; |
450 |
if (len > max_len) {
|
451 |
len = max_len; |
452 |
ret = USB_RET_BABBLE; |
453 |
} |
454 |
if (len > 0) { |
455 |
/* write the data back */
|
456 |
cpu_physical_memory_write(td->buffer, buf, len); |
457 |
} |
458 |
} else {
|
459 |
len = 0;
|
460 |
} |
461 |
break;
|
462 |
default:
|
463 |
/* invalid pid : frame interrupted */
|
464 |
s->status |= UHCI_STS_HCPERR; |
465 |
uhci_update_irq(s); |
466 |
return -1; |
467 |
} |
468 |
if (td->ctrl & TD_CTRL_IOS)
|
469 |
td->ctrl &= ~TD_CTRL_ACTIVE; |
470 |
if (ret >= 0) { |
471 |
td->ctrl = (td->ctrl & ~0x7ff) | ((len - 1) & 0x7ff); |
472 |
td->ctrl &= ~TD_CTRL_ACTIVE; |
473 |
if (pid == USB_TOKEN_IN &&
|
474 |
(td->ctrl & TD_CTRL_SPD) && |
475 |
len < max_len) { |
476 |
*int_mask |= 0x02;
|
477 |
/* short packet: do not update QH */
|
478 |
return 1; |
479 |
} else {
|
480 |
/* success */
|
481 |
return 0; |
482 |
} |
483 |
} else {
|
484 |
switch(ret) {
|
485 |
default:
|
486 |
case USB_RET_NODEV:
|
487 |
do_timeout:
|
488 |
td->ctrl |= TD_CTRL_TIMEOUT; |
489 |
err = (td->ctrl >> TD_CTRL_ERROR_SHIFT) & 3;
|
490 |
if (err != 0) { |
491 |
err--; |
492 |
if (err == 0) { |
493 |
td->ctrl &= ~TD_CTRL_ACTIVE; |
494 |
s->status |= UHCI_STS_USBERR; |
495 |
uhci_update_irq(s); |
496 |
} |
497 |
} |
498 |
td->ctrl = (td->ctrl & ~(3 << TD_CTRL_ERROR_SHIFT)) |
|
499 |
(err << TD_CTRL_ERROR_SHIFT); |
500 |
return 1; |
501 |
case USB_RET_NAK:
|
502 |
td->ctrl |= TD_CTRL_NAK; |
503 |
if (pid == USB_TOKEN_SETUP)
|
504 |
goto do_timeout;
|
505 |
return 1; |
506 |
case USB_RET_STALL:
|
507 |
td->ctrl |= TD_CTRL_STALL; |
508 |
td->ctrl &= ~TD_CTRL_ACTIVE; |
509 |
return 1; |
510 |
case USB_RET_BABBLE:
|
511 |
td->ctrl |= TD_CTRL_BABBLE | TD_CTRL_STALL; |
512 |
td->ctrl &= ~TD_CTRL_ACTIVE; |
513 |
/* frame interrupted */
|
514 |
return -1; |
515 |
} |
516 |
} |
517 |
} |
518 |
|
519 |
static void uhci_frame_timer(void *opaque) |
520 |
{ |
521 |
UHCIState *s = opaque; |
522 |
int64_t expire_time; |
523 |
uint32_t frame_addr, link, old_td_ctrl, val; |
524 |
int int_mask, cnt, ret;
|
525 |
UHCI_TD td; |
526 |
UHCI_QH qh; |
527 |
|
528 |
if (!(s->cmd & UHCI_CMD_RS)) {
|
529 |
qemu_del_timer(s->frame_timer); |
530 |
return;
|
531 |
} |
532 |
frame_addr = s->fl_base_addr + ((s->frnum & 0x3ff) << 2); |
533 |
cpu_physical_memory_read(frame_addr, (uint8_t *)&link, 4);
|
534 |
le32_to_cpus(&link); |
535 |
int_mask = 0;
|
536 |
cnt = FRAME_MAX_LOOPS; |
537 |
while ((link & 1) == 0) { |
538 |
if (--cnt == 0) |
539 |
break;
|
540 |
/* valid frame */
|
541 |
if (link & 2) { |
542 |
/* QH */
|
543 |
cpu_physical_memory_read(link & ~0xf, (uint8_t *)&qh, sizeof(qh)); |
544 |
le32_to_cpus(&qh.link); |
545 |
le32_to_cpus(&qh.el_link); |
546 |
depth_first:
|
547 |
if (qh.el_link & 1) { |
548 |
/* no element : go to next entry */
|
549 |
link = qh.link; |
550 |
} else if (qh.el_link & 2) { |
551 |
/* QH */
|
552 |
link = qh.el_link; |
553 |
} else {
|
554 |
/* TD */
|
555 |
if (--cnt == 0) |
556 |
break;
|
557 |
cpu_physical_memory_read(qh.el_link & ~0xf,
|
558 |
(uint8_t *)&td, sizeof(td));
|
559 |
le32_to_cpus(&td.link); |
560 |
le32_to_cpus(&td.ctrl); |
561 |
le32_to_cpus(&td.token); |
562 |
le32_to_cpus(&td.buffer); |
563 |
old_td_ctrl = td.ctrl; |
564 |
ret = uhci_handle_td(s, &td, &int_mask); |
565 |
/* update the status bits of the TD */
|
566 |
if (old_td_ctrl != td.ctrl) {
|
567 |
val = cpu_to_le32(td.ctrl); |
568 |
cpu_physical_memory_write((qh.el_link & ~0xf) + 4, |
569 |
(const uint8_t *)&val,
|
570 |
sizeof(val));
|
571 |
} |
572 |
if (ret < 0) |
573 |
break; /* interrupted frame */ |
574 |
if (ret == 0) { |
575 |
/* update qh element link */
|
576 |
qh.el_link = td.link; |
577 |
val = cpu_to_le32(qh.el_link); |
578 |
cpu_physical_memory_write((link & ~0xf) + 4, |
579 |
(const uint8_t *)&val,
|
580 |
sizeof(val));
|
581 |
if (qh.el_link & 4) { |
582 |
/* depth first */
|
583 |
goto depth_first;
|
584 |
} |
585 |
} |
586 |
/* go to next entry */
|
587 |
link = qh.link; |
588 |
} |
589 |
} else {
|
590 |
/* TD */
|
591 |
cpu_physical_memory_read(link & ~0xf, (uint8_t *)&td, sizeof(td)); |
592 |
le32_to_cpus(&td.link); |
593 |
le32_to_cpus(&td.ctrl); |
594 |
le32_to_cpus(&td.token); |
595 |
le32_to_cpus(&td.buffer); |
596 |
old_td_ctrl = td.ctrl; |
597 |
ret = uhci_handle_td(s, &td, &int_mask); |
598 |
/* update the status bits of the TD */
|
599 |
if (old_td_ctrl != td.ctrl) {
|
600 |
val = cpu_to_le32(td.ctrl); |
601 |
cpu_physical_memory_write((link & ~0xf) + 4, |
602 |
(const uint8_t *)&val,
|
603 |
sizeof(val));
|
604 |
} |
605 |
if (ret < 0) |
606 |
break; /* interrupted frame */ |
607 |
link = td.link; |
608 |
} |
609 |
} |
610 |
s->frnum = (s->frnum + 1) & 0x7ff; |
611 |
if (int_mask) {
|
612 |
s->status2 |= int_mask; |
613 |
s->status |= UHCI_STS_USBINT; |
614 |
uhci_update_irq(s); |
615 |
} |
616 |
/* prepare the timer for the next frame */
|
617 |
expire_time = qemu_get_clock(vm_clock) + |
618 |
(ticks_per_sec / FRAME_TIMER_FREQ); |
619 |
qemu_mod_timer(s->frame_timer, expire_time); |
620 |
} |
621 |
|
622 |
static void uhci_map(PCIDevice *pci_dev, int region_num, |
623 |
uint32_t addr, uint32_t size, int type)
|
624 |
{ |
625 |
UHCIState *s = (UHCIState *)pci_dev; |
626 |
|
627 |
register_ioport_write(addr, 32, 2, uhci_ioport_writew, s); |
628 |
register_ioport_read(addr, 32, 2, uhci_ioport_readw, s); |
629 |
register_ioport_write(addr, 32, 4, uhci_ioport_writel, s); |
630 |
register_ioport_read(addr, 32, 4, uhci_ioport_readl, s); |
631 |
register_ioport_write(addr, 32, 1, uhci_ioport_writeb, s); |
632 |
register_ioport_read(addr, 32, 1, uhci_ioport_readb, s); |
633 |
} |
634 |
|
635 |
void usb_uhci_init(PCIBus *bus, USBPort **usb_ports)
|
636 |
{ |
637 |
UHCIState *s; |
638 |
uint8_t *pci_conf; |
639 |
UHCIPort *port; |
640 |
int i;
|
641 |
|
642 |
s = (UHCIState *)pci_register_device(bus, |
643 |
"USB-UHCI", sizeof(UHCIState), |
644 |
((PCIDevice *)piix3_state)->devfn + 2,
|
645 |
NULL, NULL); |
646 |
pci_conf = s->dev.config; |
647 |
pci_conf[0x00] = 0x86; |
648 |
pci_conf[0x01] = 0x80; |
649 |
pci_conf[0x02] = 0x20; |
650 |
pci_conf[0x03] = 0x70; |
651 |
pci_conf[0x08] = 0x01; // revision number |
652 |
pci_conf[0x09] = 0x00; |
653 |
pci_conf[0x0a] = 0x03; |
654 |
pci_conf[0x0b] = 0x0c; |
655 |
pci_conf[0x0e] = 0x00; // header_type |
656 |
pci_conf[0x3d] = 4; // interrupt pin 3 |
657 |
|
658 |
for(i = 0; i < NB_PORTS; i++) { |
659 |
port = &s->ports[i]; |
660 |
port->port.opaque = s; |
661 |
port->port.index = i; |
662 |
port->port.attach = uhci_attach; |
663 |
usb_ports[i] = &port->port; |
664 |
} |
665 |
s->frame_timer = qemu_new_timer(vm_clock, uhci_frame_timer, s); |
666 |
|
667 |
uhci_reset(s); |
668 |
|
669 |
pci_register_io_region(&s->dev, 0, 0x20, |
670 |
PCI_ADDRESS_SPACE_IO, uhci_map); |
671 |
} |